ARM: cache: remove ARMv3 support code
This is only used by 740t, which is a v4 core and (by my reading of the datasheet for the CPU) ignores CRm for the cp15 cache flush operation, making the v4 cache implementation in cache-v4.S sufficient for this CPU. Tested with 740T core-tile on Integrator/AP baseboard. Acked-by: Hyok S. Choi <hyok.choi@samsung.com> Acked-by: Greg Ungerer <gerg@uclinux.org> Signed-off-by: Will Deacon <will.deacon@arm.com>
This commit is contained in:
Will Deacon
Родитель
4cc3daaf39
Коммит
82d9b0d0c6
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@ -19,14 +19,6 @@
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#undef _CACHE
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#undef MULTI_CACHE
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#if defined(CONFIG_CPU_CACHE_V3)
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# ifdef _CACHE
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# define MULTI_CACHE 1
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# else
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# define _CACHE v3
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# endif
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#endif
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#if defined(CONFIG_CPU_CACHE_V4)
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# ifdef _CACHE
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# define MULTI_CACHE 1
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@ -43,7 +43,7 @@ config CPU_ARM740T
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depends on !MMU
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select CPU_32v4T
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select CPU_ABRT_LV4T
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select CPU_CACHE_V3 # although the core is v4t
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select CPU_CACHE_V4
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select CPU_CP15_MPU
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select CPU_PABRT_LEGACY
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help
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@ -469,9 +469,6 @@ config CPU_PABRT_V7
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bool
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# The cache model
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config CPU_CACHE_V3
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bool
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config CPU_CACHE_V4
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bool
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@ -33,7 +33,6 @@ obj-$(CONFIG_CPU_PABRT_LEGACY) += pabort-legacy.o
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obj-$(CONFIG_CPU_PABRT_V6) += pabort-v6.o
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obj-$(CONFIG_CPU_PABRT_V7) += pabort-v7.o
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obj-$(CONFIG_CPU_CACHE_V3) += cache-v3.o
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obj-$(CONFIG_CPU_CACHE_V4) += cache-v4.o
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obj-$(CONFIG_CPU_CACHE_V4WT) += cache-v4wt.o
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obj-$(CONFIG_CPU_CACHE_V4WB) += cache-v4wb.o
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@ -1,137 +0,0 @@
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/*
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* linux/arch/arm/mm/cache-v3.S
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*
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* Copyright (C) 1997-2002 Russell king
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/linkage.h>
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#include <linux/init.h>
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#include <asm/page.h>
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#include "proc-macros.S"
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/*
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* flush_icache_all()
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*
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* Unconditionally clean and invalidate the entire icache.
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*/
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ENTRY(v3_flush_icache_all)
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mov pc, lr
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ENDPROC(v3_flush_icache_all)
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/*
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* flush_user_cache_all()
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*
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* Invalidate all cache entries in a particular address
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* space.
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*
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* - mm - mm_struct describing address space
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*/
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ENTRY(v3_flush_user_cache_all)
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/* FALLTHROUGH */
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/*
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* flush_kern_cache_all()
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*
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* Clean and invalidate the entire cache.
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*/
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ENTRY(v3_flush_kern_cache_all)
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/* FALLTHROUGH */
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/*
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* flush_user_cache_range(start, end, flags)
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*
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* Invalidate a range of cache entries in the specified
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* address space.
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*
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* - start - start address (may not be aligned)
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* - end - end address (exclusive, may not be aligned)
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* - flags - vma_area_struct flags describing address space
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*/
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ENTRY(v3_flush_user_cache_range)
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mov ip, #0
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mcreq p15, 0, ip, c7, c0, 0 @ flush ID cache
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mov pc, lr
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/*
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* coherent_kern_range(start, end)
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*
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* Ensure coherency between the Icache and the Dcache in the
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* region described by start. If you have non-snooping
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* Harvard caches, you need to implement this function.
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*
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* - start - virtual start address
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* - end - virtual end address
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*/
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ENTRY(v3_coherent_kern_range)
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/* FALLTHROUGH */
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/*
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* coherent_user_range(start, end)
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*
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* Ensure coherency between the Icache and the Dcache in the
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* region described by start. If you have non-snooping
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* Harvard caches, you need to implement this function.
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*
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* - start - virtual start address
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* - end - virtual end address
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*/
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ENTRY(v3_coherent_user_range)
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mov r0, #0
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mov pc, lr
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/*
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* flush_kern_dcache_area(void *page, size_t size)
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*
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* Ensure no D cache aliasing occurs, either with itself or
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* the I cache
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*
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* - addr - kernel address
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* - size - region size
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*/
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ENTRY(v3_flush_kern_dcache_area)
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/* FALLTHROUGH */
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/*
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* dma_flush_range(start, end)
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*
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* Clean and invalidate the specified virtual address range.
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*
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* - start - virtual start address
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* - end - virtual end address
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*/
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ENTRY(v3_dma_flush_range)
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mov r0, #0
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mcr p15, 0, r0, c7, c0, 0 @ flush ID cache
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mov pc, lr
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/*
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* dma_unmap_area(start, size, dir)
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* - start - kernel virtual start address
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* - size - size of region
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* - dir - DMA direction
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*/
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ENTRY(v3_dma_unmap_area)
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teq r2, #DMA_TO_DEVICE
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bne v3_dma_flush_range
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/* FALLTHROUGH */
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/*
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* dma_map_area(start, size, dir)
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* - start - kernel virtual start address
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* - size - size of region
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* - dir - DMA direction
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*/
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ENTRY(v3_dma_map_area)
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mov pc, lr
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ENDPROC(v3_dma_unmap_area)
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ENDPROC(v3_dma_map_area)
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.globl v3_flush_kern_cache_louis
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.equ v3_flush_kern_cache_louis, v3_flush_kern_cache_all
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__INITDATA
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@ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S)
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define_cache_functions v3
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@ -145,5 +145,5 @@ __arm740_proc_info:
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.long arm740_processor_functions
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.long 0
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.long 0
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.long v3_cache_fns @ cache model
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.long v4_cache_fns @ cache model
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.size __arm740_proc_info, . - __arm740_proc_info
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