cs5535: add a generic MFGPT driver
This is based on the old code on arch/x86/kernel/mfgpt_32.c, except it's not x86 specific, it's modular, and it makes use of a PCI BAR rather than a random MSR. Currently module unloading is not supported; it's uncertain whether or not it can be made work with the hardware. [akpm@linux-foundation.org: add X86 dependency] Signed-off-by: Andres Salomon <dilinger@collabora.co.uk> Cc: Jordan Crouse <jordan@cosmicpenguin.net> Cc: Ingo Molnar <mingo@elte.hu> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: john stultz <johnstul@us.ibm.com> Cc: Chris Ball <cjb@laptop.org> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
This commit is contained in:
Andres Salomon
Linus Torvalds
Родитель
3c55494670
Коммит
82dca611bb
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@ -47,16 +47,6 @@ extern int geode_get_dev_base(unsigned int dev);
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#define MSR_DIVIL_SOFT_RESET 0x51400017
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#define MSR_PIC_YSEL_LOW 0x51400020
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#define MSR_PIC_YSEL_HIGH 0x51400021
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#define MSR_PIC_ZSEL_LOW 0x51400022
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#define MSR_PIC_ZSEL_HIGH 0x51400023
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#define MSR_PIC_IRQM_LPC 0x51400025
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#define MSR_MFGPT_IRQ 0x51400028
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#define MSR_MFGPT_NR 0x51400029
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#define MSR_MFGPT_SETUP 0x5140002B
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#define MSR_LX_SPARE_MSR 0x80000011 /* DC-specific */
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#define MSR_GX_GLD_MSR_CONFIG 0xC0002001
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@ -169,36 +159,6 @@ static inline int geode_has_vsa2(void)
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}
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#endif
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/* MFGPTs */
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#define MFGPT_MAX_TIMERS 8
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#define MFGPT_TIMER_ANY (-1)
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#define MFGPT_DOMAIN_WORKING 1
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#define MFGPT_DOMAIN_STANDBY 2
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#define MFGPT_DOMAIN_ANY (MFGPT_DOMAIN_WORKING | MFGPT_DOMAIN_STANDBY)
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#define MFGPT_CMP1 0
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#define MFGPT_CMP2 1
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#define MFGPT_EVENT_IRQ 0
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#define MFGPT_EVENT_NMI 1
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#define MFGPT_EVENT_RESET 3
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#define MFGPT_REG_CMP1 0
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#define MFGPT_REG_CMP2 2
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#define MFGPT_REG_COUNTER 4
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#define MFGPT_REG_SETUP 6
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#define MFGPT_SETUP_CNTEN (1 << 15)
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#define MFGPT_SETUP_CMP2 (1 << 14)
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#define MFGPT_SETUP_CMP1 (1 << 13)
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#define MFGPT_SETUP_SETUP (1 << 12)
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#define MFGPT_SETUP_STOPEN (1 << 11)
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#define MFGPT_SETUP_EXTEN (1 << 10)
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#define MFGPT_SETUP_REVEN (1 << 5)
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#define MFGPT_SETUP_CLKSEL (1 << 4)
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static inline void geode_mfgpt_write(int timer, u16 reg, u16 value)
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{
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u32 base = geode_get_dev_base(GEODE_DEV_MFGPT);
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@ -187,6 +187,30 @@ config SGI_XP
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this feature will allow for direct communication between SSIs
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based on a network adapter and DMA messaging.
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config CS5535_MFGPT
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tristate "CS5535/CS5536 Geode Multi-Function General Purpose Timer (MFGPT) support"
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depends on PCI && !MGEODE_LX
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depends on X86
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default n
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help
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This driver provides access to MFGPT functionality for other
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drivers that need timers. MFGPTs are available in the CS5535 and
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CS5536 companion chips that are found in AMD Geode and several
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other platforms. They have a better resolution and max interval
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than the generic PIT, and are suitable for use as high-res timers.
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You probably don't want to enable this manually; other drivers that
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make use of it should enable it.
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config CS5535_MFGPT_DEFAULT_IRQ
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int
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default 7
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help
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MFGPTs on the CS5535 require an interrupt. The selected IRQ
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can be overridden as a module option as well as by driver that
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use the cs5535_mfgpt_ API; however, different architectures might
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want to use a different IRQ by default. This is here for
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architectures to set as necessary.
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config HP_ILO
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tristate "Channel interface driver for HP iLO/iLO2 processor"
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depends on PCI
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@ -18,6 +18,7 @@ obj-$(CONFIG_ENCLOSURE_SERVICES) += enclosure.o
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obj-$(CONFIG_KGDB_TESTS) += kgdbts.o
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obj-$(CONFIG_SGI_XP) += sgi-xp/
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obj-$(CONFIG_SGI_GRU) += sgi-gru/
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obj-$(CONFIG_CS5535_MFGPT) += cs5535-mfgpt.o
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obj-$(CONFIG_HP_ILO) += hpilo.o
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obj-$(CONFIG_ISL29003) += isl29003.o
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obj-$(CONFIG_EP93XX_PWM) += ep93xx_pwm.o
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@ -0,0 +1,370 @@
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/*
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* Driver for the CS5535/CS5536 Multi-Function General Purpose Timers (MFGPT)
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*
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* Copyright (C) 2006, Advanced Micro Devices, Inc.
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* Copyright (C) 2007 Andres Salomon <dilinger@debian.org>
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* Copyright (C) 2009 Andres Salomon <dilinger@collabora.co.uk>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of version 2 of the GNU General Public License
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* as published by the Free Software Foundation.
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*
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* The MFGPTs are documented in AMD Geode CS5536 Companion Device Data Book.
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*/
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#include <linux/kernel.h>
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#include <linux/spinlock.h>
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#include <linux/interrupt.h>
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <linux/cs5535.h>
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#define DRV_NAME "cs5535-mfgpt"
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#define MFGPT_BAR 2
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static int mfgpt_reset_timers;
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module_param_named(mfgptfix, mfgpt_reset_timers, int, 0644);
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MODULE_PARM_DESC(mfgptfix, "Reset the MFGPT timers during init; "
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"required by some broken BIOSes (ie, TinyBIOS < 0.99).");
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struct cs5535_mfgpt_timer {
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struct cs5535_mfgpt_chip *chip;
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int nr;
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};
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static struct cs5535_mfgpt_chip {
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DECLARE_BITMAP(avail, MFGPT_MAX_TIMERS);
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resource_size_t base;
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struct pci_dev *pdev;
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spinlock_t lock;
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int initialized;
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} cs5535_mfgpt_chip;
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int cs5535_mfgpt_toggle_event(struct cs5535_mfgpt_timer *timer, int cmp,
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int event, int enable)
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{
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uint32_t msr, mask, value, dummy;
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int shift = (cmp == MFGPT_CMP1) ? 0 : 8;
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if (!timer) {
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WARN_ON(1);
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return -EIO;
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}
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/*
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* The register maps for these are described in sections 6.17.1.x of
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* the AMD Geode CS5536 Companion Device Data Book.
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*/
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switch (event) {
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case MFGPT_EVENT_RESET:
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/*
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* XXX: According to the docs, we cannot reset timers above
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* 6; that is, resets for 7 and 8 will be ignored. Is this
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* a problem? -dilinger
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*/
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msr = MSR_MFGPT_NR;
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mask = 1 << (timer->nr + 24);
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break;
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case MFGPT_EVENT_NMI:
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msr = MSR_MFGPT_NR;
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mask = 1 << (timer->nr + shift);
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break;
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case MFGPT_EVENT_IRQ:
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msr = MSR_MFGPT_IRQ;
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mask = 1 << (timer->nr + shift);
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break;
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default:
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return -EIO;
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}
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rdmsr(msr, value, dummy);
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if (enable)
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value |= mask;
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else
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value &= ~mask;
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wrmsr(msr, value, dummy);
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return 0;
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}
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EXPORT_SYMBOL_GPL(cs5535_mfgpt_toggle_event);
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int cs5535_mfgpt_set_irq(struct cs5535_mfgpt_timer *timer, int cmp, int *irq,
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int enable)
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{
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uint32_t zsel, lpc, dummy;
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int shift;
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if (!timer) {
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WARN_ON(1);
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return -EIO;
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}
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/*
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* Unfortunately, MFGPTs come in pairs sharing their IRQ lines. If VSA
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* is using the same CMP of the timer's Siamese twin, the IRQ is set to
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* 2, and we mustn't use nor change it.
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* XXX: Likewise, 2 Linux drivers might clash if the 2nd overwrites the
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* IRQ of the 1st. This can only happen if forcing an IRQ, calling this
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* with *irq==0 is safe. Currently there _are_ no 2 drivers.
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*/
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rdmsr(MSR_PIC_ZSEL_LOW, zsel, dummy);
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shift = ((cmp == MFGPT_CMP1 ? 0 : 4) + timer->nr % 4) * 4;
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if (((zsel >> shift) & 0xF) == 2)
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return -EIO;
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/* Choose IRQ: if none supplied, keep IRQ already set or use default */
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if (!*irq)
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*irq = (zsel >> shift) & 0xF;
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if (!*irq)
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*irq = CONFIG_CS5535_MFGPT_DEFAULT_IRQ;
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/* Can't use IRQ if it's 0 (=disabled), 2, or routed to LPC */
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if (*irq < 1 || *irq == 2 || *irq > 15)
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return -EIO;
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rdmsr(MSR_PIC_IRQM_LPC, lpc, dummy);
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if (lpc & (1 << *irq))
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return -EIO;
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/* All chosen and checked - go for it */
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if (cs5535_mfgpt_toggle_event(timer, cmp, MFGPT_EVENT_IRQ, enable))
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return -EIO;
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if (enable) {
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zsel = (zsel & ~(0xF << shift)) | (*irq << shift);
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wrmsr(MSR_PIC_ZSEL_LOW, zsel, dummy);
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}
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return 0;
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}
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EXPORT_SYMBOL_GPL(cs5535_mfgpt_set_irq);
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struct cs5535_mfgpt_timer *cs5535_mfgpt_alloc_timer(int timer_nr, int domain)
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{
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struct cs5535_mfgpt_chip *mfgpt = &cs5535_mfgpt_chip;
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struct cs5535_mfgpt_timer *timer = NULL;
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unsigned long flags;
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int max;
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if (!mfgpt->initialized)
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goto done;
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/* only allocate timers from the working domain if requested */
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if (domain == MFGPT_DOMAIN_WORKING)
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max = 6;
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else
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max = MFGPT_MAX_TIMERS;
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if (timer_nr >= max) {
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/* programmer error. silly programmers! */
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WARN_ON(1);
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goto done;
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}
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spin_lock_irqsave(&mfgpt->lock, flags);
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if (timer_nr < 0) {
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unsigned long t;
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/* try to find any available timer */
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t = find_first_bit(mfgpt->avail, max);
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/* set timer_nr to -1 if no timers available */
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timer_nr = t < max ? (int) t : -1;
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} else {
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/* check if the requested timer's available */
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if (test_bit(timer_nr, mfgpt->avail))
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timer_nr = -1;
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}
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if (timer_nr >= 0)
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/* if timer_nr is not -1, it's an available timer */
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__clear_bit(timer_nr, mfgpt->avail);
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spin_unlock_irqrestore(&mfgpt->lock, flags);
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if (timer_nr < 0)
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goto done;
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timer = kmalloc(sizeof(*timer), GFP_KERNEL);
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if (!timer) {
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/* aw hell */
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spin_lock_irqsave(&mfgpt->lock, flags);
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__set_bit(timer_nr, mfgpt->avail);
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spin_unlock_irqrestore(&mfgpt->lock, flags);
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goto done;
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}
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timer->chip = mfgpt;
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timer->nr = timer_nr;
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dev_info(&mfgpt->pdev->dev, "registered timer %d\n", timer_nr);
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done:
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return timer;
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}
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EXPORT_SYMBOL_GPL(cs5535_mfgpt_alloc_timer);
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/*
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* XXX: This frees the timer memory, but never resets the actual hardware
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* timer. The old geode_mfgpt code did this; it would be good to figure
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* out a way to actually release the hardware timer. See comments below.
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*/
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void cs5535_mfgpt_free_timer(struct cs5535_mfgpt_timer *timer)
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{
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kfree(timer);
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}
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EXPORT_SYMBOL_GPL(cs5535_mfgpt_free_timer);
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uint16_t cs5535_mfgpt_read(struct cs5535_mfgpt_timer *timer, uint16_t reg)
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{
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return inw(timer->chip->base + reg + (timer->nr * 8));
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}
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EXPORT_SYMBOL_GPL(cs5535_mfgpt_read);
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void cs5535_mfgpt_write(struct cs5535_mfgpt_timer *timer, uint16_t reg,
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uint16_t value)
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{
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outw(value, timer->chip->base + reg + (timer->nr * 8));
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}
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EXPORT_SYMBOL_GPL(cs5535_mfgpt_write);
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/*
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* This is a sledgehammer that resets all MFGPT timers. This is required by
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* some broken BIOSes which leave the system in an unstable state
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* (TinyBIOS 0.98, for example; fixed in 0.99). It's uncertain as to
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* whether or not this secret MSR can be used to release individual timers.
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* Jordan tells me that he and Mitch once played w/ it, but it's unclear
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* what the results of that were (and they experienced some instability).
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*/
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static void __init reset_all_timers(void)
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{
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uint32_t val, dummy;
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/* The following undocumented bit resets the MFGPT timers */
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val = 0xFF; dummy = 0;
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wrmsr(MSR_MFGPT_SETUP, val, dummy);
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}
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/*
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* Check whether any MFGPTs are available for the kernel to use. In most
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* cases, firmware that uses AMD's VSA code will claim all timers during
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* bootup; we certainly don't want to take them if they're already in use.
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* In other cases (such as with VSAless OpenFirmware), the system firmware
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* leaves timers available for us to use.
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*/
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static int __init scan_timers(struct cs5535_mfgpt_chip *mfgpt)
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{
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struct cs5535_mfgpt_timer timer = { .chip = mfgpt };
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unsigned long flags;
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int timers = 0;
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uint16_t val;
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int i;
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/* bios workaround */
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if (mfgpt_reset_timers)
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reset_all_timers();
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/* just to be safe, protect this section w/ lock */
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spin_lock_irqsave(&mfgpt->lock, flags);
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for (i = 0; i < MFGPT_MAX_TIMERS; i++) {
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timer.nr = i;
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val = cs5535_mfgpt_read(&timer, MFGPT_REG_SETUP);
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if (!(val & MFGPT_SETUP_SETUP)) {
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__set_bit(i, mfgpt->avail);
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timers++;
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}
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}
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spin_unlock_irqrestore(&mfgpt->lock, flags);
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return timers;
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}
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static int __init cs5535_mfgpt_probe(struct pci_dev *pdev,
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const struct pci_device_id *pci_id)
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{
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int err, t;
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/* There are two ways to get the MFGPT base address; one is by
|
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* fetching it from MSR_LBAR_MFGPT, the other is by reading the
|
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* PCI BAR info. The latter method is easier (especially across
|
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* different architectures), so we'll stick with that for now. If
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* it turns out to be unreliable in the face of crappy BIOSes, we
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* can always go back to using MSRs.. */
|
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err = pci_enable_device_io(pdev);
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if (err) {
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dev_err(&pdev->dev, "can't enable device IO\n");
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goto done;
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}
|
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err = pci_request_region(pdev, MFGPT_BAR, DRV_NAME);
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if (err) {
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dev_err(&pdev->dev, "can't alloc PCI BAR #%d\n", MFGPT_BAR);
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goto done;
|
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}
|
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|
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/* set up the driver-specific struct */
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cs5535_mfgpt_chip.base = pci_resource_start(pdev, MFGPT_BAR);
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cs5535_mfgpt_chip.pdev = pdev;
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spin_lock_init(&cs5535_mfgpt_chip.lock);
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dev_info(&pdev->dev, "allocated PCI BAR #%d: base 0x%llx\n", MFGPT_BAR,
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(unsigned long long) cs5535_mfgpt_chip.base);
|
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/* detect the available timers */
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t = scan_timers(&cs5535_mfgpt_chip);
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dev_info(&pdev->dev, DRV_NAME ": %d MFGPT timers available\n", t);
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cs5535_mfgpt_chip.initialized = 1;
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return 0;
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done:
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return err;
|
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}
|
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|
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static struct pci_device_id cs5535_mfgpt_pci_tbl[] = {
|
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{ PCI_DEVICE(PCI_VENDOR_ID_NS, PCI_DEVICE_ID_NS_CS5535_ISA) },
|
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{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_ISA) },
|
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{ 0, },
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};
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MODULE_DEVICE_TABLE(pci, cs5535_mfgpt_pci_tbl);
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|
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/*
|
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* Just like with the cs5535-gpio driver, we can't use the standard PCI driver
|
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* registration stuff. It only allows only one driver to bind to each PCI
|
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* device, and we want the GPIO and MFGPT drivers to be able to share a PCI
|
||||
* device. Instead, we manually scan for the PCI device, request a single
|
||||
* region, and keep track of the devices that we're using.
|
||||
*/
|
||||
|
||||
static int __init cs5535_mfgpt_scan_pci(void)
|
||||
{
|
||||
struct pci_dev *pdev;
|
||||
int err = -ENODEV;
|
||||
int i;
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(cs5535_mfgpt_pci_tbl); i++) {
|
||||
pdev = pci_get_device(cs5535_mfgpt_pci_tbl[i].vendor,
|
||||
cs5535_mfgpt_pci_tbl[i].device, NULL);
|
||||
if (pdev) {
|
||||
err = cs5535_mfgpt_probe(pdev,
|
||||
&cs5535_mfgpt_pci_tbl[i]);
|
||||
if (err)
|
||||
pci_dev_put(pdev);
|
||||
|
||||
/* we only support a single CS5535/6 southbridge */
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
return err;
|
||||
}
|
||||
|
||||
static int __init cs5535_mfgpt_init(void)
|
||||
{
|
||||
return cs5535_mfgpt_scan_pci();
|
||||
}
|
||||
|
||||
module_init(cs5535_mfgpt_init);
|
||||
|
||||
MODULE_AUTHOR("Andres Salomon <dilinger@collabora.co.uk>");
|
||||
MODULE_DESCRIPTION("CS5535/CS5536 MFGPT timer driver");
|
||||
MODULE_LICENSE("GPL");
|
||||
|
|
@ -18,6 +18,16 @@
|
|||
#define MSR_LBAR_ACPI 0x5140000E
|
||||
#define MSR_LBAR_PMS 0x5140000F
|
||||
|
||||
#define MSR_PIC_YSEL_LOW 0x51400020
|
||||
#define MSR_PIC_YSEL_HIGH 0x51400021
|
||||
#define MSR_PIC_ZSEL_LOW 0x51400022
|
||||
#define MSR_PIC_ZSEL_HIGH 0x51400023
|
||||
#define MSR_PIC_IRQM_LPC 0x51400025
|
||||
|
||||
#define MSR_MFGPT_IRQ 0x51400028
|
||||
#define MSR_MFGPT_NR 0x51400029
|
||||
#define MSR_MFGPT_SETUP 0x5140002B
|
||||
|
||||
/* resource sizes */
|
||||
#define LBAR_GPIO_SIZE 0xFF
|
||||
#define LBAR_MFGPT_SIZE 0x40
|
||||
|
|
@ -55,4 +65,61 @@ void cs5535_gpio_set(unsigned offset, unsigned int reg);
|
|||
void cs5535_gpio_clear(unsigned offset, unsigned int reg);
|
||||
int cs5535_gpio_isset(unsigned offset, unsigned int reg);
|
||||
|
||||
/* MFGPTs */
|
||||
|
||||
#define MFGPT_MAX_TIMERS 8
|
||||
#define MFGPT_TIMER_ANY (-1)
|
||||
|
||||
#define MFGPT_DOMAIN_WORKING 1
|
||||
#define MFGPT_DOMAIN_STANDBY 2
|
||||
#define MFGPT_DOMAIN_ANY (MFGPT_DOMAIN_WORKING | MFGPT_DOMAIN_STANDBY)
|
||||
|
||||
#define MFGPT_CMP1 0
|
||||
#define MFGPT_CMP2 1
|
||||
|
||||
#define MFGPT_EVENT_IRQ 0
|
||||
#define MFGPT_EVENT_NMI 1
|
||||
#define MFGPT_EVENT_RESET 3
|
||||
|
||||
#define MFGPT_REG_CMP1 0
|
||||
#define MFGPT_REG_CMP2 2
|
||||
#define MFGPT_REG_COUNTER 4
|
||||
#define MFGPT_REG_SETUP 6
|
||||
|
||||
#define MFGPT_SETUP_CNTEN (1 << 15)
|
||||
#define MFGPT_SETUP_CMP2 (1 << 14)
|
||||
#define MFGPT_SETUP_CMP1 (1 << 13)
|
||||
#define MFGPT_SETUP_SETUP (1 << 12)
|
||||
#define MFGPT_SETUP_STOPEN (1 << 11)
|
||||
#define MFGPT_SETUP_EXTEN (1 << 10)
|
||||
#define MFGPT_SETUP_REVEN (1 << 5)
|
||||
#define MFGPT_SETUP_CLKSEL (1 << 4)
|
||||
|
||||
struct cs5535_mfgpt_timer;
|
||||
|
||||
extern uint16_t cs5535_mfgpt_read(struct cs5535_mfgpt_timer *timer,
|
||||
uint16_t reg);
|
||||
extern void cs5535_mfgpt_write(struct cs5535_mfgpt_timer *timer, uint16_t reg,
|
||||
uint16_t value);
|
||||
|
||||
extern int cs5535_mfgpt_toggle_event(struct cs5535_mfgpt_timer *timer, int cmp,
|
||||
int event, int enable);
|
||||
extern int cs5535_mfgpt_set_irq(struct cs5535_mfgpt_timer *timer, int cmp,
|
||||
int *irq, int enable);
|
||||
extern struct cs5535_mfgpt_timer *cs5535_mfgpt_alloc_timer(int timer,
|
||||
int domain);
|
||||
extern void cs5535_mfgpt_free_timer(struct cs5535_mfgpt_timer *timer);
|
||||
|
||||
static inline int cs5535_mfgpt_setup_irq(struct cs5535_mfgpt_timer *timer,
|
||||
int cmp, int *irq)
|
||||
{
|
||||
return cs5535_mfgpt_set_irq(timer, cmp, irq, 1);
|
||||
}
|
||||
|
||||
static inline int cs5535_mfgpt_release_irq(struct cs5535_mfgpt_timer *timer,
|
||||
int cmp, int *irq)
|
||||
{
|
||||
return cs5535_mfgpt_set_irq(timer, cmp, irq, 0);
|
||||
}
|
||||
|
||||
#endif
|
||||
|
|
|
|||
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