ASoC: stm32: sai: set sai as mclk clock provider
Add master clock generation support in STM32 SAI. The master clock provided by SAI can be used to feed a codec. Signed-off-by: Olivier Moysan <olivier.moysan@st.com> Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Olivier Moysan
Mark Brown
Родитель
1c5083b37d
Коммит
8307b2afd3
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@ -91,6 +91,9 @@
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#define SAI_XCR1_OSR_SHIFT 26
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#define SAI_XCR1_OSR BIT(SAI_XCR1_OSR_SHIFT)
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#define SAI_XCR1_MCKEN_SHIFT 27
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#define SAI_XCR1_MCKEN BIT(SAI_XCR1_MCKEN_SHIFT)
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/******************* Bit definition for SAI_XCR2 register *******************/
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#define SAI_XCR2_FTH_SHIFT 0
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#define SAI_XCR2_FTH_MASK GENMASK(2, SAI_XCR2_FTH_SHIFT)
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@ -17,6 +17,7 @@
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*/
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/of_irq.h>
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@ -68,6 +69,8 @@
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#define SAI_IEC60958_BLOCK_FRAMES 192
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#define SAI_IEC60958_STATUS_BYTES 24
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#define SAI_MCLK_NAME_LEN 32
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/**
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* struct stm32_sai_sub_data - private data of SAI sub block (block A or B)
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* @pdev: device data pointer
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@ -80,6 +83,7 @@
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* @pdata: SAI block parent data pointer
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* @np_sync_provider: synchronization provider node
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* @sai_ck: kernel clock feeding the SAI clock generator
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* @sai_mclk: master clock from SAI mclk provider
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* @phys_addr: SAI registers physical base address
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* @mclk_rate: SAI block master clock frequency (Hz). set at init
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* @id: SAI sub block id corresponding to sub-block A or B
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@ -110,6 +114,7 @@ struct stm32_sai_sub_data {
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struct stm32_sai_data *pdata;
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struct device_node *np_sync_provider;
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struct clk *sai_ck;
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struct clk *sai_mclk;
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dma_addr_t phys_addr;
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unsigned int mclk_rate;
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unsigned int id;
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@ -251,6 +256,177 @@ static const struct snd_kcontrol_new iec958_ctls = {
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.put = snd_pcm_iec958_put,
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};
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struct stm32_sai_mclk_data {
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struct clk_hw hw;
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unsigned long freq;
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struct stm32_sai_sub_data *sai_data;
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};
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#define to_mclk_data(_hw) container_of(_hw, struct stm32_sai_mclk_data, hw)
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#define STM32_SAI_MAX_CLKS 1
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static int stm32_sai_get_clk_div(struct stm32_sai_sub_data *sai,
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unsigned long input_rate,
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unsigned long output_rate)
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{
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int version = sai->pdata->conf->version;
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int div;
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div = DIV_ROUND_CLOSEST(input_rate, output_rate);
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if (div > SAI_XCR1_MCKDIV_MAX(version)) {
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dev_err(&sai->pdev->dev, "Divider %d out of range\n", div);
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return -EINVAL;
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}
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dev_dbg(&sai->pdev->dev, "SAI divider %d\n", div);
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if (input_rate % div)
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dev_dbg(&sai->pdev->dev,
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"Rate not accurate. requested (%ld), actual (%ld)\n",
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output_rate, input_rate / div);
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return div;
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}
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static int stm32_sai_set_clk_div(struct stm32_sai_sub_data *sai,
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unsigned int div)
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{
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int version = sai->pdata->conf->version;
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int ret, cr1, mask;
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if (div > SAI_XCR1_MCKDIV_MAX(version)) {
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dev_err(&sai->pdev->dev, "Divider %d out of range\n", div);
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return -EINVAL;
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}
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mask = SAI_XCR1_MCKDIV_MASK(SAI_XCR1_MCKDIV_WIDTH(version));
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cr1 = SAI_XCR1_MCKDIV_SET(div);
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ret = regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX, mask, cr1);
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if (ret < 0)
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dev_err(&sai->pdev->dev, "Failed to update CR1 register\n");
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return ret;
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}
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static long stm32_sai_mclk_round_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long *prate)
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{
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struct stm32_sai_mclk_data *mclk = to_mclk_data(hw);
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struct stm32_sai_sub_data *sai = mclk->sai_data;
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int div;
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div = stm32_sai_get_clk_div(sai, *prate, rate);
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if (div < 0)
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return div;
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mclk->freq = *prate / div;
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return mclk->freq;
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}
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static unsigned long stm32_sai_mclk_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct stm32_sai_mclk_data *mclk = to_mclk_data(hw);
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return mclk->freq;
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}
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static int stm32_sai_mclk_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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struct stm32_sai_mclk_data *mclk = to_mclk_data(hw);
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struct stm32_sai_sub_data *sai = mclk->sai_data;
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unsigned int div;
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int ret;
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div = stm32_sai_get_clk_div(sai, parent_rate, rate);
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if (div < 0)
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return div;
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ret = stm32_sai_set_clk_div(sai, div);
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if (ret)
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return ret;
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mclk->freq = rate;
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return 0;
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}
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static int stm32_sai_mclk_enable(struct clk_hw *hw)
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{
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struct stm32_sai_mclk_data *mclk = to_mclk_data(hw);
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struct stm32_sai_sub_data *sai = mclk->sai_data;
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dev_dbg(&sai->pdev->dev, "Enable master clock\n");
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return regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX,
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SAI_XCR1_MCKEN, SAI_XCR1_MCKEN);
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}
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static void stm32_sai_mclk_disable(struct clk_hw *hw)
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{
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struct stm32_sai_mclk_data *mclk = to_mclk_data(hw);
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struct stm32_sai_sub_data *sai = mclk->sai_data;
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dev_dbg(&sai->pdev->dev, "Disable master clock\n");
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regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX, SAI_XCR1_MCKEN, 0);
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}
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static const struct clk_ops mclk_ops = {
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.enable = stm32_sai_mclk_enable,
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.disable = stm32_sai_mclk_disable,
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.recalc_rate = stm32_sai_mclk_recalc_rate,
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.round_rate = stm32_sai_mclk_round_rate,
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.set_rate = stm32_sai_mclk_set_rate,
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};
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static int stm32_sai_add_mclk_provider(struct stm32_sai_sub_data *sai)
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{
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struct clk_hw *hw;
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struct stm32_sai_mclk_data *mclk;
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struct device *dev = &sai->pdev->dev;
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const char *pname = __clk_get_name(sai->sai_ck);
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char *mclk_name, *p, *s = (char *)pname;
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int ret, i = 0;
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mclk = devm_kzalloc(dev, sizeof(mclk), GFP_KERNEL);
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if (!mclk)
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return -ENOMEM;
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mclk_name = devm_kcalloc(dev, sizeof(char),
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SAI_MCLK_NAME_LEN, GFP_KERNEL);
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if (!mclk_name)
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return -ENOMEM;
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/*
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* Forge mclk clock name from parent clock name and suffix.
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* String after "_" char is stripped in parent name.
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*/
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p = mclk_name;
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while (*s && *s != '_' && (i < (SAI_MCLK_NAME_LEN - 6))) {
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*p++ = *s++;
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i++;
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}
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STM_SAI_IS_SUB_A(sai) ?
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strncat(p, "a_mclk", 6) : strncat(p, "b_mclk", 6);
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mclk->hw.init = CLK_HW_INIT(mclk_name, pname, &mclk_ops, 0);
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mclk->sai_data = sai;
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hw = &mclk->hw;
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dev_dbg(dev, "Register master clock %s\n", mclk_name);
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ret = devm_clk_hw_register(&sai->pdev->dev, hw);
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if (ret) {
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dev_err(dev, "mclk register returned %d\n", ret);
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return ret;
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}
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sai->sai_mclk = hw->clk;
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/* register mclk provider */
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return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, hw);
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}
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static irqreturn_t stm32_sai_isr(int irq, void *devid)
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{
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struct stm32_sai_sub_data *sai = (struct stm32_sai_sub_data *)devid;
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@ -312,15 +488,25 @@ static int stm32_sai_set_sysclk(struct snd_soc_dai *cpu_dai,
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struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai);
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int ret;
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if ((dir == SND_SOC_CLOCK_OUT) && sai->master) {
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if (dir == SND_SOC_CLOCK_OUT) {
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ret = regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX,
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SAI_XCR1_NODIV,
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(unsigned int)~SAI_XCR1_NODIV);
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if (ret < 0)
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return ret;
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sai->mclk_rate = freq;
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dev_dbg(cpu_dai->dev, "SAI MCLK frequency is %uHz\n", freq);
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sai->mclk_rate = freq;
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if (sai->sai_mclk) {
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ret = clk_set_rate_exclusive(sai->sai_mclk,
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sai->mclk_rate);
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if (ret) {
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dev_err(cpu_dai->dev,
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"Could not set mclk rate\n");
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return ret;
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}
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}
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}
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return 0;
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@ -715,15 +901,9 @@ static int stm32_sai_configure_clock(struct snd_soc_dai *cpu_dai,
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{
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struct stm32_sai_sub_data *sai = snd_soc_dai_get_drvdata(cpu_dai);
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int cr1, mask, div = 0;
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int sai_clk_rate, mclk_ratio, den, ret;
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int version = sai->pdata->conf->version;
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int sai_clk_rate, mclk_ratio, den;
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unsigned int rate = params_rate(params);
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if (!sai->mclk_rate) {
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dev_err(cpu_dai->dev, "Mclk rate is null\n");
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return -EINVAL;
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}
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if (!(rate % 11025))
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clk_set_parent(sai->sai_ck, sai->pdata->clk_x11k);
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else
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@ -731,14 +911,22 @@ static int stm32_sai_configure_clock(struct snd_soc_dai *cpu_dai,
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sai_clk_rate = clk_get_rate(sai->sai_ck);
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if (STM_SAI_IS_F4(sai->pdata)) {
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/*
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/* mclk on (NODIV=0)
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* mclk_rate = 256 * fs
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* MCKDIV = 0 if sai_ck < 3/2 * mclk_rate
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* MCKDIV = sai_ck / (2 * mclk_rate) otherwise
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* mclk off (NODIV=1)
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* MCKDIV ignored. sck = sai_ck
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*/
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if (2 * sai_clk_rate >= 3 * sai->mclk_rate)
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div = DIV_ROUND_CLOSEST(sai_clk_rate,
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if (!sai->mclk_rate)
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return 0;
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if (2 * sai_clk_rate >= 3 * sai->mclk_rate) {
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div = stm32_sai_get_clk_div(sai, sai_clk_rate,
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2 * sai->mclk_rate);
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if (div < 0)
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return div;
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}
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} else {
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/*
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* TDM mode :
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@ -750,8 +938,10 @@ static int stm32_sai_configure_clock(struct snd_soc_dai *cpu_dai,
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* Note: NOMCK/NODIV correspond to same bit.
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*/
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if (STM_SAI_PROTOCOL_IS_SPDIF(sai)) {
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div = DIV_ROUND_CLOSEST(sai_clk_rate,
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(params_rate(params) * 128));
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div = stm32_sai_get_clk_div(sai, sai_clk_rate,
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rate * 128);
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if (div < 0)
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return div;
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} else {
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if (sai->mclk_rate) {
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mclk_ratio = sai->mclk_rate / rate;
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@ -764,31 +954,22 @@ static int stm32_sai_configure_clock(struct snd_soc_dai *cpu_dai,
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mclk_ratio);
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return -EINVAL;
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}
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div = DIV_ROUND_CLOSEST(sai_clk_rate,
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div = stm32_sai_get_clk_div(sai, sai_clk_rate,
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sai->mclk_rate);
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if (div < 0)
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return div;
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} else {
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/* mclk-fs not set, master clock not active */
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den = sai->fs_length * params_rate(params);
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div = DIV_ROUND_CLOSEST(sai_clk_rate, den);
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div = stm32_sai_get_clk_div(sai, sai_clk_rate,
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den);
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if (div < 0)
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return div;
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}
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}
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}
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if (div > SAI_XCR1_MCKDIV_MAX(version)) {
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dev_err(cpu_dai->dev, "Divider %d out of range\n", div);
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return -EINVAL;
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}
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dev_dbg(cpu_dai->dev, "SAI clock %d, divider %d\n", sai_clk_rate, div);
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mask = SAI_XCR1_MCKDIV_MASK(SAI_XCR1_MCKDIV_WIDTH(version));
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cr1 = SAI_XCR1_MCKDIV_SET(div);
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ret = regmap_update_bits(sai->regmap, STM_SAI_CR1_REGX, mask, cr1);
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if (ret < 0) {
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dev_err(cpu_dai->dev, "Failed to update CR1 register\n");
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return ret;
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}
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return 0;
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return stm32_sai_set_clk_div(sai, div);
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}
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static int stm32_sai_hw_params(struct snd_pcm_substream *substream,
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@ -881,6 +1062,9 @@ static void stm32_sai_shutdown(struct snd_pcm_substream *substream,
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SAI_XCR1_NODIV);
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clk_disable_unprepare(sai->sai_ck);
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clk_rate_exclusive_put(sai->sai_mclk);
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sai->substream = NULL;
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}
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@ -903,6 +1087,8 @@ static int stm32_sai_dai_probe(struct snd_soc_dai *cpu_dai)
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struct stm32_sai_sub_data *sai = dev_get_drvdata(cpu_dai->dev);
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int cr1 = 0, cr1_mask;
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sai->cpu_dai = cpu_dai;
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sai->dma_params.addr = (dma_addr_t)(sai->phys_addr + STM_SAI_DR_REGX);
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/*
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* DMA supports 4, 8 or 16 burst sizes. Burst size 4 is the best choice,
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@ -1181,6 +1367,23 @@ static int stm32_sai_sub_parse_of(struct platform_device *pdev,
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return PTR_ERR(sai->sai_ck);
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}
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if (STM_SAI_IS_F4(sai->pdata))
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return 0;
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/* Register mclk provider if requested */
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if (of_find_property(np, "#clock-cells", NULL)) {
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ret = stm32_sai_add_mclk_provider(sai);
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if (ret < 0)
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return ret;
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} else {
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sai->sai_mclk = devm_clk_get(&pdev->dev, "MCLK");
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if (IS_ERR(sai->sai_mclk)) {
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if (PTR_ERR(sai->sai_mclk) != -ENOENT)
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return PTR_ERR(sai->sai_mclk);
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sai->sai_mclk = NULL;
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}
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}
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return 0;
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}
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