Merge branch 'drm-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/airlied/drm-2.6
* 'drm-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/airlied/drm-2.6: drm/i915: Add missing mutex_lock(&dev->struct_mutex) drm/i915: fix WC mapping in non-GEM i915 code. drm/i915: Fix regression in 95ca9d drm/i915: Retire requests from i915_gem_busy_ioctl. drm/i915: suspend/resume GEM when KMS is active drm/i915: Don't let a device flush to prepare buffers clear new write_domains. drm/i915: Cut two args to set_to_gpu_domain that confused this tricky path.
This commit is contained in:
Linus Torvalds
Коммит
8310509252
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@ -202,7 +202,7 @@ static int i915_initialize(struct drm_device * dev, drm_i915_init_t * init)
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dev_priv->ring.map.flags = 0;
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dev_priv->ring.map.mtrr = 0;
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drm_core_ioremap(&dev_priv->ring.map, dev);
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drm_core_ioremap_wc(&dev_priv->ring.map, dev);
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if (dev_priv->ring.map.handle == NULL) {
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i915_dma_cleanup(dev);
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@ -27,6 +27,7 @@
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*
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*/
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#include <linux/device.h>
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#include "drmP.h"
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#include "drm.h"
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#include "i915_drm.h"
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@ -66,6 +67,12 @@ static int i915_suspend(struct drm_device *dev, pm_message_t state)
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i915_save_state(dev);
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/* If KMS is active, we do the leavevt stuff here */
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if (drm_core_check_feature(dev, DRIVER_MODESET) && i915_gem_idle(dev)) {
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dev_err(&dev->pdev->dev, "GEM idle failed, aborting suspend\n");
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return -EBUSY;
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}
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intel_opregion_free(dev);
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if (state.event == PM_EVENT_SUSPEND) {
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@ -79,6 +86,9 @@ static int i915_suspend(struct drm_device *dev, pm_message_t state)
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static int i915_resume(struct drm_device *dev)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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int ret = 0;
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pci_set_power_state(dev->pdev, PCI_D0);
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pci_restore_state(dev->pdev);
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if (pci_enable_device(dev->pdev))
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@ -89,7 +99,18 @@ static int i915_resume(struct drm_device *dev)
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intel_opregion_init(dev);
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return 0;
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/* KMS EnterVT equivalent */
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if (drm_core_check_feature(dev, DRIVER_MODESET)) {
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mutex_lock(&dev->struct_mutex);
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dev_priv->mm.suspended = 0;
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ret = i915_gem_init_ringbuffer(dev);
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if (ret != 0)
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ret = -1;
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mutex_unlock(&dev->struct_mutex);
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}
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return ret;
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}
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static struct vm_operations_struct i915_gem_vm_ops = {
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@ -618,6 +618,7 @@ int i915_gem_init_ringbuffer(struct drm_device *dev);
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void i915_gem_cleanup_ringbuffer(struct drm_device *dev);
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int i915_gem_do_init(struct drm_device *dev, unsigned long start,
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unsigned long end);
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int i915_gem_idle(struct drm_device *dev);
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int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
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int i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj,
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int write);
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@ -34,10 +34,6 @@
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#define I915_GEM_GPU_DOMAINS (~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT))
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static void
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i915_gem_object_set_to_gpu_domain(struct drm_gem_object *obj,
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uint32_t read_domains,
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uint32_t write_domain);
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static void i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj);
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static void i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj);
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static void i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj);
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@ -2021,30 +2017,28 @@ i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj, int write)
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* drm_agp_chipset_flush
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*/
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static void
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i915_gem_object_set_to_gpu_domain(struct drm_gem_object *obj,
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uint32_t read_domains,
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uint32_t write_domain)
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i915_gem_object_set_to_gpu_domain(struct drm_gem_object *obj)
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{
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struct drm_device *dev = obj->dev;
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struct drm_i915_gem_object *obj_priv = obj->driver_private;
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uint32_t invalidate_domains = 0;
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uint32_t flush_domains = 0;
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BUG_ON(read_domains & I915_GEM_DOMAIN_CPU);
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BUG_ON(write_domain == I915_GEM_DOMAIN_CPU);
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BUG_ON(obj->pending_read_domains & I915_GEM_DOMAIN_CPU);
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BUG_ON(obj->pending_write_domain == I915_GEM_DOMAIN_CPU);
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#if WATCH_BUF
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DRM_INFO("%s: object %p read %08x -> %08x write %08x -> %08x\n",
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__func__, obj,
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obj->read_domains, read_domains,
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obj->write_domain, write_domain);
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obj->read_domains, obj->pending_read_domains,
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obj->write_domain, obj->pending_write_domain);
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#endif
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/*
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* If the object isn't moving to a new write domain,
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* let the object stay in multiple read domains
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*/
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if (write_domain == 0)
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read_domains |= obj->read_domains;
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if (obj->pending_write_domain == 0)
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obj->pending_read_domains |= obj->read_domains;
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else
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obj_priv->dirty = 1;
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@ -2054,15 +2048,17 @@ i915_gem_object_set_to_gpu_domain(struct drm_gem_object *obj,
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* any read domains which differ from the old
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* write domain
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*/
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if (obj->write_domain && obj->write_domain != read_domains) {
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if (obj->write_domain &&
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obj->write_domain != obj->pending_read_domains) {
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flush_domains |= obj->write_domain;
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invalidate_domains |= read_domains & ~obj->write_domain;
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invalidate_domains |=
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obj->pending_read_domains & ~obj->write_domain;
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}
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/*
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* Invalidate any read caches which may have
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* stale data. That is, any new read domains.
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*/
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invalidate_domains |= read_domains & ~obj->read_domains;
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invalidate_domains |= obj->pending_read_domains & ~obj->read_domains;
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if ((flush_domains | invalidate_domains) & I915_GEM_DOMAIN_CPU) {
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#if WATCH_BUF
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DRM_INFO("%s: CPU domain flush %08x invalidate %08x\n",
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@ -2071,9 +2067,15 @@ i915_gem_object_set_to_gpu_domain(struct drm_gem_object *obj,
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i915_gem_clflush_object(obj);
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}
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if ((write_domain | flush_domains) != 0)
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obj->write_domain = write_domain;
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obj->read_domains = read_domains;
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/* The actual obj->write_domain will be updated with
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* pending_write_domain after we emit the accumulated flush for all
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* of our domain changes in execbuffers (which clears objects'
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* write_domains). So if we have a current write domain that we
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* aren't changing, set pending_write_domain to that.
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*/
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if (flush_domains == 0 && obj->pending_write_domain == 0)
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obj->pending_write_domain = obj->write_domain;
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obj->read_domains = obj->pending_read_domains;
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dev->invalidate_domains |= invalidate_domains;
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dev->flush_domains |= flush_domains;
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@ -2583,9 +2585,7 @@ i915_gem_execbuffer(struct drm_device *dev, void *data,
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struct drm_gem_object *obj = object_list[i];
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/* Compute new gpu domains and update invalidate/flush */
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i915_gem_object_set_to_gpu_domain(obj,
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obj->pending_read_domains,
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obj->pending_write_domain);
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i915_gem_object_set_to_gpu_domain(obj);
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}
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i915_verify_inactive(dev, __FILE__, __LINE__);
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@ -2604,6 +2604,12 @@ i915_gem_execbuffer(struct drm_device *dev, void *data,
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(void)i915_add_request(dev, dev->flush_domains);
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}
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for (i = 0; i < args->buffer_count; i++) {
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struct drm_gem_object *obj = object_list[i];
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obj->write_domain = obj->pending_write_domain;
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}
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i915_verify_inactive(dev, __FILE__, __LINE__);
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#if WATCH_COHERENCY
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@ -2866,6 +2872,13 @@ i915_gem_busy_ioctl(struct drm_device *dev, void *data,
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return -EBADF;
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}
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/* Update the active list for the hardware's current position.
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* Otherwise this only updates on a delayed timer or when irqs are
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* actually unmasked, and our working set ends up being larger than
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* required.
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*/
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i915_gem_retire_requests(dev);
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obj_priv = obj->driver_private;
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/* Don't count being on the flushing list against the object being
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* done. Otherwise, a buffer left on the flushing list but not getting
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@ -2967,7 +2980,7 @@ i915_gem_evict_from_list(struct drm_device *dev, struct list_head *head)
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return 0;
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}
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static int
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int
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i915_gem_idle(struct drm_device *dev)
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{
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drm_i915_private_t *dev_priv = dev->dev_private;
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@ -3130,16 +3143,20 @@ static void
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i915_gem_cleanup_hws(struct drm_device *dev)
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{
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drm_i915_private_t *dev_priv = dev->dev_private;
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struct drm_gem_object *obj = dev_priv->hws_obj;
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struct drm_i915_gem_object *obj_priv = obj->driver_private;
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struct drm_gem_object *obj;
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struct drm_i915_gem_object *obj_priv;
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if (dev_priv->hws_obj == NULL)
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return;
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obj = dev_priv->hws_obj;
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obj_priv = obj->driver_private;
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kunmap(obj_priv->page_list[0]);
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i915_gem_object_unpin(obj);
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drm_gem_object_unreference(obj);
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dev_priv->hws_obj = NULL;
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memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map));
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dev_priv->hw_status_page = NULL;
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@ -1008,6 +1008,7 @@ static int intel_crtc_cursor_set(struct drm_crtc *crtc,
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temp = CURSOR_MODE_DISABLE;
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addr = 0;
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bo = NULL;
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mutex_lock(&dev->struct_mutex);
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goto finish;
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}
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