Merge branch 'sh-pfc-for-v4.6' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel
This commit is contained in:
Linus Walleij
Коммит
834fa2fdbe
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@ -5,7 +5,6 @@
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if ARCH_SHMOBILE || SUPERH
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config PINCTRL_SH_PFC
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select GPIO_SH_PFC if ARCH_REQUIRE_GPIOLIB
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select PINMUX
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select PINCONF
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select GENERIC_PINCONF
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@ -13,12 +12,12 @@ config PINCTRL_SH_PFC
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help
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This enables pin control drivers for SH and SH Mobile platforms
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config GPIO_SH_PFC
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bool "SuperH PFC GPIO support"
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depends on PINCTRL_SH_PFC && GPIOLIB
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config PINCTRL_SH_PFC_GPIO
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select GPIOLIB
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select PINCTRL_SH_PFC
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bool
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help
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This enables support for GPIOs within the SoC's pin function
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controller.
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This enables pin control and GPIO drivers for SH/SH Mobile platforms
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config PINCTRL_PFC_EMEV2
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def_bool y
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@ -28,12 +27,12 @@ config PINCTRL_PFC_EMEV2
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config PINCTRL_PFC_R8A73A4
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def_bool y
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depends on ARCH_R8A73A4
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select PINCTRL_SH_PFC
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select PINCTRL_SH_PFC_GPIO
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config PINCTRL_PFC_R8A7740
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def_bool y
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depends on ARCH_R8A7740
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select PINCTRL_SH_PFC
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select PINCTRL_SH_PFC_GPIO
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config PINCTRL_PFC_R8A7778
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def_bool y
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@ -73,79 +72,66 @@ config PINCTRL_PFC_R8A7795
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config PINCTRL_PFC_SH7203
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def_bool y
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depends on CPU_SUBTYPE_SH7203
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depends on GPIOLIB
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select PINCTRL_SH_PFC
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select PINCTRL_SH_PFC_GPIO
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config PINCTRL_PFC_SH7264
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def_bool y
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depends on CPU_SUBTYPE_SH7264
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depends on GPIOLIB
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select PINCTRL_SH_PFC
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select PINCTRL_SH_PFC_GPIO
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config PINCTRL_PFC_SH7269
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def_bool y
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depends on CPU_SUBTYPE_SH7269
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depends on GPIOLIB
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select PINCTRL_SH_PFC
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select PINCTRL_SH_PFC_GPIO
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config PINCTRL_PFC_SH73A0
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def_bool y
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depends on ARCH_SH73A0
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select PINCTRL_SH_PFC
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select PINCTRL_SH_PFC_GPIO
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select REGULATOR
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config PINCTRL_PFC_SH7720
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def_bool y
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depends on CPU_SUBTYPE_SH7720
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depends on GPIOLIB
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select PINCTRL_SH_PFC
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select PINCTRL_SH_PFC_GPIO
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config PINCTRL_PFC_SH7722
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def_bool y
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depends on CPU_SUBTYPE_SH7722
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depends on GPIOLIB
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select PINCTRL_SH_PFC
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select PINCTRL_SH_PFC_GPIO
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config PINCTRL_PFC_SH7723
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def_bool y
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depends on CPU_SUBTYPE_SH7723
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depends on GPIOLIB
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select PINCTRL_SH_PFC
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select PINCTRL_SH_PFC_GPIO
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config PINCTRL_PFC_SH7724
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def_bool y
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depends on CPU_SUBTYPE_SH7724
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depends on GPIOLIB
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select PINCTRL_SH_PFC
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select PINCTRL_SH_PFC_GPIO
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config PINCTRL_PFC_SH7734
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def_bool y
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depends on CPU_SUBTYPE_SH7734
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depends on GPIOLIB
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select PINCTRL_SH_PFC
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select PINCTRL_SH_PFC_GPIO
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config PINCTRL_PFC_SH7757
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def_bool y
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depends on CPU_SUBTYPE_SH7757
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depends on GPIOLIB
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select PINCTRL_SH_PFC
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select PINCTRL_SH_PFC_GPIO
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config PINCTRL_PFC_SH7785
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def_bool y
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depends on CPU_SUBTYPE_SH7785
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depends on GPIOLIB
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select PINCTRL_SH_PFC
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select PINCTRL_SH_PFC_GPIO
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config PINCTRL_PFC_SH7786
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def_bool y
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depends on CPU_SUBTYPE_SH7786
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depends on GPIOLIB
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select PINCTRL_SH_PFC
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select PINCTRL_SH_PFC_GPIO
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config PINCTRL_PFC_SHX3
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def_bool y
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depends on CPU_SUBTYPE_SHX3
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depends on GPIOLIB
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select PINCTRL_SH_PFC
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select PINCTRL_SH_PFC_GPIO
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endif
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@ -1,8 +1,5 @@
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sh-pfc-objs = core.o pinctrl.o
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ifeq ($(CONFIG_GPIO_SH_PFC),y)
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sh-pfc-objs += gpio.o
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endif
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obj-$(CONFIG_PINCTRL_SH_PFC) += sh-pfc.o
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obj-$(CONFIG_PINCTRL_SH_PFC) += core.o pinctrl.o
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obj-$(CONFIG_PINCTRL_SH_PFC_GPIO) += gpio.o
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obj-$(CONFIG_PINCTRL_PFC_EMEV2) += pfc-emev2.o
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obj-$(CONFIG_PINCTRL_PFC_R8A73A4) += pfc-r8a73a4.o
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obj-$(CONFIG_PINCTRL_PFC_R8A7740) += pfc-r8a7740.o
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@ -558,7 +558,7 @@ static int sh_pfc_probe(struct platform_device *pdev)
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if (unlikely(ret != 0))
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return ret;
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#ifdef CONFIG_GPIO_SH_PFC
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#ifdef CONFIG_PINCTRL_SH_PFC_GPIO
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/*
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* Then the GPIO chip
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*/
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@ -584,7 +584,7 @@ static int sh_pfc_remove(struct platform_device *pdev)
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{
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struct sh_pfc *pfc = platform_get_drvdata(pdev);
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#ifdef CONFIG_GPIO_SH_PFC
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#ifdef CONFIG_PINCTRL_SH_PFC_GPIO
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sh_pfc_unregister_gpiochip(pfc);
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#endif
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sh_pfc_unregister_pinctrl(pfc);
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@ -591,547 +591,547 @@ static const u16 pinmux_data[] = {
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PINMUX_SINGLE(IRQ3_B),
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/* IPSR0 */
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PINMUX_IPSR_DATA(IP0_1_0, A0),
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PINMUX_IPSR_DATA(IP0_1_0, ST0_CLKIN),
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PINMUX_IPSR_GPSR(IP0_1_0, A0),
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PINMUX_IPSR_GPSR(IP0_1_0, ST0_CLKIN),
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PINMUX_IPSR_MSEL(IP0_1_0, LCD_DATA0_A, SEL_LCDC_0),
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PINMUX_IPSR_MSEL(IP0_1_0, TCLKA_C, SEL_MTU2_CLK_1),
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PINMUX_IPSR_DATA(IP0_3_2, A1),
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PINMUX_IPSR_DATA(IP0_3_2, ST0_REQ),
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PINMUX_IPSR_GPSR(IP0_3_2, A1),
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PINMUX_IPSR_GPSR(IP0_3_2, ST0_REQ),
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PINMUX_IPSR_MSEL(IP0_3_2, LCD_DATA1_A, SEL_LCDC_0),
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PINMUX_IPSR_MSEL(IP0_3_2, TCLKB_C, SEL_MTU2_CLK_1),
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PINMUX_IPSR_DATA(IP0_5_4, A2),
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PINMUX_IPSR_DATA(IP0_5_4, ST0_SYC),
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PINMUX_IPSR_GPSR(IP0_5_4, A2),
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PINMUX_IPSR_GPSR(IP0_5_4, ST0_SYC),
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PINMUX_IPSR_MSEL(IP0_5_4, LCD_DATA2_A, SEL_LCDC_0),
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PINMUX_IPSR_MSEL(IP0_5_4, TCLKC_C, SEL_MTU2_CLK_1),
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PINMUX_IPSR_DATA(IP0_7_6, A3),
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PINMUX_IPSR_DATA(IP0_7_6, ST0_VLD),
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PINMUX_IPSR_GPSR(IP0_7_6, A3),
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PINMUX_IPSR_GPSR(IP0_7_6, ST0_VLD),
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PINMUX_IPSR_MSEL(IP0_7_6, LCD_DATA3_A, SEL_LCDC_0),
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PINMUX_IPSR_MSEL(IP0_7_6, TCLKD_C, SEL_MTU2_CLK_1),
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PINMUX_IPSR_DATA(IP0_9_8, A4),
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PINMUX_IPSR_DATA(IP0_9_8, ST0_D0),
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PINMUX_IPSR_GPSR(IP0_9_8, A4),
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PINMUX_IPSR_GPSR(IP0_9_8, ST0_D0),
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PINMUX_IPSR_MSEL(IP0_9_8, LCD_DATA4_A, SEL_LCDC_0),
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PINMUX_IPSR_MSEL(IP0_9_8, TIOC0A_C, SEL_MTU2_CH0_1),
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PINMUX_IPSR_DATA(IP0_11_10, A5),
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PINMUX_IPSR_DATA(IP0_11_10, ST0_D1),
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PINMUX_IPSR_GPSR(IP0_11_10, A5),
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PINMUX_IPSR_GPSR(IP0_11_10, ST0_D1),
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PINMUX_IPSR_MSEL(IP0_11_10, LCD_DATA5_A, SEL_LCDC_0),
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PINMUX_IPSR_MSEL(IP0_11_10, TIOC0B_C, SEL_MTU2_CH0_1),
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PINMUX_IPSR_DATA(IP0_13_12, A6),
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PINMUX_IPSR_DATA(IP0_13_12, ST0_D2),
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PINMUX_IPSR_GPSR(IP0_13_12, A6),
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PINMUX_IPSR_GPSR(IP0_13_12, ST0_D2),
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PINMUX_IPSR_MSEL(IP0_13_12, LCD_DATA6_A, SEL_LCDC_0),
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PINMUX_IPSR_MSEL(IP0_13_12, TIOC0C_C, SEL_MTU2_CH0_1),
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PINMUX_IPSR_DATA(IP0_15_14, A7),
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PINMUX_IPSR_DATA(IP0_15_14, ST0_D3),
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PINMUX_IPSR_GPSR(IP0_15_14, A7),
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PINMUX_IPSR_GPSR(IP0_15_14, ST0_D3),
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PINMUX_IPSR_MSEL(IP0_15_14, LCD_DATA7_A, SEL_LCDC_0),
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PINMUX_IPSR_MSEL(IP0_15_14, TIOC0D_C, SEL_MTU2_CH0_1),
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PINMUX_IPSR_DATA(IP0_17_16, A8),
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PINMUX_IPSR_DATA(IP0_17_16, ST0_D4),
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PINMUX_IPSR_GPSR(IP0_17_16, A8),
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PINMUX_IPSR_GPSR(IP0_17_16, ST0_D4),
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PINMUX_IPSR_MSEL(IP0_17_16, LCD_DATA8_A, SEL_LCDC_0),
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PINMUX_IPSR_MSEL(IP0_17_16, TIOC1A_C, SEL_MTU2_CH1_2),
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PINMUX_IPSR_DATA(IP0_19_18, A9),
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PINMUX_IPSR_DATA(IP0_19_18, ST0_D5),
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PINMUX_IPSR_GPSR(IP0_19_18, A9),
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PINMUX_IPSR_GPSR(IP0_19_18, ST0_D5),
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PINMUX_IPSR_MSEL(IP0_19_18, LCD_DATA9_A, SEL_LCDC_0),
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PINMUX_IPSR_MSEL(IP0_19_18, TIOC1B_C, SEL_MTU2_CH1_2),
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PINMUX_IPSR_DATA(IP0_21_20, A10),
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PINMUX_IPSR_DATA(IP0_21_20, ST0_D6),
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PINMUX_IPSR_GPSR(IP0_21_20, A10),
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PINMUX_IPSR_GPSR(IP0_21_20, ST0_D6),
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PINMUX_IPSR_MSEL(IP0_21_20, LCD_DATA10_A, SEL_LCDC_0),
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PINMUX_IPSR_MSEL(IP0_21_20, TIOC2A_C, SEL_MTU2_CH2_2),
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PINMUX_IPSR_DATA(IP0_23_22, A11),
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PINMUX_IPSR_DATA(IP0_23_22, ST0_D7),
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PINMUX_IPSR_GPSR(IP0_23_22, A11),
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PINMUX_IPSR_GPSR(IP0_23_22, ST0_D7),
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PINMUX_IPSR_MSEL(IP0_23_22, LCD_DATA11_A, SEL_LCDC_0),
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PINMUX_IPSR_MSEL(IP0_23_22, TIOC2B_C, SEL_MTU2_CH2_2),
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PINMUX_IPSR_DATA(IP0_25_24, A12),
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PINMUX_IPSR_GPSR(IP0_25_24, A12),
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PINMUX_IPSR_MSEL(IP0_25_24, LCD_DATA12_A, SEL_LCDC_0),
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PINMUX_IPSR_MSEL(IP0_25_24, TIOC3A_C, SEL_MTU2_CH3_1),
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PINMUX_IPSR_DATA(IP0_27_26, A13),
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PINMUX_IPSR_GPSR(IP0_27_26, A13),
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PINMUX_IPSR_MSEL(IP0_27_26, LCD_DATA13_A, SEL_LCDC_0),
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PINMUX_IPSR_MSEL(IP0_27_26, TIOC3B_C, SEL_MTU2_CH3_1),
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PINMUX_IPSR_DATA(IP0_29_28, A14),
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PINMUX_IPSR_GPSR(IP0_29_28, A14),
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PINMUX_IPSR_MSEL(IP0_29_28, LCD_DATA14_A, SEL_LCDC_0),
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PINMUX_IPSR_MSEL(IP0_29_28, TIOC3C_C, SEL_MTU2_CH3_1),
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PINMUX_IPSR_DATA(IP0_31_30, A15),
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PINMUX_IPSR_DATA(IP0_31_30, ST0_VCO_CLKIN),
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PINMUX_IPSR_GPSR(IP0_31_30, A15),
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PINMUX_IPSR_GPSR(IP0_31_30, ST0_VCO_CLKIN),
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PINMUX_IPSR_MSEL(IP0_31_30, LCD_DATA15_A, SEL_LCDC_0),
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PINMUX_IPSR_MSEL(IP0_31_30, TIOC3D_C, SEL_MTU2_CH3_1),
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/* IPSR1 */
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PINMUX_IPSR_DATA(IP1_1_0, A16),
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PINMUX_IPSR_DATA(IP1_1_0, ST0_PWM),
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PINMUX_IPSR_GPSR(IP1_1_0, A16),
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PINMUX_IPSR_GPSR(IP1_1_0, ST0_PWM),
|
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PINMUX_IPSR_MSEL(IP1_1_0, LCD_DON_A, SEL_LCDC_0),
|
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PINMUX_IPSR_MSEL(IP1_1_0, TIOC4A_C, SEL_MTU2_CH4_1),
|
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|
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PINMUX_IPSR_DATA(IP1_3_2, A17),
|
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PINMUX_IPSR_DATA(IP1_3_2, ST1_VCO_CLKIN),
|
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PINMUX_IPSR_GPSR(IP1_3_2, A17),
|
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PINMUX_IPSR_GPSR(IP1_3_2, ST1_VCO_CLKIN),
|
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PINMUX_IPSR_MSEL(IP1_3_2, LCD_CL1_A, SEL_LCDC_0),
|
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PINMUX_IPSR_MSEL(IP1_3_2, TIOC4B_C, SEL_MTU2_CH4_1),
|
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|
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PINMUX_IPSR_DATA(IP1_5_4, A18),
|
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PINMUX_IPSR_DATA(IP1_5_4, ST1_PWM),
|
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PINMUX_IPSR_GPSR(IP1_5_4, A18),
|
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PINMUX_IPSR_GPSR(IP1_5_4, ST1_PWM),
|
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PINMUX_IPSR_MSEL(IP1_5_4, LCD_CL2_A, SEL_LCDC_0),
|
||||
PINMUX_IPSR_MSEL(IP1_5_4, TIOC4C_C, SEL_MTU2_CH4_1),
|
||||
|
||||
PINMUX_IPSR_DATA(IP1_7_6, A19),
|
||||
PINMUX_IPSR_DATA(IP1_7_6, ST1_CLKIN),
|
||||
PINMUX_IPSR_GPSR(IP1_7_6, A19),
|
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PINMUX_IPSR_GPSR(IP1_7_6, ST1_CLKIN),
|
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PINMUX_IPSR_MSEL(IP1_7_6, LCD_CLK_A, SEL_LCDC_0),
|
||||
PINMUX_IPSR_MSEL(IP1_7_6, TIOC4D_C, SEL_MTU2_CH4_1),
|
||||
|
||||
PINMUX_IPSR_DATA(IP1_9_8, A20),
|
||||
PINMUX_IPSR_DATA(IP1_9_8, ST1_REQ),
|
||||
PINMUX_IPSR_GPSR(IP1_9_8, A20),
|
||||
PINMUX_IPSR_GPSR(IP1_9_8, ST1_REQ),
|
||||
PINMUX_IPSR_MSEL(IP1_9_8, LCD_FLM_A, SEL_LCDC_0),
|
||||
|
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PINMUX_IPSR_DATA(IP1_11_10, A21),
|
||||
PINMUX_IPSR_DATA(IP1_11_10, ST1_SYC),
|
||||
PINMUX_IPSR_GPSR(IP1_11_10, A21),
|
||||
PINMUX_IPSR_GPSR(IP1_11_10, ST1_SYC),
|
||||
PINMUX_IPSR_MSEL(IP1_11_10, LCD_VCPWC_A, SEL_LCDC_0),
|
||||
|
||||
PINMUX_IPSR_DATA(IP1_13_12, A22),
|
||||
PINMUX_IPSR_DATA(IP1_13_12, ST1_VLD),
|
||||
PINMUX_IPSR_GPSR(IP1_13_12, A22),
|
||||
PINMUX_IPSR_GPSR(IP1_13_12, ST1_VLD),
|
||||
PINMUX_IPSR_MSEL(IP1_13_12, LCD_VEPWC_A, SEL_LCDC_0),
|
||||
|
||||
PINMUX_IPSR_DATA(IP1_15_14, A23),
|
||||
PINMUX_IPSR_DATA(IP1_15_14, ST1_D0),
|
||||
PINMUX_IPSR_GPSR(IP1_15_14, A23),
|
||||
PINMUX_IPSR_GPSR(IP1_15_14, ST1_D0),
|
||||
PINMUX_IPSR_MSEL(IP1_15_14, LCD_M_DISP_A, SEL_LCDC_0),
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||||
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||||
PINMUX_IPSR_DATA(IP1_17_16, A24),
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||||
PINMUX_IPSR_GPSR(IP1_17_16, A24),
|
||||
PINMUX_IPSR_MSEL(IP1_17_16, RX2_D, SEL_SCIF2_3),
|
||||
PINMUX_IPSR_DATA(IP1_17_16, ST1_D1),
|
||||
PINMUX_IPSR_GPSR(IP1_17_16, ST1_D1),
|
||||
|
||||
PINMUX_IPSR_DATA(IP1_19_18, A25),
|
||||
PINMUX_IPSR_GPSR(IP1_19_18, A25),
|
||||
PINMUX_IPSR_MSEL(IP1_17_16, RX2_D, SEL_SCIF2_3),
|
||||
PINMUX_IPSR_DATA(IP1_17_16, ST1_D2),
|
||||
PINMUX_IPSR_GPSR(IP1_17_16, ST1_D2),
|
||||
|
||||
PINMUX_IPSR_DATA(IP1_22_20, D0),
|
||||
PINMUX_IPSR_GPSR(IP1_22_20, D0),
|
||||
PINMUX_IPSR_MSEL(IP1_22_20, SD0_DAT0_A, SEL_SDHI0_0),
|
||||
PINMUX_IPSR_MSEL(IP1_22_20, MMC_D0_A, SEL_MMC_0),
|
||||
PINMUX_IPSR_DATA(IP1_22_20, ST1_D3),
|
||||
PINMUX_IPSR_GPSR(IP1_22_20, ST1_D3),
|
||||
PINMUX_IPSR_MSEL(IP1_22_20, FD0_A, SEL_FLCTL_0),
|
||||
|
||||
PINMUX_IPSR_DATA(IP1_25_23, D1),
|
||||
PINMUX_IPSR_GPSR(IP1_25_23, D1),
|
||||
PINMUX_IPSR_MSEL(IP1_25_23, SD0_DAT0_A, SEL_SDHI0_0),
|
||||
PINMUX_IPSR_MSEL(IP1_25_23, MMC_D1_A, SEL_MMC_0),
|
||||
PINMUX_IPSR_DATA(IP1_25_23, ST1_D4),
|
||||
PINMUX_IPSR_GPSR(IP1_25_23, ST1_D4),
|
||||
PINMUX_IPSR_MSEL(IP1_25_23, FD1_A, SEL_FLCTL_0),
|
||||
|
||||
PINMUX_IPSR_DATA(IP1_28_26, D2),
|
||||
PINMUX_IPSR_GPSR(IP1_28_26, D2),
|
||||
PINMUX_IPSR_MSEL(IP1_28_26, SD0_DAT0_A, SEL_SDHI0_0),
|
||||
PINMUX_IPSR_MSEL(IP1_28_26, MMC_D2_A, SEL_MMC_0),
|
||||
PINMUX_IPSR_DATA(IP1_28_26, ST1_D5),
|
||||
PINMUX_IPSR_GPSR(IP1_28_26, ST1_D5),
|
||||
PINMUX_IPSR_MSEL(IP1_28_26, FD2_A, SEL_FLCTL_0),
|
||||
|
||||
PINMUX_IPSR_DATA(IP1_31_29, D3),
|
||||
PINMUX_IPSR_GPSR(IP1_31_29, D3),
|
||||
PINMUX_IPSR_MSEL(IP1_31_29, SD0_DAT0_A, SEL_SDHI0_0),
|
||||
PINMUX_IPSR_MSEL(IP1_31_29, MMC_D3_A, SEL_MMC_0),
|
||||
PINMUX_IPSR_DATA(IP1_31_29, ST1_D6),
|
||||
PINMUX_IPSR_GPSR(IP1_31_29, ST1_D6),
|
||||
PINMUX_IPSR_MSEL(IP1_31_29, FD3_A, SEL_FLCTL_0),
|
||||
|
||||
/* IPSR2 */
|
||||
PINMUX_IPSR_DATA(IP2_2_0, D4),
|
||||
PINMUX_IPSR_GPSR(IP2_2_0, D4),
|
||||
PINMUX_IPSR_MSEL(IP2_2_0, SD0_CD_A, SEL_SDHI0_0),
|
||||
PINMUX_IPSR_MSEL(IP2_2_0, MMC_D4_A, SEL_MMC_0),
|
||||
PINMUX_IPSR_DATA(IP2_2_0, ST1_D7),
|
||||
PINMUX_IPSR_GPSR(IP2_2_0, ST1_D7),
|
||||
PINMUX_IPSR_MSEL(IP2_2_0, FD4_A, SEL_FLCTL_0),
|
||||
|
||||
PINMUX_IPSR_DATA(IP2_4_3, D5),
|
||||
PINMUX_IPSR_GPSR(IP2_4_3, D5),
|
||||
PINMUX_IPSR_MSEL(IP2_4_3, SD0_WP_A, SEL_SDHI0_0),
|
||||
PINMUX_IPSR_MSEL(IP2_4_3, MMC_D5_A, SEL_MMC_0),
|
||||
PINMUX_IPSR_MSEL(IP2_4_3, FD5_A, SEL_FLCTL_0),
|
||||
|
||||
PINMUX_IPSR_DATA(IP2_7_5, D6),
|
||||
PINMUX_IPSR_GPSR(IP2_7_5, D6),
|
||||
PINMUX_IPSR_MSEL(IP2_7_5, RSPI_RSPCK_A, SEL_RSPI_0),
|
||||
PINMUX_IPSR_MSEL(IP2_7_5, MMC_D6_A, SEL_MMC_0),
|
||||
PINMUX_IPSR_MSEL(IP2_7_5, QSPCLK_A, SEL_RQSPI_0),
|
||||
PINMUX_IPSR_MSEL(IP2_7_5, FD6_A, SEL_FLCTL_0),
|
||||
|
||||
PINMUX_IPSR_DATA(IP2_10_8, D7),
|
||||
PINMUX_IPSR_GPSR(IP2_10_8, D7),
|
||||
PINMUX_IPSR_MSEL(IP2_10_8, RSPI_SSL_A, SEL_RSPI_0),
|
||||
PINMUX_IPSR_MSEL(IP2_10_8, MMC_D7_A, SEL_MMC_0),
|
||||
PINMUX_IPSR_MSEL(IP2_10_8, QSSL_A, SEL_RQSPI_0),
|
||||
PINMUX_IPSR_MSEL(IP2_10_8, FD7_A, SEL_FLCTL_0),
|
||||
|
||||
PINMUX_IPSR_DATA(IP2_13_11, D8),
|
||||
PINMUX_IPSR_GPSR(IP2_13_11, D8),
|
||||
PINMUX_IPSR_MSEL(IP2_13_11, SD0_CLK_A, SEL_SDHI0_0),
|
||||
PINMUX_IPSR_MSEL(IP2_13_11, MMC_CLK_A, SEL_MMC_0),
|
||||
PINMUX_IPSR_MSEL(IP2_13_11, QIO2_A, SEL_RQSPI_0),
|
||||
PINMUX_IPSR_MSEL(IP2_13_11, FCE_A, SEL_FLCTL_0),
|
||||
PINMUX_IPSR_MSEL(IP2_13_11, ET0_GTX_CLK_B, SEL_ET0_1),
|
||||
|
||||
PINMUX_IPSR_DATA(IP2_16_14, D9),
|
||||
PINMUX_IPSR_GPSR(IP2_16_14, D9),
|
||||
PINMUX_IPSR_MSEL(IP2_16_14, SD0_CMD_A, SEL_SDHI0_0),
|
||||
PINMUX_IPSR_MSEL(IP2_16_14, MMC_CMD_A, SEL_MMC_0),
|
||||
PINMUX_IPSR_MSEL(IP2_16_14, QIO3_A, SEL_RQSPI_0),
|
||||
PINMUX_IPSR_MSEL(IP2_16_14, FCLE_A, SEL_FLCTL_0),
|
||||
PINMUX_IPSR_MSEL(IP2_16_14, ET0_ETXD1_B, SEL_ET0_1),
|
||||
|
||||
PINMUX_IPSR_DATA(IP2_19_17, D10),
|
||||
PINMUX_IPSR_GPSR(IP2_19_17, D10),
|
||||
PINMUX_IPSR_MSEL(IP2_19_17, RSPI_MOSI_A, SEL_RSPI_0),
|
||||
PINMUX_IPSR_MSEL(IP2_19_17, QMO_QIO0_A, SEL_RQSPI_0),
|
||||
PINMUX_IPSR_MSEL(IP2_19_17, FALE_A, SEL_FLCTL_0),
|
||||
PINMUX_IPSR_MSEL(IP2_19_17, ET0_ETXD2_B, SEL_ET0_1),
|
||||
|
||||
PINMUX_IPSR_DATA(IP2_22_20, D11),
|
||||
PINMUX_IPSR_GPSR(IP2_22_20, D11),
|
||||
PINMUX_IPSR_MSEL(IP2_22_20, RSPI_MISO_A, SEL_RSPI_0),
|
||||
PINMUX_IPSR_MSEL(IP2_22_20, QMI_QIO1_A, SEL_RQSPI_0),
|
||||
PINMUX_IPSR_MSEL(IP2_22_20, FRE_A, SEL_FLCTL_0),
|
||||
|
||||
PINMUX_IPSR_DATA(IP2_24_23, D12),
|
||||
PINMUX_IPSR_GPSR(IP2_24_23, D12),
|
||||
PINMUX_IPSR_MSEL(IP2_24_23, FWE_A, SEL_FLCTL_0),
|
||||
PINMUX_IPSR_MSEL(IP2_24_23, ET0_ETXD5_B, SEL_ET0_1),
|
||||
|
||||
PINMUX_IPSR_DATA(IP2_27_25, D13),
|
||||
PINMUX_IPSR_GPSR(IP2_27_25, D13),
|
||||
PINMUX_IPSR_MSEL(IP2_27_25, RX2_B, SEL_SCIF2_1),
|
||||
PINMUX_IPSR_MSEL(IP2_27_25, FRB_A, SEL_FLCTL_0),
|
||||
PINMUX_IPSR_MSEL(IP2_27_25, ET0_ETXD6_B, SEL_ET0_1),
|
||||
|
||||
PINMUX_IPSR_DATA(IP2_30_28, D14),
|
||||
PINMUX_IPSR_GPSR(IP2_30_28, D14),
|
||||
PINMUX_IPSR_MSEL(IP2_30_28, TX2_B, SEL_SCIF2_1),
|
||||
PINMUX_IPSR_MSEL(IP2_30_28, FSE_A, SEL_FLCTL_0),
|
||||
PINMUX_IPSR_MSEL(IP2_30_28, ET0_TX_CLK_B, SEL_ET0_1),
|
||||
|
||||
/* IPSR3 */
|
||||
PINMUX_IPSR_DATA(IP3_1_0, D15),
|
||||
PINMUX_IPSR_GPSR(IP3_1_0, D15),
|
||||
PINMUX_IPSR_MSEL(IP3_1_0, SCK2_B, SEL_SCIF2_1),
|
||||
|
||||
PINMUX_IPSR_DATA(IP3_2, CS1_A26),
|
||||
PINMUX_IPSR_GPSR(IP3_2, CS1_A26),
|
||||
PINMUX_IPSR_MSEL(IP3_2, QIO3_B, SEL_RQSPI_1),
|
||||
|
||||
PINMUX_IPSR_DATA(IP3_5_3, EX_CS1),
|
||||
PINMUX_IPSR_GPSR(IP3_5_3, EX_CS1),
|
||||
PINMUX_IPSR_MSEL(IP3_5_3, RX3_B, SEL_SCIF2_1),
|
||||
PINMUX_IPSR_DATA(IP3_5_3, ATACS0),
|
||||
PINMUX_IPSR_GPSR(IP3_5_3, ATACS0),
|
||||
PINMUX_IPSR_MSEL(IP3_5_3, QIO2_B, SEL_RQSPI_1),
|
||||
PINMUX_IPSR_DATA(IP3_5_3, ET0_ETXD0),
|
||||
PINMUX_IPSR_GPSR(IP3_5_3, ET0_ETXD0),
|
||||
|
||||
PINMUX_IPSR_DATA(IP3_8_6, EX_CS2),
|
||||
PINMUX_IPSR_GPSR(IP3_8_6, EX_CS2),
|
||||
PINMUX_IPSR_MSEL(IP3_8_6, TX3_B, SEL_SCIF3_1),
|
||||
PINMUX_IPSR_DATA(IP3_8_6, ATACS1),
|
||||
PINMUX_IPSR_GPSR(IP3_8_6, ATACS1),
|
||||
PINMUX_IPSR_MSEL(IP3_8_6, QSPCLK_B, SEL_RQSPI_1),
|
||||
PINMUX_IPSR_MSEL(IP3_8_6, ET0_GTX_CLK_A, SEL_ET0_0),
|
||||
|
||||
PINMUX_IPSR_DATA(IP3_11_9, EX_CS3),
|
||||
PINMUX_IPSR_GPSR(IP3_11_9, EX_CS3),
|
||||
PINMUX_IPSR_MSEL(IP3_11_9, SD1_CD_A, SEL_SDHI1_0),
|
||||
PINMUX_IPSR_DATA(IP3_11_9, ATARD),
|
||||
PINMUX_IPSR_GPSR(IP3_11_9, ATARD),
|
||||
PINMUX_IPSR_MSEL(IP3_11_9, QMO_QIO0_B, SEL_RQSPI_1),
|
||||
PINMUX_IPSR_MSEL(IP3_11_9, ET0_ETXD1_A, SEL_ET0_0),
|
||||
|
||||
PINMUX_IPSR_DATA(IP3_14_12, EX_CS4),
|
||||
PINMUX_IPSR_GPSR(IP3_14_12, EX_CS4),
|
||||
PINMUX_IPSR_MSEL(IP3_14_12, SD1_WP_A, SEL_SDHI1_0),
|
||||
PINMUX_IPSR_DATA(IP3_14_12, ATAWR),
|
||||
PINMUX_IPSR_GPSR(IP3_14_12, ATAWR),
|
||||
PINMUX_IPSR_MSEL(IP3_14_12, QMI_QIO1_B, SEL_RQSPI_1),
|
||||
PINMUX_IPSR_MSEL(IP3_14_12, ET0_ETXD2_A, SEL_ET0_0),
|
||||
|
||||
PINMUX_IPSR_DATA(IP3_17_15, EX_CS5),
|
||||
PINMUX_IPSR_GPSR(IP3_17_15, EX_CS5),
|
||||
PINMUX_IPSR_MSEL(IP3_17_15, SD1_CMD_A, SEL_SDHI1_0),
|
||||
PINMUX_IPSR_DATA(IP3_17_15, ATADIR),
|
||||
PINMUX_IPSR_GPSR(IP3_17_15, ATADIR),
|
||||
PINMUX_IPSR_MSEL(IP3_17_15, QSSL_B, SEL_RQSPI_1),
|
||||
PINMUX_IPSR_MSEL(IP3_17_15, ET0_ETXD3_A, SEL_ET0_0),
|
||||
|
||||
PINMUX_IPSR_DATA(IP3_19_18, RD_WR),
|
||||
PINMUX_IPSR_DATA(IP3_19_18, TCLK0),
|
||||
PINMUX_IPSR_GPSR(IP3_19_18, RD_WR),
|
||||
PINMUX_IPSR_GPSR(IP3_19_18, TCLK0),
|
||||
PINMUX_IPSR_MSEL(IP3_19_18, CAN_CLK_B, SEL_RCAN_CLK_1),
|
||||
PINMUX_IPSR_DATA(IP3_19_18, ET0_ETXD4),
|
||||
PINMUX_IPSR_GPSR(IP3_19_18, ET0_ETXD4),
|
||||
|
||||
PINMUX_IPSR_DATA(IP3_20, EX_WAIT0),
|
||||
PINMUX_IPSR_GPSR(IP3_20, EX_WAIT0),
|
||||
PINMUX_IPSR_MSEL(IP3_20, TCLK1_B, SEL_TMU_1),
|
||||
|
||||
PINMUX_IPSR_DATA(IP3_23_21, EX_WAIT1),
|
||||
PINMUX_IPSR_GPSR(IP3_23_21, EX_WAIT1),
|
||||
PINMUX_IPSR_MSEL(IP3_23_21, SD1_DAT0_A, SEL_SDHI1_0),
|
||||
PINMUX_IPSR_DATA(IP3_23_21, DREQ2),
|
||||
PINMUX_IPSR_GPSR(IP3_23_21, DREQ2),
|
||||
PINMUX_IPSR_MSEL(IP3_23_21, CAN1_TX_C, SEL_RCAN1_2),
|
||||
PINMUX_IPSR_MSEL(IP3_23_21, ET0_LINK_C, SEL_ET0_CTL_2),
|
||||
PINMUX_IPSR_MSEL(IP3_23_21, ET0_ETXD5_A, SEL_ET0_0),
|
||||
|
||||
PINMUX_IPSR_DATA(IP3_26_24, EX_WAIT2),
|
||||
PINMUX_IPSR_GPSR(IP3_26_24, EX_WAIT2),
|
||||
PINMUX_IPSR_MSEL(IP3_26_24, SD1_DAT1_A, SEL_SDHI1_0),
|
||||
PINMUX_IPSR_DATA(IP3_26_24, DACK2),
|
||||
PINMUX_IPSR_GPSR(IP3_26_24, DACK2),
|
||||
PINMUX_IPSR_MSEL(IP3_26_24, CAN1_RX_C, SEL_RCAN1_2),
|
||||
PINMUX_IPSR_MSEL(IP3_26_24, ET0_MAGIC_C, SEL_ET0_CTL_2),
|
||||
PINMUX_IPSR_MSEL(IP3_26_24, ET0_ETXD6_A, SEL_ET0_0),
|
||||
|
||||
PINMUX_IPSR_DATA(IP3_29_27, DRACK0),
|
||||
PINMUX_IPSR_GPSR(IP3_29_27, DRACK0),
|
||||
PINMUX_IPSR_MSEL(IP3_29_27, SD1_DAT2_A, SEL_SDHI1_0),
|
||||
PINMUX_IPSR_DATA(IP3_29_27, ATAG),
|
||||
PINMUX_IPSR_GPSR(IP3_29_27, ATAG),
|
||||
PINMUX_IPSR_MSEL(IP3_29_27, TCLK1_A, SEL_TMU_0),
|
||||
PINMUX_IPSR_DATA(IP3_29_27, ET0_ETXD7),
|
||||
PINMUX_IPSR_GPSR(IP3_29_27, ET0_ETXD7),
|
||||
|
||||
/* IPSR4 */
|
||||
PINMUX_IPSR_MSEL(IP4_2_0, HCTS0_A, SEL_HSCIF_0),
|
||||
PINMUX_IPSR_MSEL(IP4_2_0, CTS1_A, SEL_SCIF1_0),
|
||||
PINMUX_IPSR_DATA(IP4_2_0, VI0_FIELD),
|
||||
PINMUX_IPSR_GPSR(IP4_2_0, VI0_FIELD),
|
||||
PINMUX_IPSR_MSEL(IP4_2_0, RMII0_RXD1_A, SEL_RMII_0),
|
||||
PINMUX_IPSR_DATA(IP4_2_0, ET0_ERXD7),
|
||||
PINMUX_IPSR_GPSR(IP4_2_0, ET0_ERXD7),
|
||||
|
||||
PINMUX_IPSR_MSEL(IP4_5_3, HRTS0_A, SEL_HSCIF_0),
|
||||
PINMUX_IPSR_MSEL(IP4_5_3, RTS1_A, SEL_SCIF1_0),
|
||||
PINMUX_IPSR_DATA(IP4_5_3, VI0_HSYNC),
|
||||
PINMUX_IPSR_GPSR(IP4_5_3, VI0_HSYNC),
|
||||
PINMUX_IPSR_MSEL(IP4_5_3, RMII0_TXD_EN_A, SEL_RMII_0),
|
||||
PINMUX_IPSR_DATA(IP4_5_3, ET0_RX_DV),
|
||||
PINMUX_IPSR_GPSR(IP4_5_3, ET0_RX_DV),
|
||||
|
||||
PINMUX_IPSR_MSEL(IP4_8_6, HSCK0_A, SEL_HSCIF_0),
|
||||
PINMUX_IPSR_MSEL(IP4_8_6, SCK1_A, SEL_SCIF1_0),
|
||||
PINMUX_IPSR_DATA(IP4_8_6, VI0_VSYNC),
|
||||
PINMUX_IPSR_GPSR(IP4_8_6, VI0_VSYNC),
|
||||
PINMUX_IPSR_MSEL(IP4_8_6, RMII0_RX_ER_A, SEL_RMII_0),
|
||||
PINMUX_IPSR_DATA(IP4_8_6, ET0_RX_ER),
|
||||
PINMUX_IPSR_GPSR(IP4_8_6, ET0_RX_ER),
|
||||
|
||||
PINMUX_IPSR_MSEL(IP4_11_9, HRX0_A, SEL_HSCIF_0),
|
||||
PINMUX_IPSR_MSEL(IP4_11_9, RX1_A, SEL_SCIF1_0),
|
||||
PINMUX_IPSR_DATA(IP4_11_9, VI0_DATA0_VI0_B0),
|
||||
PINMUX_IPSR_GPSR(IP4_11_9, VI0_DATA0_VI0_B0),
|
||||
PINMUX_IPSR_MSEL(IP4_11_9, RMII0_CRS_DV_A, SEL_RMII_0),
|
||||
PINMUX_IPSR_DATA(IP4_11_9, ET0_CRS),
|
||||
PINMUX_IPSR_GPSR(IP4_11_9, ET0_CRS),
|
||||
|
||||
PINMUX_IPSR_MSEL(IP4_14_12, HTX0_A, SEL_HSCIF_0),
|
||||
PINMUX_IPSR_MSEL(IP4_14_12, TX1_A, SEL_SCIF1_0),
|
||||
PINMUX_IPSR_DATA(IP4_14_12, VI0_DATA1_VI0_B1),
|
||||
PINMUX_IPSR_GPSR(IP4_14_12, VI0_DATA1_VI0_B1),
|
||||
PINMUX_IPSR_MSEL(IP4_14_12, RMII0_MDC_A, SEL_RMII_0),
|
||||
PINMUX_IPSR_DATA(IP4_14_12, ET0_COL),
|
||||
PINMUX_IPSR_GPSR(IP4_14_12, ET0_COL),
|
||||
|
||||
PINMUX_IPSR_MSEL(IP4_17_15, CTS0_B, SEL_SCIF0_1),
|
||||
PINMUX_IPSR_DATA(IP4_17_15, VI0_DATA2_VI0_B2),
|
||||
PINMUX_IPSR_GPSR(IP4_17_15, VI0_DATA2_VI0_B2),
|
||||
PINMUX_IPSR_MSEL(IP4_17_15, RMII0_MDIO_A, SEL_RMII_0),
|
||||
PINMUX_IPSR_DATA(IP4_17_15, ET0_MDC),
|
||||
PINMUX_IPSR_GPSR(IP4_17_15, ET0_MDC),
|
||||
|
||||
PINMUX_IPSR_MSEL(IP4_19_18, RTS0_B, SEL_SCIF0_1),
|
||||
PINMUX_IPSR_DATA(IP4_19_18, VI0_DATA3_VI0_B3),
|
||||
PINMUX_IPSR_GPSR(IP4_19_18, VI0_DATA3_VI0_B3),
|
||||
PINMUX_IPSR_MSEL(IP4_19_18, ET0_MDIO_A, SEL_ET0_0),
|
||||
|
||||
PINMUX_IPSR_MSEL(IP4_21_20, SCK1_B, SEL_SCIF1_1),
|
||||
PINMUX_IPSR_DATA(IP4_21_20, VI0_DATA4_VI0_B4),
|
||||
PINMUX_IPSR_GPSR(IP4_21_20, VI0_DATA4_VI0_B4),
|
||||
PINMUX_IPSR_MSEL(IP4_21_20, ET0_LINK_A, SEL_ET0_CTL_0),
|
||||
|
||||
PINMUX_IPSR_MSEL(IP4_23_22, RX1_B, SEL_SCIF1_1),
|
||||
PINMUX_IPSR_DATA(IP4_23_22, VI0_DATA5_VI0_B5),
|
||||
PINMUX_IPSR_GPSR(IP4_23_22, VI0_DATA5_VI0_B5),
|
||||
PINMUX_IPSR_MSEL(IP4_23_22, ET0_MAGIC_A, SEL_ET0_CTL_0),
|
||||
|
||||
PINMUX_IPSR_MSEL(IP4_25_24, TX1_B, SEL_SCIF1_1),
|
||||
PINMUX_IPSR_DATA(IP4_25_24, VI0_DATA6_VI0_G0),
|
||||
PINMUX_IPSR_GPSR(IP4_25_24, VI0_DATA6_VI0_G0),
|
||||
PINMUX_IPSR_MSEL(IP4_25_24, ET0_PHY_INT_A, SEL_ET0_CTL_0),
|
||||
|
||||
PINMUX_IPSR_MSEL(IP4_27_26, CTS1_B, SEL_SCIF1_1),
|
||||
PINMUX_IPSR_DATA(IP4_27_26, VI0_DATA7_VI0_G1),
|
||||
PINMUX_IPSR_GPSR(IP4_27_26, VI0_DATA7_VI0_G1),
|
||||
|
||||
PINMUX_IPSR_MSEL(IP4_29_28, RTS1_B, SEL_SCIF1_1),
|
||||
PINMUX_IPSR_DATA(IP4_29_28, VI0_G2),
|
||||
PINMUX_IPSR_GPSR(IP4_29_28, VI0_G2),
|
||||
|
||||
PINMUX_IPSR_MSEL(IP4_31_30, SCK2_A, SEL_SCIF2_0),
|
||||
PINMUX_IPSR_DATA(IP4_31_30, VI0_G3),
|
||||
PINMUX_IPSR_GPSR(IP4_31_30, VI0_G3),
|
||||
|
||||
/* IPSR5 */
|
||||
PINMUX_IPSR_MSEL(IP5_2_0, SD2_CLK_A, SEL_SDHI2_0),
|
||||
PINMUX_IPSR_MSEL(IP5_2_0, RX2_A, SEL_SCIF2_0),
|
||||
PINMUX_IPSR_DATA(IP5_2_0, VI0_G4),
|
||||
PINMUX_IPSR_GPSR(IP5_2_0, VI0_G4),
|
||||
PINMUX_IPSR_MSEL(IP5_2_0, ET0_RX_CLK_B, SEL_ET0_1),
|
||||
|
||||
PINMUX_IPSR_MSEL(IP5_5_3, SD2_CMD_A, SEL_SDHI2_0),
|
||||
PINMUX_IPSR_MSEL(IP5_5_3, TX2_A, SEL_SCIF2_0),
|
||||
PINMUX_IPSR_DATA(IP5_5_3, VI0_G5),
|
||||
PINMUX_IPSR_GPSR(IP5_5_3, VI0_G5),
|
||||
PINMUX_IPSR_MSEL(IP5_5_3, ET0_ERXD2_B, SEL_ET0_1),
|
||||
|
||||
PINMUX_IPSR_MSEL(IP5_8_6, SD2_DAT0_A, SEL_SDHI2_0),
|
||||
PINMUX_IPSR_MSEL(IP5_8_6, RX3_A, SEL_SCIF3_0),
|
||||
PINMUX_IPSR_DATA(IP4_8_6, VI0_R0),
|
||||
PINMUX_IPSR_GPSR(IP4_8_6, VI0_R0),
|
||||
PINMUX_IPSR_MSEL(IP4_8_6, ET0_ERXD2_B, SEL_ET0_1),
|
||||
|
||||
PINMUX_IPSR_MSEL(IP5_11_9, SD2_DAT1_A, SEL_SDHI2_0),
|
||||
PINMUX_IPSR_MSEL(IP5_11_9, TX3_A, SEL_SCIF3_0),
|
||||
PINMUX_IPSR_DATA(IP5_11_9, VI0_R1),
|
||||
PINMUX_IPSR_GPSR(IP5_11_9, VI0_R1),
|
||||
PINMUX_IPSR_MSEL(IP5_11_9, ET0_MDIO_B, SEL_ET0_1),
|
||||
|
||||
PINMUX_IPSR_MSEL(IP5_14_12, SD2_DAT2_A, SEL_SDHI2_0),
|
||||
PINMUX_IPSR_MSEL(IP5_14_12, RX4_A, SEL_SCIF4_0),
|
||||
PINMUX_IPSR_DATA(IP5_14_12, VI0_R2),
|
||||
PINMUX_IPSR_GPSR(IP5_14_12, VI0_R2),
|
||||
PINMUX_IPSR_MSEL(IP5_14_12, ET0_LINK_B, SEL_ET0_CTL_1),
|
||||
|
||||
PINMUX_IPSR_MSEL(IP5_17_15, SD2_DAT3_A, SEL_SDHI2_0),
|
||||
PINMUX_IPSR_MSEL(IP5_17_15, TX4_A, SEL_SCIF4_0),
|
||||
PINMUX_IPSR_DATA(IP5_17_15, VI0_R3),
|
||||
PINMUX_IPSR_GPSR(IP5_17_15, VI0_R3),
|
||||
PINMUX_IPSR_MSEL(IP5_17_15, ET0_MAGIC_B, SEL_ET0_CTL_1),
|
||||
|
||||
PINMUX_IPSR_MSEL(IP5_20_18, SD2_CD_A, SEL_SDHI2_0),
|
||||
PINMUX_IPSR_MSEL(IP5_20_18, RX5_A, SEL_SCIF5_0),
|
||||
PINMUX_IPSR_DATA(IP5_20_18, VI0_R4),
|
||||
PINMUX_IPSR_GPSR(IP5_20_18, VI0_R4),
|
||||
PINMUX_IPSR_MSEL(IP5_20_18, ET0_PHY_INT_B, SEL_ET0_CTL_1),
|
||||
|
||||
PINMUX_IPSR_MSEL(IP5_22_21, SD2_WP_A, SEL_SDHI2_0),
|
||||
PINMUX_IPSR_MSEL(IP5_22_21, TX5_A, SEL_SCIF5_0),
|
||||
PINMUX_IPSR_DATA(IP5_22_21, VI0_R5),
|
||||
PINMUX_IPSR_GPSR(IP5_22_21, VI0_R5),
|
||||
|
||||
PINMUX_IPSR_DATA(IP5_24_23, REF125CK),
|
||||
PINMUX_IPSR_DATA(IP5_24_23, ADTRG),
|
||||
PINMUX_IPSR_GPSR(IP5_24_23, REF125CK),
|
||||
PINMUX_IPSR_GPSR(IP5_24_23, ADTRG),
|
||||
PINMUX_IPSR_MSEL(IP5_24_23, RX5_C, SEL_SCIF5_2),
|
||||
PINMUX_IPSR_DATA(IP5_26_25, REF50CK),
|
||||
PINMUX_IPSR_GPSR(IP5_26_25, REF50CK),
|
||||
PINMUX_IPSR_MSEL(IP5_26_25, CTS1_E, SEL_SCIF1_3),
|
||||
PINMUX_IPSR_MSEL(IP5_26_25, HCTS0_D, SEL_HSCIF_3),
|
||||
|
||||
/* IPSR6 */
|
||||
PINMUX_IPSR_DATA(IP6_2_0, DU0_DR0),
|
||||
PINMUX_IPSR_GPSR(IP6_2_0, DU0_DR0),
|
||||
PINMUX_IPSR_MSEL(IP6_2_0, SCIF_CLK_B, SEL_SCIF_CLK_1),
|
||||
PINMUX_IPSR_MSEL(IP6_2_0, HRX0_D, SEL_HSCIF_3),
|
||||
PINMUX_IPSR_MSEL(IP6_2_0, IETX_A, SEL_IEBUS_0),
|
||||
PINMUX_IPSR_MSEL(IP6_2_0, TCLKA_A, SEL_MTU2_CLK_0),
|
||||
PINMUX_IPSR_DATA(IP6_2_0, HIFD00),
|
||||
PINMUX_IPSR_GPSR(IP6_2_0, HIFD00),
|
||||
|
||||
PINMUX_IPSR_DATA(IP6_5_3, DU0_DR1),
|
||||
PINMUX_IPSR_GPSR(IP6_5_3, DU0_DR1),
|
||||
PINMUX_IPSR_MSEL(IP6_5_3, SCK0_B, SEL_SCIF0_1),
|
||||
PINMUX_IPSR_MSEL(IP6_5_3, HTX0_D, SEL_HSCIF_3),
|
||||
PINMUX_IPSR_MSEL(IP6_5_3, IERX_A, SEL_IEBUS_0),
|
||||
PINMUX_IPSR_MSEL(IP6_5_3, TCLKB_A, SEL_MTU2_CLK_0),
|
||||
PINMUX_IPSR_DATA(IP6_5_3, HIFD01),
|
||||
PINMUX_IPSR_GPSR(IP6_5_3, HIFD01),
|
||||
|
||||
PINMUX_IPSR_DATA(IP6_7_6, DU0_DR2),
|
||||
PINMUX_IPSR_GPSR(IP6_7_6, DU0_DR2),
|
||||
PINMUX_IPSR_MSEL(IP6_7_6, RX0_B, SEL_SCIF0_1),
|
||||
PINMUX_IPSR_MSEL(IP6_7_6, TCLKC_A, SEL_MTU2_CLK_0),
|
||||
PINMUX_IPSR_DATA(IP6_7_6, HIFD02),
|
||||
PINMUX_IPSR_GPSR(IP6_7_6, HIFD02),
|
||||
|
||||
PINMUX_IPSR_DATA(IP6_9_8, DU0_DR3),
|
||||
PINMUX_IPSR_GPSR(IP6_9_8, DU0_DR3),
|
||||
PINMUX_IPSR_MSEL(IP6_9_8, TX0_B, SEL_SCIF0_1),
|
||||
PINMUX_IPSR_MSEL(IP6_9_8, TCLKD_A, SEL_MTU2_CLK_0),
|
||||
PINMUX_IPSR_DATA(IP6_9_8, HIFD03),
|
||||
PINMUX_IPSR_GPSR(IP6_9_8, HIFD03),
|
||||
|
||||
PINMUX_IPSR_DATA(IP6_11_10, DU0_DR4),
|
||||
PINMUX_IPSR_GPSR(IP6_11_10, DU0_DR4),
|
||||
PINMUX_IPSR_MSEL(IP6_11_10, CTS0_C, SEL_SCIF0_2),
|
||||
PINMUX_IPSR_MSEL(IP6_11_10, TIOC0A_A, SEL_MTU2_CH0_0),
|
||||
PINMUX_IPSR_DATA(IP6_11_10, HIFD04),
|
||||
PINMUX_IPSR_GPSR(IP6_11_10, HIFD04),
|
||||
|
||||
PINMUX_IPSR_DATA(IP6_13_12, DU0_DR5),
|
||||
PINMUX_IPSR_GPSR(IP6_13_12, DU0_DR5),
|
||||
PINMUX_IPSR_MSEL(IP6_13_12, RTS0_C, SEL_SCIF0_1),
|
||||
PINMUX_IPSR_MSEL(IP6_13_12, TIOC0B_A, SEL_MTU2_CH0_0),
|
||||
PINMUX_IPSR_DATA(IP6_13_12, HIFD05),
|
||||
PINMUX_IPSR_GPSR(IP6_13_12, HIFD05),
|
||||
|
||||
PINMUX_IPSR_DATA(IP6_15_14, DU0_DR6),
|
||||
PINMUX_IPSR_GPSR(IP6_15_14, DU0_DR6),
|
||||
PINMUX_IPSR_MSEL(IP6_15_14, SCK1_C, SEL_SCIF1_2),
|
||||
PINMUX_IPSR_MSEL(IP6_15_14, TIOC0C_A, SEL_MTU2_CH0_0),
|
||||
PINMUX_IPSR_DATA(IP6_15_14, HIFD06),
|
||||
PINMUX_IPSR_GPSR(IP6_15_14, HIFD06),
|
||||
|
||||
PINMUX_IPSR_DATA(IP6_17_16, DU0_DR7),
|
||||
PINMUX_IPSR_GPSR(IP6_17_16, DU0_DR7),
|
||||
PINMUX_IPSR_MSEL(IP6_17_16, RX1_C, SEL_SCIF1_2),
|
||||
PINMUX_IPSR_MSEL(IP6_17_16, TIOC0D_A, SEL_MTU2_CH0_0),
|
||||
PINMUX_IPSR_DATA(IP6_17_16, HIFD07),
|
||||
PINMUX_IPSR_GPSR(IP6_17_16, HIFD07),
|
||||
|
||||
PINMUX_IPSR_DATA(IP6_20_18, DU0_DG0),
|
||||
PINMUX_IPSR_GPSR(IP6_20_18, DU0_DG0),
|
||||
PINMUX_IPSR_MSEL(IP6_20_18, TX1_C, SEL_SCIF1_2),
|
||||
PINMUX_IPSR_MSEL(IP6_20_18, HSCK0_D, SEL_HSCIF_3),
|
||||
PINMUX_IPSR_MSEL(IP6_20_18, IECLK_A, SEL_IEBUS_0),
|
||||
PINMUX_IPSR_MSEL(IP6_20_18, TIOC1A_A, SEL_MTU2_CH1_0),
|
||||
PINMUX_IPSR_DATA(IP6_20_18, HIFD08),
|
||||
PINMUX_IPSR_GPSR(IP6_20_18, HIFD08),
|
||||
|
||||
PINMUX_IPSR_DATA(IP6_23_21, DU0_DG1),
|
||||
PINMUX_IPSR_GPSR(IP6_23_21, DU0_DG1),
|
||||
PINMUX_IPSR_MSEL(IP6_23_21, CTS1_C, SEL_SCIF1_2),
|
||||
PINMUX_IPSR_MSEL(IP6_23_21, HRTS0_D, SEL_HSCIF_3),
|
||||
PINMUX_IPSR_MSEL(IP6_23_21, TIOC1B_A, SEL_MTU2_CH1_0),
|
||||
PINMUX_IPSR_DATA(IP6_23_21, HIFD09),
|
||||
PINMUX_IPSR_GPSR(IP6_23_21, HIFD09),
|
||||
|
||||
/* IPSR7 */
|
||||
PINMUX_IPSR_DATA(IP7_2_0, DU0_DG2),
|
||||
PINMUX_IPSR_GPSR(IP7_2_0, DU0_DG2),
|
||||
PINMUX_IPSR_MSEL(IP7_2_0, RTS1_C, SEL_SCIF1_2),
|
||||
PINMUX_IPSR_MSEL(IP7_2_0, RMII0_MDC_B, SEL_RMII_1),
|
||||
PINMUX_IPSR_MSEL(IP7_2_0, TIOC2A_A, SEL_MTU2_CH2_0),
|
||||
PINMUX_IPSR_DATA(IP7_2_0, HIFD10),
|
||||
PINMUX_IPSR_GPSR(IP7_2_0, HIFD10),
|
||||
|
||||
PINMUX_IPSR_DATA(IP7_5_3, DU0_DG3),
|
||||
PINMUX_IPSR_GPSR(IP7_5_3, DU0_DG3),
|
||||
PINMUX_IPSR_MSEL(IP7_5_3, SCK2_C, SEL_SCIF2_2),
|
||||
PINMUX_IPSR_MSEL(IP7_5_3, RMII0_MDIO_B, SEL_RMII_1),
|
||||
PINMUX_IPSR_MSEL(IP7_5_3, TIOC2B_A, SEL_MTU2_CH2_0),
|
||||
PINMUX_IPSR_DATA(IP7_5_3, HIFD11),
|
||||
PINMUX_IPSR_GPSR(IP7_5_3, HIFD11),
|
||||
|
||||
PINMUX_IPSR_DATA(IP7_8_6, DU0_DG4),
|
||||
PINMUX_IPSR_GPSR(IP7_8_6, DU0_DG4),
|
||||
PINMUX_IPSR_MSEL(IP7_8_6, RX2_C, SEL_SCIF2_2),
|
||||
PINMUX_IPSR_MSEL(IP7_8_6, RMII0_CRS_DV_B, SEL_RMII_1),
|
||||
PINMUX_IPSR_MSEL(IP7_8_6, TIOC3A_A, SEL_MTU2_CH3_0),
|
||||
PINMUX_IPSR_DATA(IP7_8_6, HIFD12),
|
||||
PINMUX_IPSR_GPSR(IP7_8_6, HIFD12),
|
||||
|
||||
PINMUX_IPSR_DATA(IP7_11_9, DU0_DG5),
|
||||
PINMUX_IPSR_GPSR(IP7_11_9, DU0_DG5),
|
||||
PINMUX_IPSR_MSEL(IP7_11_9, TX2_C, SEL_SCIF2_2),
|
||||
PINMUX_IPSR_MSEL(IP7_11_9, RMII0_RX_ER_B, SEL_RMII_1),
|
||||
PINMUX_IPSR_MSEL(IP7_11_9, TIOC3B_A, SEL_MTU2_CH3_0),
|
||||
PINMUX_IPSR_DATA(IP7_11_9, HIFD13),
|
||||
PINMUX_IPSR_GPSR(IP7_11_9, HIFD13),
|
||||
|
||||
PINMUX_IPSR_DATA(IP7_14_12, DU0_DG6),
|
||||
PINMUX_IPSR_GPSR(IP7_14_12, DU0_DG6),
|
||||
PINMUX_IPSR_MSEL(IP7_14_12, RX3_C, SEL_SCIF3_2),
|
||||
PINMUX_IPSR_MSEL(IP7_14_12, RMII0_RXD0_B, SEL_RMII_1),
|
||||
PINMUX_IPSR_MSEL(IP7_14_12, TIOC3C_A, SEL_MTU2_CH3_0),
|
||||
PINMUX_IPSR_DATA(IP7_14_12, HIFD14),
|
||||
PINMUX_IPSR_GPSR(IP7_14_12, HIFD14),
|
||||
|
||||
PINMUX_IPSR_DATA(IP7_17_15, DU0_DG7),
|
||||
PINMUX_IPSR_GPSR(IP7_17_15, DU0_DG7),
|
||||
PINMUX_IPSR_MSEL(IP7_17_15, TX3_C, SEL_SCIF3_2),
|
||||
PINMUX_IPSR_MSEL(IP7_17_15, RMII0_RXD1_B, SEL_RMII_1),
|
||||
PINMUX_IPSR_MSEL(IP7_17_15, TIOC3D_A, SEL_MTU2_CH3_0),
|
||||
PINMUX_IPSR_DATA(IP7_17_15, HIFD15),
|
||||
PINMUX_IPSR_GPSR(IP7_17_15, HIFD15),
|
||||
|
||||
PINMUX_IPSR_DATA(IP7_20_18, DU0_DB0),
|
||||
PINMUX_IPSR_GPSR(IP7_20_18, DU0_DB0),
|
||||
PINMUX_IPSR_MSEL(IP7_20_18, RX4_C, SEL_SCIF4_2),
|
||||
PINMUX_IPSR_MSEL(IP7_20_18, RMII0_TXD_EN_B, SEL_RMII_1),
|
||||
PINMUX_IPSR_MSEL(IP7_20_18, TIOC4A_A, SEL_MTU2_CH4_0),
|
||||
PINMUX_IPSR_DATA(IP7_20_18, HIFCS),
|
||||
PINMUX_IPSR_GPSR(IP7_20_18, HIFCS),
|
||||
|
||||
PINMUX_IPSR_DATA(IP7_23_21, DU0_DB1),
|
||||
PINMUX_IPSR_GPSR(IP7_23_21, DU0_DB1),
|
||||
PINMUX_IPSR_MSEL(IP7_23_21, TX4_C, SEL_SCIF4_2),
|
||||
PINMUX_IPSR_MSEL(IP7_23_21, RMII0_TXD0_B, SEL_RMII_1),
|
||||
PINMUX_IPSR_MSEL(IP7_23_21, TIOC4B_A, SEL_MTU2_CH4_0),
|
||||
PINMUX_IPSR_DATA(IP7_23_21, HIFWR),
|
||||
PINMUX_IPSR_GPSR(IP7_23_21, HIFWR),
|
||||
|
||||
PINMUX_IPSR_DATA(IP7_26_24, DU0_DB2),
|
||||
PINMUX_IPSR_GPSR(IP7_26_24, DU0_DB2),
|
||||
PINMUX_IPSR_MSEL(IP7_26_24, RX5_B, SEL_SCIF5_1),
|
||||
PINMUX_IPSR_MSEL(IP7_26_24, RMII0_TXD1_B, SEL_RMII_1),
|
||||
PINMUX_IPSR_MSEL(IP7_26_24, TIOC4C_A, SEL_MTU2_CH4_0),
|
||||
|
||||
PINMUX_IPSR_DATA(IP7_28_27, DU0_DB3),
|
||||
PINMUX_IPSR_GPSR(IP7_28_27, DU0_DB3),
|
||||
PINMUX_IPSR_MSEL(IP7_28_27, TX5_B, SEL_SCIF5_1),
|
||||
PINMUX_IPSR_MSEL(IP7_28_27, TIOC4D_A, SEL_MTU2_CH4_0),
|
||||
PINMUX_IPSR_DATA(IP7_28_27, HIFRD),
|
||||
PINMUX_IPSR_GPSR(IP7_28_27, HIFRD),
|
||||
|
||||
PINMUX_IPSR_DATA(IP7_30_29, DU0_DB4),
|
||||
PINMUX_IPSR_DATA(IP7_30_29, HIFINT),
|
||||
PINMUX_IPSR_GPSR(IP7_30_29, DU0_DB4),
|
||||
PINMUX_IPSR_GPSR(IP7_30_29, HIFINT),
|
||||
|
||||
/* IPSR8 */
|
||||
PINMUX_IPSR_DATA(IP8_1_0, DU0_DB5),
|
||||
PINMUX_IPSR_DATA(IP8_1_0, HIFDREQ),
|
||||
PINMUX_IPSR_GPSR(IP8_1_0, DU0_DB5),
|
||||
PINMUX_IPSR_GPSR(IP8_1_0, HIFDREQ),
|
||||
|
||||
PINMUX_IPSR_DATA(IP8_3_2, DU0_DB6),
|
||||
PINMUX_IPSR_DATA(IP8_3_2, HIFRDY),
|
||||
PINMUX_IPSR_GPSR(IP8_3_2, DU0_DB6),
|
||||
PINMUX_IPSR_GPSR(IP8_3_2, HIFRDY),
|
||||
|
||||
PINMUX_IPSR_DATA(IP8_5_4, DU0_DB7),
|
||||
PINMUX_IPSR_GPSR(IP8_5_4, DU0_DB7),
|
||||
PINMUX_IPSR_MSEL(IP8_5_4, SSI_SCK0_B, SEL_SSI0_1),
|
||||
PINMUX_IPSR_MSEL(IP8_5_4, HIFEBL_B, SEL_HIF_1),
|
||||
|
||||
PINMUX_IPSR_DATA(IP8_7_6, DU0_DOTCLKIN),
|
||||
PINMUX_IPSR_GPSR(IP8_7_6, DU0_DOTCLKIN),
|
||||
PINMUX_IPSR_MSEL(IP8_7_6, HSPI_CS0_C, SEL_HSPI_2),
|
||||
PINMUX_IPSR_MSEL(IP8_7_6, SSI_WS0_B, SEL_SSI0_1),
|
||||
|
||||
PINMUX_IPSR_DATA(IP8_9_8, DU0_DOTCLKOUT),
|
||||
PINMUX_IPSR_GPSR(IP8_9_8, DU0_DOTCLKOUT),
|
||||
PINMUX_IPSR_MSEL(IP8_9_8, HSPI_CLK0_C, SEL_HSPI_2),
|
||||
PINMUX_IPSR_MSEL(IP8_9_8, SSI_SDATA0_B, SEL_SSI0_1),
|
||||
|
||||
PINMUX_IPSR_DATA(IP8_11_10, DU0_EXHSYNC_DU0_HSYNC),
|
||||
PINMUX_IPSR_GPSR(IP8_11_10, DU0_EXHSYNC_DU0_HSYNC),
|
||||
PINMUX_IPSR_MSEL(IP8_11_10, HSPI_TX0_C, SEL_HSPI_2),
|
||||
PINMUX_IPSR_MSEL(IP8_11_10, SSI_SCK1_B, SEL_SSI1_1),
|
||||
|
||||
PINMUX_IPSR_DATA(IP8_13_12, DU0_EXVSYNC_DU0_VSYNC),
|
||||
PINMUX_IPSR_GPSR(IP8_13_12, DU0_EXVSYNC_DU0_VSYNC),
|
||||
PINMUX_IPSR_MSEL(IP8_13_12, HSPI_RX0_C, SEL_HSPI_2),
|
||||
PINMUX_IPSR_MSEL(IP8_13_12, SSI_WS1_B, SEL_SSI1_1),
|
||||
|
||||
PINMUX_IPSR_DATA(IP8_15_14, DU0_EXODDF_DU0_ODDF),
|
||||
PINMUX_IPSR_GPSR(IP8_15_14, DU0_EXODDF_DU0_ODDF),
|
||||
PINMUX_IPSR_MSEL(IP8_15_14, CAN0_RX_B, SEL_RCAN0_1),
|
||||
PINMUX_IPSR_MSEL(IP8_15_14, HSCK0_B, SEL_HSCIF_1),
|
||||
PINMUX_IPSR_MSEL(IP8_15_14, SSI_SDATA1_B, SEL_SSI1_1),
|
||||
|
||||
PINMUX_IPSR_DATA(IP8_17_16, DU0_DISP),
|
||||
PINMUX_IPSR_GPSR(IP8_17_16, DU0_DISP),
|
||||
PINMUX_IPSR_MSEL(IP8_17_16, CAN0_TX_B, SEL_RCAN0_1),
|
||||
PINMUX_IPSR_MSEL(IP8_17_16, HRX0_B, SEL_HSCIF_1),
|
||||
PINMUX_IPSR_MSEL(IP8_17_16, AUDIO_CLKA_B, SEL_AUDIO_CLKA_1),
|
||||
|
||||
PINMUX_IPSR_DATA(IP8_19_18, DU0_CDE),
|
||||
PINMUX_IPSR_GPSR(IP8_19_18, DU0_CDE),
|
||||
PINMUX_IPSR_MSEL(IP8_19_18, HTX0_B, SEL_HSCIF_1),
|
||||
PINMUX_IPSR_MSEL(IP8_19_18, AUDIO_CLKB_B, SEL_AUDIO_CLKB_1),
|
||||
PINMUX_IPSR_MSEL(IP8_19_18, LCD_VCPWC_B, SEL_LCDC_1),
|
||||
|
|
@ -1139,12 +1139,12 @@ static const u16 pinmux_data[] = {
|
|||
PINMUX_IPSR_MSEL(IP8_22_20, IRQ0_A, SEL_INTC_0),
|
||||
PINMUX_IPSR_MSEL(IP8_22_20, HSPI_TX_B, SEL_HSPI_1),
|
||||
PINMUX_IPSR_MSEL(IP8_22_20, RX3_E, SEL_SCIF3_4),
|
||||
PINMUX_IPSR_DATA(IP8_22_20, ET0_ERXD0),
|
||||
PINMUX_IPSR_GPSR(IP8_22_20, ET0_ERXD0),
|
||||
|
||||
PINMUX_IPSR_MSEL(IP8_25_23, IRQ1_A, SEL_INTC_0),
|
||||
PINMUX_IPSR_MSEL(IP8_25_23, HSPI_RX_B, SEL_HSPI_1),
|
||||
PINMUX_IPSR_MSEL(IP8_25_23, TX3_E, SEL_SCIF3_4),
|
||||
PINMUX_IPSR_DATA(IP8_25_23, ET0_ERXD1),
|
||||
PINMUX_IPSR_GPSR(IP8_25_23, ET0_ERXD1),
|
||||
|
||||
PINMUX_IPSR_MSEL(IP8_27_26, IRQ2_A, SEL_INTC_0),
|
||||
PINMUX_IPSR_MSEL(IP8_27_26, CTS0_A, SEL_SCIF0_0),
|
||||
|
|
@ -1220,26 +1220,26 @@ static const u16 pinmux_data[] = {
|
|||
PINMUX_IPSR_MSEL(IP9_29_28, LCD_DATA14_B, SEL_LCDC_1),
|
||||
|
||||
/* IPSE10 */
|
||||
PINMUX_IPSR_DATA(IP10_2_0, SSI_SCK23),
|
||||
PINMUX_IPSR_GPSR(IP10_2_0, SSI_SCK23),
|
||||
PINMUX_IPSR_MSEL(IP10_2_0, VI1_4_B, SEL_VIN1_1),
|
||||
PINMUX_IPSR_MSEL(IP10_2_0, RX1_D, SEL_SCIF1_3),
|
||||
PINMUX_IPSR_MSEL(IP10_2_0, FCLE_B, SEL_FLCTL_1),
|
||||
PINMUX_IPSR_MSEL(IP10_2_0, LCD_DATA15_B, SEL_LCDC_1),
|
||||
|
||||
PINMUX_IPSR_DATA(IP10_5_3, SSI_WS23),
|
||||
PINMUX_IPSR_GPSR(IP10_5_3, SSI_WS23),
|
||||
PINMUX_IPSR_MSEL(IP10_5_3, VI1_5_B, SEL_VIN1_1),
|
||||
PINMUX_IPSR_MSEL(IP10_5_3, TX1_D, SEL_SCIF1_3),
|
||||
PINMUX_IPSR_MSEL(IP10_5_3, HSCK0_C, SEL_HSCIF_2),
|
||||
PINMUX_IPSR_MSEL(IP10_5_3, FALE_B, SEL_FLCTL_1),
|
||||
PINMUX_IPSR_MSEL(IP10_5_3, LCD_DON_B, SEL_LCDC_1),
|
||||
|
||||
PINMUX_IPSR_DATA(IP10_8_6, SSI_SDATA2),
|
||||
PINMUX_IPSR_GPSR(IP10_8_6, SSI_SDATA2),
|
||||
PINMUX_IPSR_MSEL(IP10_8_6, VI1_6_B, SEL_VIN1_1),
|
||||
PINMUX_IPSR_MSEL(IP10_8_6, HRX0_C, SEL_HSCIF_2),
|
||||
PINMUX_IPSR_MSEL(IP10_8_6, FRE_B, SEL_FLCTL_1),
|
||||
PINMUX_IPSR_MSEL(IP10_8_6, LCD_CL1_B, SEL_LCDC_1),
|
||||
|
||||
PINMUX_IPSR_DATA(IP10_11_9, SSI_SDATA3),
|
||||
PINMUX_IPSR_GPSR(IP10_11_9, SSI_SDATA3),
|
||||
PINMUX_IPSR_MSEL(IP10_11_9, VI1_7_B, SEL_VIN1_1),
|
||||
PINMUX_IPSR_MSEL(IP10_11_9, HTX0_C, SEL_HSCIF_2),
|
||||
PINMUX_IPSR_MSEL(IP10_11_9, FWE_B, SEL_FLCTL_1),
|
||||
|
|
@ -1254,13 +1254,13 @@ static const u16 pinmux_data[] = {
|
|||
PINMUX_IPSR_MSEL(IP10_15, AUDIO_CLKB_A, SEL_AUDIO_CLKB_0),
|
||||
PINMUX_IPSR_MSEL(IP10_15, LCD_CLK_B, SEL_LCDC_1),
|
||||
|
||||
PINMUX_IPSR_DATA(IP10_18_16, AUDIO_CLKC),
|
||||
PINMUX_IPSR_GPSR(IP10_18_16, AUDIO_CLKC),
|
||||
PINMUX_IPSR_MSEL(IP10_18_16, SCK1_E, SEL_SCIF1_4),
|
||||
PINMUX_IPSR_MSEL(IP10_18_16, HCTS0_C, SEL_HSCIF_2),
|
||||
PINMUX_IPSR_MSEL(IP10_18_16, FRB_B, SEL_FLCTL_1),
|
||||
PINMUX_IPSR_MSEL(IP10_18_16, LCD_VEPWC_B, SEL_LCDC_1),
|
||||
|
||||
PINMUX_IPSR_DATA(IP10_21_19, AUDIO_CLKOUT),
|
||||
PINMUX_IPSR_GPSR(IP10_21_19, AUDIO_CLKOUT),
|
||||
PINMUX_IPSR_MSEL(IP10_21_19, TX1_E, SEL_SCIF1_4),
|
||||
PINMUX_IPSR_MSEL(IP10_21_19, HRTS0_C, SEL_HSCIF_2),
|
||||
PINMUX_IPSR_MSEL(IP10_21_19, FSE_B, SEL_FLCTL_1),
|
||||
|
|
@ -1271,85 +1271,85 @@ static const u16 pinmux_data[] = {
|
|||
|
||||
PINMUX_IPSR_MSEL(IP10_24_23, CAN0_TX_A, SEL_RCAN0_0),
|
||||
PINMUX_IPSR_MSEL(IP10_24_23, TX4_D, SEL_SCIF4_3),
|
||||
PINMUX_IPSR_DATA(IP10_24_23, MLB_CLK),
|
||||
PINMUX_IPSR_GPSR(IP10_24_23, MLB_CLK),
|
||||
|
||||
PINMUX_IPSR_MSEL(IP10_25, CAN1_RX_A, SEL_RCAN1_0),
|
||||
PINMUX_IPSR_MSEL(IP10_25, IRQ1_B, SEL_INTC_1),
|
||||
|
||||
PINMUX_IPSR_MSEL(IP10_27_26, CAN0_RX_A, SEL_RCAN0_0),
|
||||
PINMUX_IPSR_MSEL(IP10_27_26, IRQ0_B, SEL_INTC_1),
|
||||
PINMUX_IPSR_DATA(IP10_27_26, MLB_SIG),
|
||||
PINMUX_IPSR_GPSR(IP10_27_26, MLB_SIG),
|
||||
|
||||
PINMUX_IPSR_MSEL(IP10_29_28, CAN1_TX_A, SEL_RCAN1_0),
|
||||
PINMUX_IPSR_MSEL(IP10_29_28, TX5_C, SEL_SCIF1_2),
|
||||
PINMUX_IPSR_DATA(IP10_29_28, MLB_DAT),
|
||||
PINMUX_IPSR_GPSR(IP10_29_28, MLB_DAT),
|
||||
|
||||
/* IPSR11 */
|
||||
PINMUX_IPSR_DATA(IP11_0, SCL1),
|
||||
PINMUX_IPSR_GPSR(IP11_0, SCL1),
|
||||
PINMUX_IPSR_MSEL(IP11_0, SCIF_CLK_C, SEL_SCIF_CLK_2),
|
||||
|
||||
PINMUX_IPSR_DATA(IP11_1, SDA1),
|
||||
PINMUX_IPSR_GPSR(IP11_1, SDA1),
|
||||
PINMUX_IPSR_MSEL(IP11_0, RX1_E, SEL_SCIF1_4),
|
||||
|
||||
PINMUX_IPSR_DATA(IP11_2, SDA0),
|
||||
PINMUX_IPSR_GPSR(IP11_2, SDA0),
|
||||
PINMUX_IPSR_MSEL(IP11_2, HIFEBL_A, SEL_HIF_0),
|
||||
|
||||
PINMUX_IPSR_DATA(IP11_3, SDSELF),
|
||||
PINMUX_IPSR_GPSR(IP11_3, SDSELF),
|
||||
PINMUX_IPSR_MSEL(IP11_3, RTS1_E, SEL_SCIF1_3),
|
||||
|
||||
PINMUX_IPSR_MSEL(IP11_6_4, SCIF_CLK_A, SEL_SCIF_CLK_0),
|
||||
PINMUX_IPSR_MSEL(IP11_6_4, HSPI_CLK_A, SEL_HSPI_0),
|
||||
PINMUX_IPSR_DATA(IP11_6_4, VI0_CLK),
|
||||
PINMUX_IPSR_GPSR(IP11_6_4, VI0_CLK),
|
||||
PINMUX_IPSR_MSEL(IP11_6_4, RMII0_TXD0_A, SEL_RMII_0),
|
||||
PINMUX_IPSR_DATA(IP11_6_4, ET0_ERXD4),
|
||||
PINMUX_IPSR_GPSR(IP11_6_4, ET0_ERXD4),
|
||||
|
||||
PINMUX_IPSR_MSEL(IP11_9_7, SCK0_A, SEL_SCIF0_0),
|
||||
PINMUX_IPSR_MSEL(IP11_9_7, HSPI_CS_A, SEL_HSPI_0),
|
||||
PINMUX_IPSR_DATA(IP11_9_7, VI0_CLKENB),
|
||||
PINMUX_IPSR_GPSR(IP11_9_7, VI0_CLKENB),
|
||||
PINMUX_IPSR_MSEL(IP11_9_7, RMII0_TXD1_A, SEL_RMII_0),
|
||||
PINMUX_IPSR_DATA(IP11_9_7, ET0_ERXD5),
|
||||
PINMUX_IPSR_GPSR(IP11_9_7, ET0_ERXD5),
|
||||
|
||||
PINMUX_IPSR_MSEL(IP11_11_10, RX0_A, SEL_SCIF0_0),
|
||||
PINMUX_IPSR_MSEL(IP11_11_10, HSPI_RX_A, SEL_HSPI_0),
|
||||
PINMUX_IPSR_MSEL(IP11_11_10, RMII0_RXD0_A, SEL_RMII_0),
|
||||
PINMUX_IPSR_DATA(IP11_11_10, ET0_ERXD6),
|
||||
PINMUX_IPSR_GPSR(IP11_11_10, ET0_ERXD6),
|
||||
|
||||
PINMUX_IPSR_MSEL(IP11_12, TX0_A, SEL_SCIF0_0),
|
||||
PINMUX_IPSR_MSEL(IP11_12, HSPI_TX_A, SEL_HSPI_0),
|
||||
|
||||
PINMUX_IPSR_DATA(IP11_15_13, PENC1),
|
||||
PINMUX_IPSR_GPSR(IP11_15_13, PENC1),
|
||||
PINMUX_IPSR_MSEL(IP11_15_13, TX3_D, SEL_SCIF3_3),
|
||||
PINMUX_IPSR_MSEL(IP11_15_13, CAN1_TX_B, SEL_RCAN1_1),
|
||||
PINMUX_IPSR_MSEL(IP11_15_13, TX5_D, SEL_SCIF5_3),
|
||||
PINMUX_IPSR_MSEL(IP11_15_13, IETX_B, SEL_IEBUS_1),
|
||||
|
||||
PINMUX_IPSR_DATA(IP11_18_16, USB_OVC1),
|
||||
PINMUX_IPSR_GPSR(IP11_18_16, USB_OVC1),
|
||||
PINMUX_IPSR_MSEL(IP11_18_16, RX3_D, SEL_SCIF3_3),
|
||||
PINMUX_IPSR_MSEL(IP11_18_16, CAN1_RX_B, SEL_RCAN1_1),
|
||||
PINMUX_IPSR_MSEL(IP11_18_16, RX5_D, SEL_SCIF5_3),
|
||||
PINMUX_IPSR_MSEL(IP11_18_16, IERX_B, SEL_IEBUS_1),
|
||||
|
||||
PINMUX_IPSR_DATA(IP11_20_19, DREQ0),
|
||||
PINMUX_IPSR_GPSR(IP11_20_19, DREQ0),
|
||||
PINMUX_IPSR_MSEL(IP11_20_19, SD1_CLK_A, SEL_SDHI1_0),
|
||||
PINMUX_IPSR_DATA(IP11_20_19, ET0_TX_EN),
|
||||
PINMUX_IPSR_GPSR(IP11_20_19, ET0_TX_EN),
|
||||
|
||||
PINMUX_IPSR_DATA(IP11_22_21, DACK0),
|
||||
PINMUX_IPSR_GPSR(IP11_22_21, DACK0),
|
||||
PINMUX_IPSR_MSEL(IP11_22_21, SD1_DAT3_A, SEL_SDHI1_0),
|
||||
PINMUX_IPSR_DATA(IP11_22_21, ET0_TX_ER),
|
||||
PINMUX_IPSR_GPSR(IP11_22_21, ET0_TX_ER),
|
||||
|
||||
PINMUX_IPSR_DATA(IP11_25_23, DREQ1),
|
||||
PINMUX_IPSR_GPSR(IP11_25_23, DREQ1),
|
||||
PINMUX_IPSR_MSEL(IP11_25_23, HSPI_CLK_B, SEL_HSPI_1),
|
||||
PINMUX_IPSR_MSEL(IP11_25_23, RX4_B, SEL_SCIF4_1),
|
||||
PINMUX_IPSR_MSEL(IP11_25_23, ET0_PHY_INT_C, SEL_ET0_CTL_0),
|
||||
PINMUX_IPSR_MSEL(IP11_25_23, ET0_TX_CLK_A, SEL_ET0_0),
|
||||
|
||||
PINMUX_IPSR_DATA(IP11_27_26, DACK1),
|
||||
PINMUX_IPSR_GPSR(IP11_27_26, DACK1),
|
||||
PINMUX_IPSR_MSEL(IP11_27_26, HSPI_CS_B, SEL_HSPI_1),
|
||||
PINMUX_IPSR_MSEL(IP11_27_26, TX4_B, SEL_SCIF3_1),
|
||||
PINMUX_IPSR_MSEL(IP11_27_26, ET0_RX_CLK_A, SEL_ET0_0),
|
||||
|
||||
PINMUX_IPSR_DATA(IP11_28, PRESETOUT),
|
||||
PINMUX_IPSR_DATA(IP11_28, ST_CLKOUT),
|
||||
PINMUX_IPSR_GPSR(IP11_28, PRESETOUT),
|
||||
PINMUX_IPSR_GPSR(IP11_28, ST_CLKOUT),
|
||||
};
|
||||
|
||||
static const struct sh_pfc_pin pinmux_pins[] = {
|
||||
|
|
|
|||
|
|
@ -100,10 +100,31 @@ struct pinmux_cfg_reg {
|
|||
const u8 *var_field_width;
|
||||
};
|
||||
|
||||
/*
|
||||
* Describe a config register consisting of several fields of the same width
|
||||
* - name: Register name (unused, for documentation purposes only)
|
||||
* - r: Physical register address
|
||||
* - r_width: Width of the register (in bits)
|
||||
* - f_width: Width of the fixed-width register fields (in bits)
|
||||
* This macro must be followed by initialization data: For each register field
|
||||
* (from left to right, i.e. MSB to LSB), 2^f_width enum IDs must be specified,
|
||||
* one for each possible combination of the register field bit values.
|
||||
*/
|
||||
#define PINMUX_CFG_REG(name, r, r_width, f_width) \
|
||||
.reg = r, .reg_width = r_width, .field_width = f_width, \
|
||||
.enum_ids = (const u16 [(r_width / f_width) * (1 << f_width)])
|
||||
|
||||
/*
|
||||
* Describe a config register consisting of several fields of different widths
|
||||
* - name: Register name (unused, for documentation purposes only)
|
||||
* - r: Physical register address
|
||||
* - r_width: Width of the register (in bits)
|
||||
* - var_fw0, var_fwn...: List of widths of the register fields (in bits),
|
||||
* From left to right (i.e. MSB to LSB)
|
||||
* This macro must be followed by initialization data: For each register field
|
||||
* (from left to right, i.e. MSB to LSB), 2^var_fwi enum IDs must be specified,
|
||||
* one for each possible combination of the register field bit values.
|
||||
*/
|
||||
#define PINMUX_CFG_REG_VAR(name, r, r_width, var_fw0, var_fwn...) \
|
||||
.reg = r, .reg_width = r_width, \
|
||||
.var_field_width = (const u8 [r_width]) \
|
||||
|
|
@ -116,6 +137,14 @@ struct pinmux_data_reg {
|
|||
const u16 *enum_ids;
|
||||
};
|
||||
|
||||
/*
|
||||
* Describe a data register
|
||||
* - name: Register name (unused, for documentation purposes only)
|
||||
* - r: Physical register address
|
||||
* - r_width: Width of the register (in bits)
|
||||
* This macro must be followed by initialization data: For each register bit
|
||||
* (from left to right, i.e. MSB to LSB), one enum ID must be specified.
|
||||
*/
|
||||
#define PINMUX_DATA_REG(name, r, r_width) \
|
||||
.reg = r, .reg_width = r_width, \
|
||||
.enum_ids = (const u16 [r_width]) \
|
||||
|
|
@ -124,6 +153,10 @@ struct pinmux_irq {
|
|||
const short *gpios;
|
||||
};
|
||||
|
||||
/*
|
||||
* Describe the mapping from GPIOs to a single IRQ
|
||||
* - ids...: List of GPIOs that are mapped to the same IRQ
|
||||
*/
|
||||
#define PINMUX_IRQ(ids...) \
|
||||
{ .gpios = (const short []) { ids, -1 } }
|
||||
|
||||
|
|
@ -185,18 +218,65 @@ struct sh_pfc_soc_info {
|
|||
* sh_pfc_soc_info pinmux_data array macros
|
||||
*/
|
||||
|
||||
/*
|
||||
* Describe generic pinmux data
|
||||
* - data_or_mark: *_DATA or *_MARK enum ID
|
||||
* - ids...: List of enum IDs to associate with data_or_mark
|
||||
*/
|
||||
#define PINMUX_DATA(data_or_mark, ids...) data_or_mark, ids, 0
|
||||
|
||||
#define PINMUX_IPSR_NOGP(ispr, fn) \
|
||||
/*
|
||||
* Describe a pinmux configuration without GPIO function that needs
|
||||
* configuration in a Peripheral Function Select Register (IPSR)
|
||||
* - ipsr: IPSR field (unused, for documentation purposes only)
|
||||
* - fn: Function name, referring to a field in the IPSR
|
||||
*/
|
||||
#define PINMUX_IPSR_NOGP(ipsr, fn) \
|
||||
PINMUX_DATA(fn##_MARK, FN_##fn)
|
||||
#define PINMUX_IPSR_DATA(ipsr, fn) \
|
||||
|
||||
/*
|
||||
* Describe a pinmux configuration with GPIO function that needs configuration
|
||||
* in both a Peripheral Function Select Register (IPSR) and in a
|
||||
* GPIO/Peripheral Function Select Register (GPSR)
|
||||
* - ipsr: IPSR field
|
||||
* - fn: Function name, also referring to the IPSR field
|
||||
*/
|
||||
#define PINMUX_IPSR_GPSR(ipsr, fn) \
|
||||
PINMUX_DATA(fn##_MARK, FN_##fn, FN_##ipsr)
|
||||
#define PINMUX_IPSR_NOGM(ispr, fn, ms) \
|
||||
PINMUX_DATA(fn##_MARK, FN_##fn, FN_##ms)
|
||||
#define PINMUX_IPSR_NOFN(ipsr, fn, ms) \
|
||||
PINMUX_DATA(fn##_MARK, FN_##ipsr, FN_##ms)
|
||||
#define PINMUX_IPSR_MSEL(ipsr, fn, ms) \
|
||||
PINMUX_DATA(fn##_MARK, FN_##ms, FN_##ipsr, FN_##fn)
|
||||
|
||||
/*
|
||||
* Describe a pinmux configuration without GPIO function that needs
|
||||
* configuration in a Peripheral Function Select Register (IPSR), and where the
|
||||
* pinmux function has a representation in a Module Select Register (MOD_SEL).
|
||||
* - ipsr: IPSR field (unused, for documentation purposes only)
|
||||
* - fn: Function name, also referring to the IPSR field
|
||||
* - msel: Module selector
|
||||
*/
|
||||
#define PINMUX_IPSR_NOGM(ipsr, fn, msel) \
|
||||
PINMUX_DATA(fn##_MARK, FN_##fn, FN_##msel)
|
||||
|
||||
/*
|
||||
* Describe a pinmux configuration with GPIO function where the pinmux function
|
||||
* has no representation in a Peripheral Function Select Register (IPSR), but
|
||||
* instead solely depends on a group selection.
|
||||
* - gpsr: GPSR field
|
||||
* - fn: Function name, also referring to the GPSR field
|
||||
* - gsel: Group selector
|
||||
*/
|
||||
#define PINMUX_IPSR_NOFN(gpsr, fn, gsel) \
|
||||
PINMUX_DATA(fn##_MARK, FN_##gpsr, FN_##gsel)
|
||||
|
||||
/*
|
||||
* Describe a pinmux configuration with GPIO function that needs configuration
|
||||
* in both a Peripheral Function Select Register (IPSR) and a GPIO/Peripheral
|
||||
* Function Select Register (GPSR), and where the pinmux function has a
|
||||
* representation in a Module Select Register (MOD_SEL).
|
||||
* - ipsr: IPSR field
|
||||
* - fn: Function name, also referring to the IPSR field
|
||||
* - msel: Module selector
|
||||
*/
|
||||
#define PINMUX_IPSR_MSEL(ipsr, fn, msel) \
|
||||
PINMUX_DATA(fn##_MARK, FN_##msel, FN_##ipsr, FN_##fn)
|
||||
|
||||
/*
|
||||
* Describe a pinmux configuration for a single-function pin with GPIO
|
||||
|
|
@ -381,7 +461,7 @@ struct sh_pfc_soc_info {
|
|||
PINMUX_GPIO_FN(GPIO_FN_##str, PINMUX_FN_BASE, str##_MARK)
|
||||
|
||||
/*
|
||||
* PORTnCR macro
|
||||
* PORTnCR helper macro for SH-Mobile/R-Mobile
|
||||
*/
|
||||
#define PORTCR(nr, reg) \
|
||||
{ \
|
||||
|
|
|
|||
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