powerpc: Add little endian support to alignment handler
Handle most unaligned load and store faults in little endian mode. Strings, multiples and VSX are not supported. Signed-off-by: Anton Blanchard <anton@samba.org> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
This commit is contained in:
Anton Blanchard
Benjamin Herrenschmidt
Родитель
a5841a4602
Коммит
835e206a67
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@ -262,6 +262,7 @@ static int emulate_dcbz(struct pt_regs *regs, unsigned char __user *addr)
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#define SWIZ_PTR(p) ((unsigned char __user *)((p) ^ swiz))
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#ifdef __BIG_ENDIAN__
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static int emulate_multiple(struct pt_regs *regs, unsigned char __user *addr,
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unsigned int reg, unsigned int nb,
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unsigned int flags, unsigned int instr,
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@ -390,6 +391,7 @@ static int emulate_fp_pair(unsigned char __user *addr, unsigned int reg,
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return -EFAULT;
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return 1; /* exception handled and fixed up */
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}
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#endif
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#ifdef CONFIG_SPE
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@ -628,7 +630,7 @@ static int emulate_spe(struct pt_regs *regs, unsigned int reg,
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}
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#endif /* CONFIG_SPE */
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#ifdef CONFIG_VSX
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#if defined(CONFIG_VSX) && defined(__BIG_ENDIAN__)
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/*
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* Emulate VSX instructions...
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*/
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@ -702,18 +704,28 @@ int fix_alignment(struct pt_regs *regs)
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unsigned int dsisr;
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unsigned char __user *addr;
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unsigned long p, swiz;
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int ret;
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union {
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int ret, i;
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union data {
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u64 ll;
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double dd;
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unsigned char v[8];
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struct {
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#ifdef __LITTLE_ENDIAN__
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int low32;
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unsigned hi32;
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#else
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unsigned hi32;
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int low32;
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#endif
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} x32;
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struct {
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#ifdef __LITTLE_ENDIAN__
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short low16;
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unsigned char hi48[6];
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#else
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unsigned char hi48[6];
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short low16;
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#endif
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} x16;
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} data;
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@ -772,8 +784,9 @@ int fix_alignment(struct pt_regs *regs)
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/* Byteswap little endian loads and stores */
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swiz = 0;
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if (regs->msr & MSR_LE) {
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if ((regs->msr & MSR_LE) != (MSR_KERNEL & MSR_LE)) {
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flags ^= SW;
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#ifdef __BIG_ENDIAN__
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/*
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* So-called "PowerPC little endian" mode works by
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* swizzling addresses rather than by actually doing
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@ -786,11 +799,13 @@ int fix_alignment(struct pt_regs *regs)
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*/
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if (cpu_has_feature(CPU_FTR_PPC_LE))
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swiz = 7;
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#endif
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}
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/* DAR has the operand effective address */
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addr = (unsigned char __user *)regs->dar;
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#ifdef __BIG_ENDIAN__
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#ifdef CONFIG_VSX
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if ((instruction & 0xfc00003e) == 0x7c000018) {
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unsigned int elsize;
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@ -810,7 +825,7 @@ int fix_alignment(struct pt_regs *regs)
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elsize = 8;
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flags = 0;
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if (regs->msr & MSR_LE)
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if ((regs->msr & MSR_LE) != (MSR_KERNEL & MSR_LE))
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flags |= SW;
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if (instruction & 0x100)
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flags |= ST;
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@ -824,6 +839,9 @@ int fix_alignment(struct pt_regs *regs)
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PPC_WARN_ALIGNMENT(vsx, regs);
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return emulate_vsx(addr, reg, areg, regs, flags, nb, elsize);
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}
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#endif
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#else
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return -EFAULT;
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#endif
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/* A size of 0 indicates an instruction we don't support, with
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* the exception of DCBZ which is handled as a special case here
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@ -839,9 +857,13 @@ int fix_alignment(struct pt_regs *regs)
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* function
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*/
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if (flags & M) {
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#ifdef __BIG_ENDIAN__
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PPC_WARN_ALIGNMENT(multiple, regs);
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return emulate_multiple(regs, addr, reg, nb,
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flags, instr, swiz);
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#else
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return -EFAULT;
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#endif
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}
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/* Verify the address of the operand */
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@ -860,8 +882,12 @@ int fix_alignment(struct pt_regs *regs)
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/* Special case for 16-byte FP loads and stores */
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if (nb == 16) {
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#ifdef __BIG_ENDIAN__
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PPC_WARN_ALIGNMENT(fp_pair, regs);
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return emulate_fp_pair(addr, reg, flags);
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#else
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return -EFAULT;
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#endif
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}
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PPC_WARN_ALIGNMENT(unaligned, regs);
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@ -870,24 +896,28 @@ int fix_alignment(struct pt_regs *regs)
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* get it from register values
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*/
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if (!(flags & ST)) {
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unsigned int start = 0;
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switch (nb) {
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case 4:
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start = offsetof(union data, x32.low32);
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break;
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case 2:
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start = offsetof(union data, x16.low16);
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break;
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}
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data.ll = 0;
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ret = 0;
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p = (unsigned long) addr;
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switch (nb) {
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case 8:
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ret |= __get_user_inatomic(data.v[0], SWIZ_PTR(p++));
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ret |= __get_user_inatomic(data.v[1], SWIZ_PTR(p++));
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ret |= __get_user_inatomic(data.v[2], SWIZ_PTR(p++));
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ret |= __get_user_inatomic(data.v[3], SWIZ_PTR(p++));
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case 4:
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ret |= __get_user_inatomic(data.v[4], SWIZ_PTR(p++));
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ret |= __get_user_inatomic(data.v[5], SWIZ_PTR(p++));
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case 2:
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ret |= __get_user_inatomic(data.v[6], SWIZ_PTR(p++));
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ret |= __get_user_inatomic(data.v[7], SWIZ_PTR(p++));
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if (unlikely(ret))
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return -EFAULT;
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}
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p = (unsigned long)addr;
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for (i = 0; i < nb; i++)
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ret |= __get_user_inatomic(data.v[start + i],
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SWIZ_PTR(p++));
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if (unlikely(ret))
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return -EFAULT;
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} else if (flags & F) {
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data.dd = current->thread.TS_FPR(reg);
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if (flags & S) {
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@ -945,21 +975,24 @@ int fix_alignment(struct pt_regs *regs)
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/* Store result to memory or update registers */
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if (flags & ST) {
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ret = 0;
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p = (unsigned long) addr;
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unsigned int start = 0;
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switch (nb) {
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case 8:
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ret |= __put_user_inatomic(data.v[0], SWIZ_PTR(p++));
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ret |= __put_user_inatomic(data.v[1], SWIZ_PTR(p++));
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ret |= __put_user_inatomic(data.v[2], SWIZ_PTR(p++));
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ret |= __put_user_inatomic(data.v[3], SWIZ_PTR(p++));
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case 4:
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ret |= __put_user_inatomic(data.v[4], SWIZ_PTR(p++));
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ret |= __put_user_inatomic(data.v[5], SWIZ_PTR(p++));
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start = offsetof(union data, x32.low32);
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break;
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case 2:
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ret |= __put_user_inatomic(data.v[6], SWIZ_PTR(p++));
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ret |= __put_user_inatomic(data.v[7], SWIZ_PTR(p++));
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start = offsetof(union data, x16.low16);
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break;
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}
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ret = 0;
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p = (unsigned long)addr;
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for (i = 0; i < nb; i++)
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ret |= __put_user_inatomic(data.v[start + i],
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SWIZ_PTR(p++));
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if (unlikely(ret))
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return -EFAULT;
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} else if (flags & F)
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