mtd: spi-nor: move all spansion specifics into spansion.c
The clear status register flags is only available on spansion flashes. Move all the functions around that into the spanion module. Signed-off-by: Michael Walle <michael@walle.cc> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Tested-by: Pratyush Yadav <p.yadav@ti.com> # on mt35xu512aba, s28hs512t Reviewed-by: Pratyush Yadav <p.yadav@ti.com> Link: https://lore.kernel.org/r/20220223134358.1914798-29-michael@walle.cc
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@ -554,33 +554,6 @@ int spi_nor_write_ear(struct spi_nor *nor, u8 ear)
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return ret;
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}
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/**
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* spi_nor_clear_sr() - Clear the Status Register.
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* @nor: pointer to 'struct spi_nor'.
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*/
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static void spi_nor_clear_sr(struct spi_nor *nor)
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{
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int ret;
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if (nor->spimem) {
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struct spi_mem_op op =
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SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_CLSR, 0),
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SPI_MEM_OP_NO_ADDR,
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SPI_MEM_OP_NO_DUMMY,
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SPI_MEM_OP_NO_DATA);
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spi_nor_spimem_setup_op(nor, &op, nor->reg_proto);
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ret = spi_mem_exec_op(nor->spimem, &op);
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} else {
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ret = spi_nor_controller_ops_write_reg(nor, SPINOR_OP_CLSR,
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NULL, 0);
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}
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if (ret)
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dev_dbg(nor->dev, "error %d clearing SR\n", ret);
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}
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/**
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* spi_nor_sr_ready() - Query the Status Register to see if the flash is ready
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* for new commands.
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@ -595,28 +568,6 @@ int spi_nor_sr_ready(struct spi_nor *nor)
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if (ret)
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return ret;
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if (nor->flags & SNOR_F_USE_CLSR &&
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nor->bouncebuf[0] & (SR_E_ERR | SR_P_ERR)) {
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if (nor->bouncebuf[0] & SR_E_ERR)
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dev_err(nor->dev, "Erase Error occurred\n");
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else
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dev_err(nor->dev, "Programming Error occurred\n");
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spi_nor_clear_sr(nor);
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/*
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* WEL bit remains set to one when an erase or page program
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* error occurs. Issue a Write Disable command to protect
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* against inadvertent writes that can possibly corrupt the
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* contents of the memory.
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*/
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ret = spi_nor_write_disable(nor);
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if (ret)
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return ret;
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return -EIO;
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}
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return !(nor->bouncebuf[0] & SR_WIP);
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}
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@ -8,6 +8,7 @@
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#include "core.h"
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#define SPINOR_OP_CLSR 0x30 /* Clear status register 1 */
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#define SPINOR_OP_RD_ANY_REG 0x65 /* Read any register */
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#define SPINOR_OP_WR_ANY_REG 0x71 /* Write any register */
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#define SPINOR_REG_CYPRESS_CFR2V 0x00800003
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@ -294,6 +295,72 @@ static const struct flash_info spansion_nor_parts[] = {
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},
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};
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/**
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* spi_nor_clear_sr() - Clear the Status Register.
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* @nor: pointer to 'struct spi_nor'.
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*/
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static void spi_nor_clear_sr(struct spi_nor *nor)
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{
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int ret;
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if (nor->spimem) {
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struct spi_mem_op op =
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SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_CLSR, 0),
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SPI_MEM_OP_NO_ADDR,
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SPI_MEM_OP_NO_DUMMY,
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SPI_MEM_OP_NO_DATA);
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spi_nor_spimem_setup_op(nor, &op, nor->reg_proto);
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ret = spi_mem_exec_op(nor->spimem, &op);
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} else {
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ret = spi_nor_controller_ops_write_reg(nor, SPINOR_OP_CLSR,
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NULL, 0);
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}
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if (ret)
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dev_dbg(nor->dev, "error %d clearing SR\n", ret);
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}
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/**
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* spi_nor_sr_ready_and_clear() - Query the Status Register to see if the flash
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* is ready for new commands and clear it if there are any errors.
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* @nor: pointer to 'struct spi_nor'.
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*
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* Return: 1 if ready, 0 if not ready, -errno on errors.
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*/
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static int spi_nor_sr_ready_and_clear(struct spi_nor *nor)
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{
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int ret;
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ret = spi_nor_read_sr(nor, nor->bouncebuf);
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if (ret)
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return ret;
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if (nor->bouncebuf[0] & (SR_E_ERR | SR_P_ERR)) {
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if (nor->bouncebuf[0] & SR_E_ERR)
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dev_err(nor->dev, "Erase Error occurred\n");
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else
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dev_err(nor->dev, "Programming Error occurred\n");
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spi_nor_clear_sr(nor);
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/*
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* WEL bit remains set to one when an erase or page program
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* error occurs. Issue a Write Disable command to protect
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* against inadvertent writes that can possibly corrupt the
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* contents of the memory.
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*/
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ret = spi_nor_write_disable(nor);
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if (ret)
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return ret;
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return -EIO;
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}
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return !(nor->bouncebuf[0] & SR_WIP);
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}
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static void spansion_nor_late_init(struct spi_nor *nor)
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{
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if (nor->params->size > SZ_16M) {
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@ -302,6 +369,9 @@ static void spansion_nor_late_init(struct spi_nor *nor)
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nor->erase_opcode = SPINOR_OP_SE;
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nor->mtd.erasesize = nor->info->sector_size;
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}
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if (nor->flags & SNOR_F_USE_CLSR)
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nor->params->ready = spi_nor_sr_ready_and_clear;
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}
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static const struct spi_nor_fixups spansion_nor_fixups = {
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@ -90,7 +90,6 @@
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/* Used for Spansion flashes only. */
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#define SPINOR_OP_BRWR 0x17 /* Bank register write */
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#define SPINOR_OP_CLSR 0x30 /* Clear status register 1 */
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/* Used for Micron flashes only. */
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#define SPINOR_OP_RD_EVCR 0x65 /* Read EVCR register */
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