drm/ast: initial DP501 support (v0.2)
This is the initial attempt at porting the DP501 code from the userspace driver, the firmware file is in http://people.freedesktop.org/~airlied/ast_dp501_fw.bin this should really be exposed as another encoder/connector that is cloneable v0.2: init 3rd tx properly, add scratch reduction of VRAM size backup firmware properly. Signed-off-by: Dave Airlie <airlied@redhat.com>
This commit is contained in:
Dave Airlie
Родитель
0e5ce92438
Коммит
83c6620bae
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@ -4,6 +4,6 @@
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ccflags-y := -Iinclude/drm
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ast-y := ast_drv.o ast_main.o ast_mode.o ast_fb.o ast_ttm.o ast_post.o
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ast-y := ast_drv.o ast_main.o ast_mode.o ast_fb.o ast_ttm.o ast_post.o ast_dp501.o
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obj-$(CONFIG_DRM_AST) := ast.o
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@ -0,0 +1,410 @@
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#include <linux/firmware.h>
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#include <drm/drmP.h>
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#include "ast_drv.h"
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MODULE_FIRMWARE("ast_dp501_fw.bin");
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int ast_load_dp501_microcode(struct drm_device *dev)
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{
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struct ast_private *ast = dev->dev_private;
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static char *fw_name = "ast_dp501_fw.bin";
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int err;
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err = request_firmware(&ast->dp501_fw, fw_name, dev->dev);
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if (err)
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return err;
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return 0;
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}
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static void send_ack(struct ast_private *ast)
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{
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u8 sendack;
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sendack = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x9b, 0xff);
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sendack |= 0x80;
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ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x9b, 0x00, sendack);
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}
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static void send_nack(struct ast_private *ast)
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{
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u8 sendack;
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sendack = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x9b, 0xff);
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sendack &= ~0x80;
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ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x9b, 0x00, sendack);
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}
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static bool wait_ack(struct ast_private *ast)
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{
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u8 waitack;
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u32 retry = 0;
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do {
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waitack = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd2, 0xff);
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waitack &= 0x80;
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udelay(100);
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} while ((!waitack) && (retry++ < 1000));
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if (retry < 1000)
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return true;
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else
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return false;
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}
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static bool wait_nack(struct ast_private *ast)
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{
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u8 waitack;
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u32 retry = 0;
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do {
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waitack = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd2, 0xff);
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waitack &= 0x80;
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udelay(100);
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} while ((waitack) && (retry++ < 1000));
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if (retry < 1000)
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return true;
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else
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return false;
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}
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static void set_cmd_trigger(struct ast_private *ast)
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{
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ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x9b, ~0x40, 0x40);
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}
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static void clear_cmd_trigger(struct ast_private *ast)
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{
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ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x9b, ~0x40, 0x00);
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}
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#if 0
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static bool wait_fw_ready(struct ast_private *ast)
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{
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u8 waitready;
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u32 retry = 0;
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do {
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waitready = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd2, 0xff);
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waitready &= 0x40;
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udelay(100);
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} while ((!waitready) && (retry++ < 1000));
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if (retry < 1000)
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return true;
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else
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return false;
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}
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#endif
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static bool ast_write_cmd(struct drm_device *dev, u8 data)
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{
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struct ast_private *ast = dev->dev_private;
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int retry = 0;
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if (wait_nack(ast)) {
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send_nack(ast);
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ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x9a, 0x00, data);
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send_ack(ast);
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set_cmd_trigger(ast);
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do {
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if (wait_ack(ast)) {
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clear_cmd_trigger(ast);
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send_nack(ast);
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return true;
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}
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} while (retry++ < 100);
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}
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clear_cmd_trigger(ast);
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send_nack(ast);
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return false;
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}
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static bool ast_write_data(struct drm_device *dev, u8 data)
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{
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struct ast_private *ast = dev->dev_private;
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if (wait_nack(ast)) {
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send_nack(ast);
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ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x9a, 0x00, data);
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send_ack(ast);
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if (wait_ack(ast)) {
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send_nack(ast);
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return true;
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}
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}
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send_nack(ast);
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return false;
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}
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#if 0
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static bool ast_read_data(struct drm_device *dev, u8 *data)
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{
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struct ast_private *ast = dev->dev_private;
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u8 tmp;
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*data = 0;
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if (wait_ack(ast) == false)
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return false;
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tmp = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd3, 0xff);
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*data = tmp;
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if (wait_nack(ast) == false) {
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send_nack(ast);
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return false;
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}
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send_nack(ast);
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return true;
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}
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static void clear_cmd(struct ast_private *ast)
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{
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send_nack(ast);
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ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x9a, 0x00, 0x00);
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}
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#endif
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void ast_set_dp501_video_output(struct drm_device *dev, u8 mode)
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{
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ast_write_cmd(dev, 0x40);
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ast_write_data(dev, mode);
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msleep(10);
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}
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static u32 get_fw_base(struct ast_private *ast)
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{
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return ast_mindwm(ast, 0x1e6e2104) & 0x7fffffff;
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}
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bool ast_backup_fw(struct drm_device *dev, u8 *addr, u32 size)
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{
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struct ast_private *ast = dev->dev_private;
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u32 i, data;
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u32 boot_address;
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data = ast_mindwm(ast, 0x1e6e2100) & 0x01;
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if (data) {
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boot_address = get_fw_base(ast);
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for (i = 0; i < size; i += 4)
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*(u32 *)(addr + i) = ast_mindwm(ast, boot_address + i);
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return true;
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}
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return false;
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}
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bool ast_launch_m68k(struct drm_device *dev)
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{
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struct ast_private *ast = dev->dev_private;
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u32 i, data, len = 0;
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u32 boot_address;
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u8 *fw_addr = NULL;
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u8 jreg;
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data = ast_mindwm(ast, 0x1e6e2100) & 0x01;
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if (!data) {
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if (ast->dp501_fw_addr) {
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fw_addr = ast->dp501_fw_addr;
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len = 32*1024;
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} else if (ast->dp501_fw) {
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fw_addr = (u8 *)ast->dp501_fw->data;
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len = ast->dp501_fw->size;
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}
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/* Get BootAddress */
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ast_moutdwm(ast, 0x1e6e2000, 0x1688a8a8);
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data = ast_mindwm(ast, 0x1e6e0004);
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switch (data & 0x03) {
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case 0:
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boot_address = 0x44000000;
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break;
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default:
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case 1:
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boot_address = 0x48000000;
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break;
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case 2:
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boot_address = 0x50000000;
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break;
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case 3:
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boot_address = 0x60000000;
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break;
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}
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boot_address -= 0x200000; /* -2MB */
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/* copy image to buffer */
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for (i = 0; i < len; i += 4) {
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data = *(u32 *)(fw_addr + i);
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ast_moutdwm(ast, boot_address + i, data);
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}
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/* Init SCU */
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ast_moutdwm(ast, 0x1e6e2000, 0x1688a8a8);
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/* Launch FW */
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ast_moutdwm(ast, 0x1e6e2104, 0x80000000 + boot_address);
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ast_moutdwm(ast, 0x1e6e2100, 1);
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/* Update Scratch */
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data = ast_mindwm(ast, 0x1e6e2040) & 0xfffff1ff; /* D[11:9] = 100b: UEFI handling */
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data |= 0x800;
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ast_moutdwm(ast, 0x1e6e2040, data);
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jreg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x99, 0xfc); /* D[1:0]: Reserved Video Buffer */
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jreg |= 0x02;
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ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x99, jreg);
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}
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return true;
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}
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u8 ast_get_dp501_max_clk(struct drm_device *dev)
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{
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struct ast_private *ast = dev->dev_private;
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u32 boot_address, offset, data;
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u8 linkcap[4], linkrate, linklanes, maxclk = 0xff;
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boot_address = get_fw_base(ast);
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/* validate FW version */
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offset = 0xf000;
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data = ast_mindwm(ast, boot_address + offset);
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if ((data & 0xf0) != 0x10) /* version: 1x */
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return maxclk;
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/* Read Link Capability */
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offset = 0xf014;
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*(u32 *)linkcap = ast_mindwm(ast, boot_address + offset);
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if (linkcap[2] == 0) {
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linkrate = linkcap[0];
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linklanes = linkcap[1];
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data = (linkrate == 0x0a) ? (90 * linklanes) : (54 * linklanes);
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if (data > 0xff)
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data = 0xff;
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maxclk = (u8)data;
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}
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return maxclk;
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}
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bool ast_dp501_read_edid(struct drm_device *dev, u8 *ediddata)
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{
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struct ast_private *ast = dev->dev_private;
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u32 i, boot_address, offset, data;
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boot_address = get_fw_base(ast);
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/* validate FW version */
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offset = 0xf000;
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data = ast_mindwm(ast, boot_address + offset);
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if ((data & 0xf0) != 0x10)
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return false;
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/* validate PnP Monitor */
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offset = 0xf010;
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data = ast_mindwm(ast, boot_address + offset);
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if (!(data & 0x01))
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return false;
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/* Read EDID */
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offset = 0xf020;
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for (i = 0; i < 128; i += 4) {
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data = ast_mindwm(ast, boot_address + offset + i);
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*(u32 *)(ediddata + i) = data;
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}
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return true;
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}
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static bool ast_init_dvo(struct drm_device *dev)
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{
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struct ast_private *ast = dev->dev_private;
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u8 jreg;
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u32 data;
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ast_write32(ast, 0xf004, 0x1e6e0000);
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ast_write32(ast, 0xf000, 0x1);
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ast_write32(ast, 0x12000, 0x1688a8a8);
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jreg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff);
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if (!(jreg & 0x80)) {
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/* Init SCU DVO Settings */
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data = ast_read32(ast, 0x12008);
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/* delay phase */
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data &= 0xfffff8ff;
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data |= 0x00000500;
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ast_write32(ast, 0x12008, data);
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if (ast->chip == AST2300) {
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data = ast_read32(ast, 0x12084);
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/* multi-pins for DVO single-edge */
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data |= 0xfffe0000;
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ast_write32(ast, 0x12084, data);
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data = ast_read32(ast, 0x12088);
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/* multi-pins for DVO single-edge */
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data |= 0x000fffff;
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ast_write32(ast, 0x12088, data);
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data = ast_read32(ast, 0x12090);
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/* multi-pins for DVO single-edge */
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data &= 0xffffffcf;
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data |= 0x00000020;
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ast_write32(ast, 0x12090, data);
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} else { /* AST2400 */
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data = ast_read32(ast, 0x12088);
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/* multi-pins for DVO single-edge */
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data |= 0x30000000;
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ast_write32(ast, 0x12088, data);
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data = ast_read32(ast, 0x1208c);
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/* multi-pins for DVO single-edge */
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data |= 0x000000cf;
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ast_write32(ast, 0x1208c, data);
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data = ast_read32(ast, 0x120a4);
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/* multi-pins for DVO single-edge */
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data |= 0xffff0000;
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ast_write32(ast, 0x120a4, data);
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data = ast_read32(ast, 0x120a8);
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/* multi-pins for DVO single-edge */
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data |= 0x0000000f;
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ast_write32(ast, 0x120a8, data);
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data = ast_read32(ast, 0x12094);
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/* multi-pins for DVO single-edge */
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data |= 0x00000002;
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ast_write32(ast, 0x12094, data);
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}
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}
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/* Force to DVO */
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data = ast_read32(ast, 0x1202c);
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data &= 0xfffbffff;
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ast_write32(ast, 0x1202c, data);
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/* Init VGA DVO Settings */
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ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa3, 0xcf, 0x80);
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return true;
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}
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void ast_init_3rdtx(struct drm_device *dev)
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{
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struct ast_private *ast = dev->dev_private;
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u8 jreg;
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u32 data;
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if (ast->chip == AST2300 || ast->chip == AST2400) {
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jreg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd1, 0xff);
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switch (jreg & 0x0e) {
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case 0x04:
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ast_init_dvo(dev);
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break;
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case 0x08:
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ast_launch_m68k(dev);
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break;
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case 0x0c:
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ast_init_dvo(dev);
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break;
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default:
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if (ast->tx_chip_type == AST_TX_SIL164)
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ast_init_dvo(dev);
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else {
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ast_write32(ast, 0x12000, 0x1688a8a8);
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data = ast_read32(ast, 0x1202c);
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data &= 0xfffcffff;
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ast_write32(ast, 0, data);
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}
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}
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}
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}
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@ -65,6 +65,13 @@ enum ast_chip {
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AST1180,
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};
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enum ast_tx_chip {
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AST_TX_NONE,
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AST_TX_SIL164,
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AST_TX_ITE66121,
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AST_TX_DP501,
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};
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#define AST_DRAM_512Mx16 0
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#define AST_DRAM_1Gx16 1
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#define AST_DRAM_512Mx32 2
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@ -104,6 +111,11 @@ struct ast_private {
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struct ttm_bo_kmap_obj cache_kmap;
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int next_cursor;
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bool support_wide_screen;
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enum ast_tx_chip tx_chip_type;
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u8 dp501_maxclk;
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u8 *dp501_fw_addr;
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const struct firmware *dp501_fw; /* dp501 fw */
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};
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int ast_driver_load(struct drm_device *dev, unsigned long flags);
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@ -370,4 +382,14 @@ int ast_mmap(struct file *filp, struct vm_area_struct *vma);
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/* ast post */
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void ast_post_gpu(struct drm_device *dev);
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u32 ast_mindwm(struct ast_private *ast, u32 r);
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void ast_moutdwm(struct ast_private *ast, u32 r, u32 v);
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/* ast dp501 */
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int ast_load_dp501_microcode(struct drm_device *dev);
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void ast_set_dp501_video_output(struct drm_device *dev, u8 mode);
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bool ast_launch_m68k(struct drm_device *dev);
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bool ast_backup_fw(struct drm_device *dev, u8 *addr, u32 size);
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bool ast_dp501_read_edid(struct drm_device *dev, u8 *ediddata);
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u8 ast_get_dp501_max_clk(struct drm_device *dev);
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void ast_init_3rdtx(struct drm_device *dev);
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#endif
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|||
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@ -136,6 +136,31 @@ static int ast_detect_chip(struct drm_device *dev)
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break;
|
||||
}
|
||||
|
||||
ast->tx_chip_type = AST_TX_NONE;
|
||||
jreg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa3, 0xff);
|
||||
if (jreg & 0x80)
|
||||
ast->tx_chip_type = AST_TX_SIL164;
|
||||
if ((ast->chip == AST2300) || (ast->chip == AST2400)) {
|
||||
jreg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd1, 0xff);
|
||||
switch (jreg) {
|
||||
case 0x04:
|
||||
ast->tx_chip_type = AST_TX_SIL164;
|
||||
break;
|
||||
case 0x08:
|
||||
ast->dp501_fw_addr = kzalloc(32*1024, GFP_KERNEL);
|
||||
if (ast->dp501_fw_addr) {
|
||||
/* backup firmware */
|
||||
if (ast_backup_fw(dev, ast->dp501_fw_addr, 32*1024)) {
|
||||
kfree(ast->dp501_fw_addr);
|
||||
ast->dp501_fw_addr = NULL;
|
||||
}
|
||||
}
|
||||
/* fallthrough */
|
||||
case 0x0c:
|
||||
ast->tx_chip_type = AST_TX_DP501;
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -289,17 +314,32 @@ static u32 ast_get_vram_info(struct drm_device *dev)
|
|||
{
|
||||
struct ast_private *ast = dev->dev_private;
|
||||
u8 jreg;
|
||||
|
||||
u32 vram_size;
|
||||
ast_open_key(ast);
|
||||
|
||||
vram_size = AST_VIDMEM_DEFAULT_SIZE;
|
||||
jreg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xaa, 0xff);
|
||||
switch (jreg & 3) {
|
||||
case 0: return AST_VIDMEM_SIZE_8M;
|
||||
case 1: return AST_VIDMEM_SIZE_16M;
|
||||
case 2: return AST_VIDMEM_SIZE_32M;
|
||||
case 3: return AST_VIDMEM_SIZE_64M;
|
||||
case 0: vram_size = AST_VIDMEM_SIZE_8M; break;
|
||||
case 1: vram_size = AST_VIDMEM_SIZE_16M; break;
|
||||
case 2: vram_size = AST_VIDMEM_SIZE_32M; break;
|
||||
case 3: vram_size = AST_VIDMEM_SIZE_64M; break;
|
||||
}
|
||||
return AST_VIDMEM_DEFAULT_SIZE;
|
||||
|
||||
jreg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x99, 0xff);
|
||||
switch (jreg & 0x03) {
|
||||
case 1:
|
||||
vram_size -= 0x100000;
|
||||
break;
|
||||
case 2:
|
||||
vram_size -= 0x200000;
|
||||
break;
|
||||
case 3:
|
||||
vram_size -= 0x400000;
|
||||
break;
|
||||
}
|
||||
|
||||
return vram_size;
|
||||
}
|
||||
|
||||
int ast_driver_load(struct drm_device *dev, unsigned long flags)
|
||||
|
|
@ -376,6 +416,7 @@ int ast_driver_unload(struct drm_device *dev)
|
|||
{
|
||||
struct ast_private *ast = dev->dev_private;
|
||||
|
||||
kfree(ast->dp501_fw_addr);
|
||||
ast_mode_fini(dev);
|
||||
ast_fbdev_fini(dev);
|
||||
drm_mode_config_cleanup(dev);
|
||||
|
|
|
|||
|
|
@ -460,9 +460,13 @@ static void ast_crtc_dpms(struct drm_crtc *crtc, int mode)
|
|||
case DRM_MODE_DPMS_STANDBY:
|
||||
case DRM_MODE_DPMS_SUSPEND:
|
||||
ast_set_index_reg_mask(ast, AST_IO_SEQ_PORT, 0x1, 0xdf, 0);
|
||||
if (ast->tx_chip_type == AST_TX_DP501)
|
||||
ast_set_dp501_video_output(crtc->dev, 1);
|
||||
ast_crtc_load_lut(crtc);
|
||||
break;
|
||||
case DRM_MODE_DPMS_OFF:
|
||||
if (ast->tx_chip_type == AST_TX_DP501)
|
||||
ast_set_dp501_video_output(crtc->dev, 0);
|
||||
ast_set_index_reg_mask(ast, AST_IO_SEQ_PORT, 0x1, 0xdf, 0x20);
|
||||
break;
|
||||
}
|
||||
|
|
@ -738,9 +742,23 @@ static int ast_encoder_init(struct drm_device *dev)
|
|||
static int ast_get_modes(struct drm_connector *connector)
|
||||
{
|
||||
struct ast_connector *ast_connector = to_ast_connector(connector);
|
||||
struct ast_private *ast = connector->dev->dev_private;
|
||||
struct edid *edid;
|
||||
int ret;
|
||||
bool flags = false;
|
||||
if (ast->tx_chip_type == AST_TX_DP501) {
|
||||
ast->dp501_maxclk = 0xff;
|
||||
edid = kmalloc(128, GFP_KERNEL);
|
||||
if (!edid)
|
||||
return -ENOMEM;
|
||||
|
||||
flags = ast_dp501_read_edid(connector->dev, (u8 *)edid);
|
||||
if (flags)
|
||||
ast->dp501_maxclk = ast_get_dp501_max_clk(connector->dev);
|
||||
else
|
||||
kfree(edid);
|
||||
}
|
||||
if (!flags)
|
||||
edid = drm_get_edid(connector, &ast_connector->i2c->adapter);
|
||||
if (edid) {
|
||||
drm_mode_connector_update_edid_property(&ast_connector->base, edid);
|
||||
|
|
|
|||
|
|
@ -107,7 +107,7 @@ ast_set_def_ext_reg(struct drm_device *dev)
|
|||
ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb6, 0xff, reg);
|
||||
}
|
||||
|
||||
static u32 ast_mindwm(struct ast_private *ast, u32 r)
|
||||
u32 ast_mindwm(struct ast_private *ast, u32 r)
|
||||
{
|
||||
uint32_t data;
|
||||
|
||||
|
|
@ -120,7 +120,7 @@ static u32 ast_mindwm(struct ast_private *ast, u32 r)
|
|||
return ast_read32(ast, 0x10000 + (r & 0x0000ffff));
|
||||
}
|
||||
|
||||
static void ast_moutdwm(struct ast_private *ast, u32 r, u32 v)
|
||||
void ast_moutdwm(struct ast_private *ast, u32 r, u32 v)
|
||||
{
|
||||
uint32_t data;
|
||||
ast_write32(ast, 0xf004, r & 0xffff0000);
|
||||
|
|
@ -378,6 +378,8 @@ void ast_post_gpu(struct drm_device *dev)
|
|||
ast_init_dram_2300(dev);
|
||||
else
|
||||
ast_init_dram_reg(dev);
|
||||
|
||||
ast_init_3rdtx(dev);
|
||||
}
|
||||
|
||||
/* AST 2300 DRAM settings */
|
||||
|
|
|
|||
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