mbox: add polarfire soc system controller mailbox
This driver adds support for the single mailbox channel of the MSS system controller on the Microchip PolarFire SoC. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
This commit is contained in:
Conor Dooley
Jassi Brar
Родитель
ed9543d6f2
Коммит
83d7b15608
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@ -160,6 +160,18 @@ config MAILBOX_TEST
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Test client to help with testing new Controller driver
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implementations.
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config POLARFIRE_SOC_MAILBOX
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tristate "PolarFire SoC (MPFS) Mailbox"
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depends on HAS_IOMEM
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depends on SOC_MICROCHIP_POLARFIRE || COMPILE_TEST
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help
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This driver adds support for the PolarFire SoC (MPFS) mailbox controller.
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To compile this driver as a module, choose M here. the
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module will be called mailbox-mpfs.
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If unsure, say N.
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config QCOM_APCS_IPC
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tristate "Qualcomm APCS IPC driver"
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depends on ARCH_QCOM || COMPILE_TEST
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@ -41,6 +41,8 @@ obj-$(CONFIG_BCM_PDC_MBOX) += bcm-pdc-mailbox.o
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obj-$(CONFIG_BCM_FLEXRM_MBOX) += bcm-flexrm-mailbox.o
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obj-$(CONFIG_POLARFIRE_SOC_MAILBOX) += mailbox-mpfs.o
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obj-$(CONFIG_QCOM_APCS_IPC) += qcom-apcs-ipc-mailbox.o
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obj-$(CONFIG_TEGRA_HSP_MBOX) += tegra-hsp.o
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@ -0,0 +1,251 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Microchip PolarFire SoC (MPFS) system controller/mailbox controller driver
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*
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* Copyright (c) 2020 Microchip Corporation. All rights reserved.
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*
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* Author: Conor Dooley <conor.dooley@microchip.com>
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*
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*/
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#include <linux/io.h>
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#include <linux/err.h>
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/interrupt.h>
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#include <linux/platform_device.h>
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#include <linux/mailbox_controller.h>
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#include <soc/microchip/mpfs.h>
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#define SERVICES_CR_OFFSET 0x50u
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#define SERVICES_SR_OFFSET 0x54u
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#define MAILBOX_REG_OFFSET 0x800u
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#define MSS_SYS_MAILBOX_DATA_OFFSET 0u
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#define SCB_MASK_WIDTH 16u
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/* SCBCTRL service control register */
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#define SCB_CTRL_REQ (0)
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#define SCB_CTRL_REQ_MASK BIT(SCB_CTRL_REQ)
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#define SCB_CTRL_BUSY (1)
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#define SCB_CTRL_BUSY_MASK BIT(SCB_CTRL_BUSY)
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#define SCB_CTRL_ABORT (2)
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#define SCB_CTRL_ABORT_MASK BIT(SCB_CTRL_ABORT)
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#define SCB_CTRL_NOTIFY (3)
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#define SCB_CTRL_NOTIFY_MASK BIT(SCB_CTRL_NOTIFY)
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#define SCB_CTRL_POS (16)
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#define SCB_CTRL_MASK GENMASK_ULL(SCB_CTRL_POS + SCB_MASK_WIDTH, SCB_CTRL_POS)
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/* SCBCTRL service status register */
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#define SCB_STATUS_REQ (0)
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#define SCB_STATUS_REQ_MASK BIT(SCB_STATUS_REQ)
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#define SCB_STATUS_BUSY (1)
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#define SCB_STATUS_BUSY_MASK BIT(SCB_STATUS_BUSY)
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#define SCB_STATUS_ABORT (2)
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#define SCB_STATUS_ABORT_MASK BIT(SCB_STATUS_ABORT)
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#define SCB_STATUS_NOTIFY (3)
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#define SCB_STATUS_NOTIFY_MASK BIT(SCB_STATUS_NOTIFY)
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#define SCB_STATUS_POS (16)
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#define SCB_STATUS_MASK GENMASK_ULL(SCB_STATUS_POS + SCB_MASK_WIDTH, SCB_STATUS_POS)
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struct mpfs_mbox {
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struct mbox_controller controller;
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struct device *dev;
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int irq;
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void __iomem *mbox_base;
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void __iomem *int_reg;
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struct mbox_chan chans[1];
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struct mpfs_mss_response *response;
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u16 resp_offset;
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};
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static bool mpfs_mbox_busy(struct mpfs_mbox *mbox)
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{
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u32 status;
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status = readl_relaxed(mbox->mbox_base + SERVICES_SR_OFFSET);
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return status & SCB_STATUS_BUSY_MASK;
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}
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static int mpfs_mbox_send_data(struct mbox_chan *chan, void *data)
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{
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struct mpfs_mbox *mbox = (struct mpfs_mbox *)chan->con_priv;
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struct mpfs_mss_msg *msg = data;
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u32 tx_trigger;
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u16 opt_sel;
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u32 val = 0u;
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mbox->response = msg->response;
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mbox->resp_offset = msg->resp_offset;
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if (mpfs_mbox_busy(mbox))
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return -EBUSY;
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if (msg->cmd_data_size) {
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u32 index;
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u8 extra_bits = msg->cmd_data_size & 3;
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u32 *word_buf = (u32 *)msg->cmd_data;
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for (index = 0; index < (msg->cmd_data_size / 4); index++)
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writel_relaxed(word_buf[index],
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mbox->mbox_base + MAILBOX_REG_OFFSET + index * 0x4);
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if (extra_bits) {
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u8 i;
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u8 byte_off = ALIGN_DOWN(msg->cmd_data_size, 4);
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u8 *byte_buf = msg->cmd_data + byte_off;
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val = readl_relaxed(mbox->mbox_base +
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MAILBOX_REG_OFFSET + index * 0x4);
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for (i = 0u; i < extra_bits; i++) {
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val &= ~(0xffu << (i * 8u));
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val |= (byte_buf[i] << (i * 8u));
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}
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writel_relaxed(val,
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mbox->mbox_base + MAILBOX_REG_OFFSET + index * 0x4);
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}
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}
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opt_sel = ((msg->mbox_offset << 7u) | (msg->cmd_opcode & 0x7fu));
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tx_trigger = (opt_sel << SCB_CTRL_POS) & SCB_CTRL_MASK;
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tx_trigger |= SCB_CTRL_REQ_MASK | SCB_STATUS_NOTIFY_MASK;
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writel_relaxed(tx_trigger, mbox->mbox_base + SERVICES_CR_OFFSET);
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return 0;
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}
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static void mpfs_mbox_rx_data(struct mbox_chan *chan)
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{
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struct mpfs_mbox *mbox = (struct mpfs_mbox *)chan->con_priv;
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struct mpfs_mss_response *response = mbox->response;
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u16 num_words = ALIGN((response->resp_size), (4)) / 4U;
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u32 i;
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if (!response->resp_msg) {
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dev_err(mbox->dev, "failed to assign memory for response %d\n", -ENOMEM);
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return;
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}
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if (!mpfs_mbox_busy(mbox)) {
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for (i = 0; i < num_words; i++) {
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response->resp_msg[i] =
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readl_relaxed(mbox->mbox_base + MAILBOX_REG_OFFSET
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+ mbox->resp_offset + i * 0x4);
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}
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}
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mbox_chan_received_data(chan, response);
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}
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static irqreturn_t mpfs_mbox_inbox_isr(int irq, void *data)
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{
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struct mbox_chan *chan = data;
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struct mpfs_mbox *mbox = (struct mpfs_mbox *)chan->con_priv;
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writel_relaxed(0, mbox->int_reg);
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mpfs_mbox_rx_data(chan);
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mbox_chan_txdone(chan, 0);
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return IRQ_HANDLED;
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}
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static int mpfs_mbox_startup(struct mbox_chan *chan)
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{
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struct mpfs_mbox *mbox = (struct mpfs_mbox *)chan->con_priv;
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int ret = 0;
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if (!mbox)
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return -EINVAL;
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ret = devm_request_irq(mbox->dev, mbox->irq, mpfs_mbox_inbox_isr, 0, "mpfs-mailbox", chan);
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if (ret)
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dev_err(mbox->dev, "failed to register mailbox interrupt:%d\n", ret);
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return ret;
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}
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static void mpfs_mbox_shutdown(struct mbox_chan *chan)
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{
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struct mpfs_mbox *mbox = (struct mpfs_mbox *)chan->con_priv;
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devm_free_irq(mbox->dev, mbox->irq, chan);
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}
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static const struct mbox_chan_ops mpfs_mbox_ops = {
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.send_data = mpfs_mbox_send_data,
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.startup = mpfs_mbox_startup,
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.shutdown = mpfs_mbox_shutdown,
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};
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static int mpfs_mbox_probe(struct platform_device *pdev)
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{
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struct mpfs_mbox *mbox;
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struct resource *regs;
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int ret;
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mbox = devm_kzalloc(&pdev->dev, sizeof(*mbox), GFP_KERNEL);
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if (!mbox)
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return -ENOMEM;
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mbox->mbox_base = devm_platform_get_and_ioremap_resource(pdev, 0, ®s);
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if (IS_ERR(mbox->mbox_base))
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return PTR_ERR(mbox->mbox_base);
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mbox->int_reg = devm_platform_get_and_ioremap_resource(pdev, 1, ®s);
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if (IS_ERR(mbox->int_reg))
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return PTR_ERR(mbox->int_reg);
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mbox->irq = platform_get_irq(pdev, 0);
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if (mbox->irq < 0)
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return mbox->irq;
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mbox->dev = &pdev->dev;
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mbox->chans[0].con_priv = mbox;
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mbox->controller.dev = mbox->dev;
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mbox->controller.num_chans = 1;
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mbox->controller.chans = mbox->chans;
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mbox->controller.ops = &mpfs_mbox_ops;
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mbox->controller.txdone_irq = true;
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ret = devm_mbox_controller_register(&pdev->dev, &mbox->controller);
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if (ret) {
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dev_err(&pdev->dev, "Registering MPFS mailbox controller failed\n");
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return ret;
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}
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dev_info(&pdev->dev, "Registered MPFS mailbox controller driver\n");
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return 0;
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}
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static const struct of_device_id mpfs_mbox_of_match[] = {
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{.compatible = "microchip,polarfire-soc-mailbox", },
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{},
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};
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MODULE_DEVICE_TABLE(of, mpfs_mbox_of_match);
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static struct platform_driver mpfs_mbox_driver = {
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.driver = {
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.name = "mpfs-mailbox",
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.of_match_table = mpfs_mbox_of_match,
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},
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.probe = mpfs_mbox_probe,
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};
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module_platform_driver(mpfs_mbox_driver);
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MODULE_LICENSE("GPL v2");
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MODULE_AUTHOR("Conor Dooley <conor.dooley@microchip.com>");
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MODULE_DESCRIPTION("MPFS mailbox controller driver");
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@ -0,0 +1,43 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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*
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* Microchip PolarFire SoC (MPFS)
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*
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* Copyright (c) 2020 Microchip Corporation. All rights reserved.
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*
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* Author: Conor Dooley <conor.dooley@microchip.com>
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*
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*/
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#ifndef __SOC_MPFS_H__
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#define __SOC_MPFS_H__
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#include <linux/types.h>
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#include <linux/of_device.h>
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struct mpfs_sys_controller;
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struct mpfs_mss_msg {
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u8 cmd_opcode;
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u16 cmd_data_size;
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struct mpfs_mss_response *response;
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u8 *cmd_data;
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u16 mbox_offset;
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u16 resp_offset;
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};
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struct mpfs_mss_response {
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u32 resp_status;
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u32 *resp_msg;
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u16 resp_size;
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};
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#if IS_ENABLED(CONFIG_POLARFIRE_SOC_SYS_CTRL)
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int mpfs_blocking_transaction(struct mpfs_sys_controller *mpfs_client, void *msg);
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struct mpfs_sys_controller *mpfs_sys_controller_get(struct device_node *mailbox_node);
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#endif /* if IS_ENABLED(CONFIG_POLARFIRE_SOC_SYS_CTRL) */
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#endif /* __SOC_MPFS_H__ */
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