Merge branch 'pci/host/mt7621'
- Add MediaTek MT7621 SoC PCIe host controller (moved from staging) (Sergio Paracuellos) * pci/host/mt7621: MAINTAINERS: Add Sergio Paracuellos as MT7621 PCIe maintainer PCI: mt7621: Add MediaTek MT7621 PCIe host controller driver dt-bindings: PCI: Add MT7621 SoC PCIe host controller # Conflicts: # drivers/pci/controller/Kconfig # drivers/pci/controller/Makefile
This commit is contained in:
Bjorn Helgaas
Коммит
83e168d607
|
|
@ -0,0 +1,142 @@
|
|||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/pci/mediatek,mt7621-pcie.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: MediaTek MT7621 PCIe controller
|
||||
|
||||
maintainers:
|
||||
- Sergio Paracuellos <sergio.paracuellos@gmail.com>
|
||||
|
||||
description: |+
|
||||
MediaTek MT7621 PCIe subsys supports a single Root Complex (RC)
|
||||
with 3 Root Ports. Each Root Port supports a Gen1 1-lane Link
|
||||
|
||||
allOf:
|
||||
- $ref: /schemas/pci/pci-bus.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: mediatek,mt7621-pci
|
||||
|
||||
reg:
|
||||
items:
|
||||
- description: host-pci bridge registers
|
||||
- description: pcie port 0 RC control registers
|
||||
- description: pcie port 1 RC control registers
|
||||
- description: pcie port 2 RC control registers
|
||||
|
||||
ranges:
|
||||
maxItems: 2
|
||||
|
||||
patternProperties:
|
||||
'pcie@[0-2],0':
|
||||
type: object
|
||||
$ref: /schemas/pci/pci-bus.yaml#
|
||||
|
||||
properties:
|
||||
resets:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
phys:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- "#interrupt-cells"
|
||||
- interrupt-map-mask
|
||||
- interrupt-map
|
||||
- resets
|
||||
- clocks
|
||||
- phys
|
||||
- phy-names
|
||||
- ranges
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- ranges
|
||||
- "#interrupt-cells"
|
||||
- interrupt-map-mask
|
||||
- interrupt-map
|
||||
- reset-gpios
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/interrupt-controller/mips-gic.h>
|
||||
|
||||
pcie: pcie@1e140000 {
|
||||
compatible = "mediatek,mt7621-pci";
|
||||
reg = <0x1e140000 0x100>,
|
||||
<0x1e142000 0x100>,
|
||||
<0x1e143000 0x100>,
|
||||
<0x1e144000 0x100>;
|
||||
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pcie_pins>;
|
||||
device_type = "pci";
|
||||
ranges = <0x02000000 0 0x60000000 0x60000000 0 0x10000000>, /* pci memory */
|
||||
<0x01000000 0 0x1e160000 0x1e160000 0 0x00010000>; /* io space */
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0xF800 0 0 0>;
|
||||
interrupt-map = <0x0000 0 0 0 &gic GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0x0800 0 0 0 &gic GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0x1000 0 0 0 &gic GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reset-gpios = <&gpio 19 GPIO_ACTIVE_LOW>;
|
||||
|
||||
pcie@0,0 {
|
||||
reg = <0x0000 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
device_type = "pci";
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &gic GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH>;
|
||||
resets = <&rstctrl 24>;
|
||||
clocks = <&clkctrl 24>;
|
||||
phys = <&pcie0_phy 1>;
|
||||
phy-names = "pcie-phy0";
|
||||
ranges;
|
||||
};
|
||||
|
||||
pcie@1,0 {
|
||||
reg = <0x0800 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
device_type = "pci";
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &gic GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>;
|
||||
resets = <&rstctrl 25>;
|
||||
clocks = <&clkctrl 25>;
|
||||
phys = <&pcie0_phy 1>;
|
||||
phy-names = "pcie-phy1";
|
||||
ranges;
|
||||
};
|
||||
|
||||
pcie@2,0 {
|
||||
reg = <0x1000 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
device_type = "pci";
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &gic GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>;
|
||||
resets = <&rstctrl 26>;
|
||||
clocks = <&clkctrl 26>;
|
||||
phys = <&pcie2_phy 0>;
|
||||
phy-names = "pcie-phy2";
|
||||
ranges;
|
||||
};
|
||||
};
|
||||
...
|
||||
|
|
@ -11849,6 +11849,12 @@ S: Maintained
|
|||
F: Documentation/devicetree/bindings/i2c/i2c-mt7621.txt
|
||||
F: drivers/i2c/busses/i2c-mt7621.c
|
||||
|
||||
MEDIATEK MT7621 PCIE CONTROLLER DRIVER
|
||||
M: Sergio Paracuellos <sergio.paracuellos@gmail.com>
|
||||
S: Maintained
|
||||
F: Documentation/devicetree/bindings/pci/mediatek,mt7621-pcie.yaml
|
||||
F: drivers/pci/controller/pcie-mt7621.c
|
||||
|
||||
MEDIATEK MT7621 PHY PCI DRIVER
|
||||
M: Sergio Paracuellos <sergio.paracuellos@gmail.com>
|
||||
S: Maintained
|
||||
|
|
|
|||
|
|
@ -51,7 +51,8 @@ choice
|
|||
select SYS_SUPPORTS_HIGHMEM
|
||||
select MIPS_GIC
|
||||
select CLKSRC_MIPS_GIC
|
||||
select HAVE_PCI if PCI_MT7621
|
||||
select HAVE_PCI
|
||||
select PCI_DRIVERS_GENERIC
|
||||
select SOC_BUS
|
||||
endchoice
|
||||
|
||||
|
|
|
|||
|
|
@ -330,6 +330,14 @@ config PCIE_APPLE
|
|||
|
||||
If unsure, say Y if you have an Apple Silicon system.
|
||||
|
||||
config PCIE_MT7621
|
||||
tristate "MediaTek MT7621 PCIe Controller"
|
||||
depends on (RALINK && SOC_MT7621) || (MIPS && COMPILE_TEST)
|
||||
select PHY_MT7621_PCI
|
||||
default SOC_MT7621
|
||||
help
|
||||
This selects a driver for the MediaTek MT7621 PCIe Controller.
|
||||
|
||||
source "drivers/pci/controller/dwc/Kconfig"
|
||||
source "drivers/pci/controller/mobiveil/Kconfig"
|
||||
source "drivers/pci/controller/cadence/Kconfig"
|
||||
|
|
|
|||
|
|
@ -38,6 +38,8 @@ obj-$(CONFIG_PCIE_BRCMSTB) += pcie-brcmstb.o
|
|||
obj-$(CONFIG_PCI_LOONGSON) += pci-loongson.o
|
||||
obj-$(CONFIG_PCIE_HISI_ERR) += pcie-hisi-error.o
|
||||
obj-$(CONFIG_PCIE_APPLE) += pcie-apple.o
|
||||
obj-$(CONFIG_PCIE_MT7621) += pcie-mt7621.o
|
||||
|
||||
# pcie-hisi.o quirks are needed even without CONFIG_PCIE_DW
|
||||
obj-y += dwc/
|
||||
obj-y += mobiveil/
|
||||
|
|
|
|||
|
|
@ -30,18 +30,18 @@
|
|||
#include <linux/reset.h>
|
||||
#include <linux/sys_soc.h>
|
||||
|
||||
/* MediaTek specific configuration registers */
|
||||
/* MediaTek-specific configuration registers */
|
||||
#define PCIE_FTS_NUM 0x70c
|
||||
#define PCIE_FTS_NUM_MASK GENMASK(15, 8)
|
||||
#define PCIE_FTS_NUM_L0(x) (((x) & 0xff) << 8)
|
||||
|
||||
/* Host-PCI bridge registers */
|
||||
#define RALINK_PCI_PCICFG_ADDR 0x0000
|
||||
#define RALINK_PCI_PCIMSK_ADDR 0x000C
|
||||
#define RALINK_PCI_PCIMSK_ADDR 0x000c
|
||||
#define RALINK_PCI_CONFIG_ADDR 0x0020
|
||||
#define RALINK_PCI_CONFIG_DATA 0x0024
|
||||
#define RALINK_PCI_MEMBASE 0x0028
|
||||
#define RALINK_PCI_IOBASE 0x002C
|
||||
#define RALINK_PCI_IOBASE 0x002c
|
||||
|
||||
/* PCIe RC control registers */
|
||||
#define RALINK_PCI_ID 0x0030
|
||||
|
|
@ -132,7 +132,7 @@ static inline void pcie_port_write(struct mt7621_pcie_port *port,
|
|||
static inline u32 mt7621_pci_get_cfgaddr(unsigned int bus, unsigned int slot,
|
||||
unsigned int func, unsigned int where)
|
||||
{
|
||||
return (((where & 0xF00) >> 8) << 24) | (bus << 16) | (slot << 11) |
|
||||
return (((where & 0xf00) >> 8) << 24) | (bus << 16) | (slot << 11) |
|
||||
(func << 8) | (where & 0xfc) | 0x80000000;
|
||||
}
|
||||
|
||||
|
|
@ -217,7 +217,7 @@ static int setup_cm_memory_region(struct pci_host_bridge *host)
|
|||
|
||||
entry = resource_list_first_type(&host->windows, IORESOURCE_MEM);
|
||||
if (!entry) {
|
||||
dev_err(dev, "Cannot get memory resource\n");
|
||||
dev_err(dev, "cannot get memory resource\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
|
|
@ -280,7 +280,7 @@ static int mt7621_pcie_parse_port(struct mt7621_pcie *pcie,
|
|||
port->gpio_rst = devm_gpiod_get_index_optional(dev, "reset", slot,
|
||||
GPIOD_OUT_LOW);
|
||||
if (IS_ERR(port->gpio_rst)) {
|
||||
dev_err(dev, "Failed to get GPIO for PCIe%d\n", slot);
|
||||
dev_err(dev, "failed to get GPIO for PCIe%d\n", slot);
|
||||
err = PTR_ERR(port->gpio_rst);
|
||||
goto remove_reset;
|
||||
}
|
||||
|
|
@ -409,7 +409,7 @@ static int mt7621_pcie_init_ports(struct mt7621_pcie *pcie)
|
|||
|
||||
err = mt7621_pcie_init_port(port);
|
||||
if (err) {
|
||||
dev_err(dev, "Initiating port %d failed\n", slot);
|
||||
dev_err(dev, "initializing port %d failed\n", slot);
|
||||
list_del(&port->list);
|
||||
}
|
||||
}
|
||||
|
|
@ -476,7 +476,7 @@ static int mt7621_pcie_enable_ports(struct pci_host_bridge *host)
|
|||
|
||||
entry = resource_list_first_type(&host->windows, IORESOURCE_IO);
|
||||
if (!entry) {
|
||||
dev_err(dev, "Cannot get io resource\n");
|
||||
dev_err(dev, "cannot get io resource\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
|
|
@ -541,25 +541,25 @@ static int mt7621_pci_probe(struct platform_device *pdev)
|
|||
|
||||
err = mt7621_pcie_parse_dt(pcie);
|
||||
if (err) {
|
||||
dev_err(dev, "Parsing DT failed\n");
|
||||
dev_err(dev, "parsing DT failed\n");
|
||||
return err;
|
||||
}
|
||||
|
||||
err = mt7621_pcie_init_ports(pcie);
|
||||
if (err) {
|
||||
dev_err(dev, "Nothing connected in virtual bridges\n");
|
||||
dev_err(dev, "nothing connected in virtual bridges\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
err = mt7621_pcie_enable_ports(bridge);
|
||||
if (err) {
|
||||
dev_err(dev, "Error enabling pcie ports\n");
|
||||
dev_err(dev, "error enabling pcie ports\n");
|
||||
goto remove_resets;
|
||||
}
|
||||
|
||||
err = setup_cm_memory_region(bridge);
|
||||
if (err) {
|
||||
dev_err(dev, "Error setting up iocu mem regions\n");
|
||||
dev_err(dev, "error setting up iocu mem regions\n");
|
||||
goto remove_resets;
|
||||
}
|
||||
|
||||
|
|
@ -86,8 +86,6 @@ source "drivers/staging/vc04_services/Kconfig"
|
|||
|
||||
source "drivers/staging/pi433/Kconfig"
|
||||
|
||||
source "drivers/staging/mt7621-pci/Kconfig"
|
||||
|
||||
source "drivers/staging/mt7621-dma/Kconfig"
|
||||
|
||||
source "drivers/staging/ralink-gdma/Kconfig"
|
||||
|
|
|
|||
|
|
@ -33,7 +33,6 @@ obj-$(CONFIG_KS7010) += ks7010/
|
|||
obj-$(CONFIG_GREYBUS) += greybus/
|
||||
obj-$(CONFIG_BCM2835_VCHIQ) += vc04_services/
|
||||
obj-$(CONFIG_PI433) += pi433/
|
||||
obj-$(CONFIG_PCI_MT7621) += mt7621-pci/
|
||||
obj-$(CONFIG_SOC_MT7621) += mt7621-dma/
|
||||
obj-$(CONFIG_DMA_RALINK) += ralink-gdma/
|
||||
obj-$(CONFIG_SOC_MT7621) += mt7621-dts/
|
||||
|
|
|
|||
|
|
@ -1,8 +0,0 @@
|
|||
# SPDX-License-Identifier: GPL-2.0
|
||||
config PCI_MT7621
|
||||
tristate "MediaTek MT7621 PCI Controller"
|
||||
depends on RALINK
|
||||
select PCI_DRIVERS_GENERIC
|
||||
help
|
||||
This selects a driver for the MediaTek MT7621 PCI Controller.
|
||||
|
||||
|
|
@ -1,2 +0,0 @@
|
|||
# SPDX-License-Identifier: GPL-2.0
|
||||
obj-$(CONFIG_PCI_MT7621) += pci-mt7621.o
|
||||
|
|
@ -1,4 +0,0 @@
|
|||
|
||||
- general code review and cleanup
|
||||
|
||||
Cc: NeilBrown <neil@brown.name>
|
||||
|
|
@ -1,104 +0,0 @@
|
|||
MediaTek MT7621 PCIe controller
|
||||
|
||||
Required properties:
|
||||
- compatible: "mediatek,mt7621-pci"
|
||||
- device_type: Must be "pci"
|
||||
- reg: Base addresses and lengths of the PCIe subsys and root ports.
|
||||
- bus-range: Range of bus numbers associated with this controller.
|
||||
- #address-cells: Address representation for root ports (must be 3)
|
||||
- pinctrl-names : The pin control state names.
|
||||
- pinctrl-0: The "default" pinctrl state.
|
||||
- #size-cells: Size representation for root ports (must be 2)
|
||||
- ranges: Ranges for the PCI memory and I/O regions.
|
||||
- #interrupt-cells: Must be 1
|
||||
- interrupt-map-mask and interrupt-map: Standard PCI IRQ mapping properties.
|
||||
Please refer to the standard PCI bus binding document for a more detailed
|
||||
explanation.
|
||||
- status: either "disabled" or "okay".
|
||||
- resets: Must contain an entry for each entry in reset-names.
|
||||
See ../reset/reset.txt for details.
|
||||
- reset-names: Must be "pcie0", "pcie1", "pcieN"... based on the number of
|
||||
root ports.
|
||||
- clocks: Must contain an entry for each entry in clock-names.
|
||||
See ../clocks/clock-bindings.txt for details.
|
||||
- clock-names: Must be "pcie0", "pcie1", "pcieN"... based on the number of
|
||||
root ports.
|
||||
- reset-gpios: GPIO specs for the reset pins.
|
||||
|
||||
In addition, the device tree node must have sub-nodes describing each PCIe port
|
||||
interface, having the following mandatory properties:
|
||||
|
||||
Required properties:
|
||||
- reg: Only the first four bytes are used to refer to the correct bus number
|
||||
and device number.
|
||||
- #address-cells: Must be 3
|
||||
- #size-cells: Must be 2
|
||||
- ranges: Sub-ranges distributed from the PCIe controller node. An empty
|
||||
property is sufficient.
|
||||
- bus-range: Range of bus numbers associated with this port.
|
||||
|
||||
Example for MT7621:
|
||||
|
||||
pcie: pcie@1e140000 {
|
||||
compatible = "mediatek,mt7621-pci";
|
||||
reg = <0x1e140000 0x100 /* host-pci bridge registers */
|
||||
0x1e142000 0x100 /* pcie port 0 RC control registers */
|
||||
0x1e143000 0x100 /* pcie port 1 RC control registers */
|
||||
0x1e144000 0x100>; /* pcie port 2 RC control registers */
|
||||
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pcie_pins>;
|
||||
|
||||
device_type = "pci";
|
||||
|
||||
bus-range = <0 255>;
|
||||
ranges = <
|
||||
0x02000000 0 0x00000000 0x60000000 0 0x10000000 /* pci memory */
|
||||
0x01000000 0 0x00000000 0x1e160000 0 0x00010000 /* io space */
|
||||
>;
|
||||
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0xF0000 0 0 1>;
|
||||
interrupt-map = <0x10000 0 0 1 &gic GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0x20000 0 0 1 &gic GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0x30000 0 0 1 &gic GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
status = "disabled";
|
||||
|
||||
resets = <&rstctrl 24 &rstctrl 25 &rstctrl 26>;
|
||||
reset-names = "pcie0", "pcie1", "pcie2";
|
||||
clocks = <&clkctrl 24 &clkctrl 25 &clkctrl 26>;
|
||||
clock-names = "pcie0", "pcie1", "pcie2";
|
||||
|
||||
reset-gpios = <&gpio 19 GPIO_ACTIVE_LOW>,
|
||||
<&gpio 8 GPIO_ACTIVE_LOW>,
|
||||
<&gpio 7 GPIO_ACTIVE_LOW>;
|
||||
|
||||
pcie@0,0 {
|
||||
reg = <0x0000 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
bus-range = <0x00 0xff>;
|
||||
};
|
||||
|
||||
pcie@1,0 {
|
||||
reg = <0x0800 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
bus-range = <0x00 0xff>;
|
||||
};
|
||||
|
||||
pcie@2,0 {
|
||||
reg = <0x1000 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
bus-range = <0x00 0xff>;
|
||||
};
|
||||
};
|
||||
|
||||
Загрузка…
Ссылка в новой задаче