sparc64: Use consistent chmc_ prefix in variables, types, and functions.
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
David S. Miller
Родитель
b28422e32b
Коммит
83ef64b9de
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@ -35,35 +35,35 @@ MODULE_VERSION(DRV_MODULE_VERSION);
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#define CHMCTRL_NDGRPS 2
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#define CHMCTRL_NDIMMS 4
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#define DIMMS_PER_MC (CHMCTRL_NDGRPS * CHMCTRL_NDIMMS)
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#define CHMC_DIMMS_PER_MC (CHMCTRL_NDGRPS * CHMCTRL_NDIMMS)
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/* OBP memory-layout property format. */
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struct obp_map {
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struct chmc_obp_map {
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unsigned char dimm_map[144];
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unsigned char pin_map[576];
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};
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#define DIMM_LABEL_SZ 8
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struct obp_mem_layout {
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struct chmc_obp_mem_layout {
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/* One max 8-byte string label per DIMM. Usually
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* this matches the label on the motherboard where
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* that DIMM resides.
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*/
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char dimm_labels[DIMMS_PER_MC][DIMM_LABEL_SZ];
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char dimm_labels[CHMC_DIMMS_PER_MC][DIMM_LABEL_SZ];
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/* If symmetric use map[0], else it is
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* asymmetric and map[1] should be used.
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*/
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char symmetric;
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char symmetric;
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struct obp_map map[2];
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struct chmc_obp_map map[2];
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};
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#define CHMCTRL_NBANKS 4
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struct bank_info {
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struct mctrl_info *mp;
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struct chmc_bank_info {
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struct chmc *p;
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int bank_id;
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u64 raw_reg;
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@ -77,28 +77,28 @@ struct bank_info {
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unsigned long size;
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};
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struct mctrl_info {
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struct list_head list;
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int portid;
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struct chmc {
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struct list_head list;
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int portid;
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struct obp_mem_layout layout_prop;
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int layout_size;
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struct chmc_obp_mem_layout layout_prop;
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int layout_size;
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void __iomem *regs;
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void __iomem *regs;
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u64 timing_control1;
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u64 timing_control2;
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u64 timing_control3;
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u64 timing_control4;
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u64 memaddr_control;
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u64 timing_control1;
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u64 timing_control2;
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u64 timing_control3;
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u64 timing_control4;
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u64 memaddr_control;
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struct bank_info logical_banks[CHMCTRL_NBANKS];
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struct chmc_bank_info logical_banks[CHMCTRL_NBANKS];
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};
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static LIST_HEAD(mctrl_list);
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/* Does BANK decode PHYS_ADDR? */
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static int bank_match(struct bank_info *bp, unsigned long phys_addr)
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static int chmc_bank_match(struct chmc_bank_info *bp, unsigned long phys_addr)
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{
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unsigned long upper_bits = (phys_addr & PA_UPPER_BITS) >> PA_UPPER_BITS_SHIFT;
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unsigned long lower_bits = (phys_addr & PA_LOWER_BITS) >> PA_LOWER_BITS_SHIFT;
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@ -130,14 +130,13 @@ static int bank_match(struct bank_info *bp, unsigned long phys_addr)
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}
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/* Given PHYS_ADDR, search memory controller banks for a match. */
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static struct bank_info *find_bank(unsigned long phys_addr)
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static struct chmc_bank_info *chmc_find_bank(unsigned long phys_addr)
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{
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struct list_head *mctrl_head = &mctrl_list;
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struct list_head *mctrl_entry = mctrl_head->next;
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for (;;) {
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struct mctrl_info *mp =
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list_entry(mctrl_entry, struct mctrl_info, list);
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struct chmc *p = list_entry(mctrl_entry, struct chmc, list);
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int bank_no;
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if (mctrl_entry == mctrl_head)
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@ -145,10 +144,10 @@ static struct bank_info *find_bank(unsigned long phys_addr)
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mctrl_entry = mctrl_entry->next;
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for (bank_no = 0; bank_no < CHMCTRL_NBANKS; bank_no++) {
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struct bank_info *bp;
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struct chmc_bank_info *bp;
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bp = &mp->logical_banks[bank_no];
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if (bank_match(bp, phys_addr))
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bp = &p->logical_banks[bank_no];
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if (chmc_bank_match(bp, phys_addr))
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return bp;
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}
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}
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@ -163,11 +162,11 @@ int chmc_getunumber(int syndrome_code,
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unsigned long phys_addr,
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char *buf, int buflen)
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{
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struct bank_info *bp;
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struct obp_mem_layout *prop;
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struct chmc_bank_info *bp;
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struct chmc_obp_mem_layout *prop;
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int bank_in_controller, first_dimm;
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bp = find_bank(phys_addr);
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bp = chmc_find_bank(phys_addr);
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if (bp == NULL ||
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syndrome_code < SYNDROME_MIN ||
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syndrome_code > SYNDROME_MAX) {
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@ -178,13 +177,13 @@ int chmc_getunumber(int syndrome_code,
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return 0;
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}
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prop = &bp->mp->layout_prop;
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prop = &bp->p->layout_prop;
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bank_in_controller = bp->bank_id & (CHMCTRL_NBANKS - 1);
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first_dimm = (bank_in_controller & (CHMCTRL_NDGRPS - 1));
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first_dimm *= CHMCTRL_NDIMMS;
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if (syndrome_code != SYNDROME_MIN) {
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struct obp_map *map;
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struct chmc_obp_map *map;
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int qword, where_in_line, where, map_index, map_offset;
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unsigned int map_val;
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@ -252,7 +251,7 @@ int chmc_getunumber(int syndrome_code,
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* the code is executing, you must use special ASI load/store else
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* you go through the global mapping.
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*/
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static u64 read_mcreg(struct mctrl_info *mp, unsigned long offset)
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static u64 chmc_read_mcreg(struct chmc *p, unsigned long offset)
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{
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unsigned long ret, this_cpu;
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@ -260,14 +259,14 @@ static u64 read_mcreg(struct mctrl_info *mp, unsigned long offset)
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this_cpu = real_hard_smp_processor_id();
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if (mp->portid == this_cpu) {
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if (p->portid == this_cpu) {
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__asm__ __volatile__("ldxa [%1] %2, %0"
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: "=r" (ret)
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: "r" (offset), "i" (ASI_MCU_CTRL_REG));
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} else {
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__asm__ __volatile__("ldxa [%1] %2, %0"
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: "=r" (ret)
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: "r" (mp->regs + offset),
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: "r" (p->regs + offset),
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"i" (ASI_PHYS_BYPASS_EC_E));
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}
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@ -277,164 +276,168 @@ static u64 read_mcreg(struct mctrl_info *mp, unsigned long offset)
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}
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#if 0 /* currently unused */
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static void write_mcreg(struct mctrl_info *mp, unsigned long offset, u64 val)
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static void chmc_write_mcreg(struct chmc *p, unsigned long offset, u64 val)
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{
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if (mp->portid == smp_processor_id()) {
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if (p->portid == smp_processor_id()) {
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__asm__ __volatile__("stxa %0, [%1] %2"
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: : "r" (val),
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"r" (offset), "i" (ASI_MCU_CTRL_REG));
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} else {
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__asm__ __volatile__("ldxa %0, [%1] %2"
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: : "r" (val),
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"r" (mp->regs + offset),
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"r" (p->regs + offset),
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"i" (ASI_PHYS_BYPASS_EC_E));
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}
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}
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#endif
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static void interpret_one_decode_reg(struct mctrl_info *mp, int which_bank, u64 val)
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static void chmc_interpret_one_decode_reg(struct chmc *p, int which_bank, u64 val)
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{
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struct bank_info *p = &mp->logical_banks[which_bank];
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struct chmc_bank_info *bp = &p->logical_banks[which_bank];
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p->mp = mp;
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p->bank_id = (CHMCTRL_NBANKS * mp->portid) + which_bank;
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p->raw_reg = val;
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p->valid = (val & MEM_DECODE_VALID) >> MEM_DECODE_VALID_SHIFT;
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p->uk = (val & MEM_DECODE_UK) >> MEM_DECODE_UK_SHIFT;
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p->um = (val & MEM_DECODE_UM) >> MEM_DECODE_UM_SHIFT;
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p->lk = (val & MEM_DECODE_LK) >> MEM_DECODE_LK_SHIFT;
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p->lm = (val & MEM_DECODE_LM) >> MEM_DECODE_LM_SHIFT;
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bp->p = p;
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bp->bank_id = (CHMCTRL_NBANKS * p->portid) + which_bank;
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bp->raw_reg = val;
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bp->valid = (val & MEM_DECODE_VALID) >> MEM_DECODE_VALID_SHIFT;
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bp->uk = (val & MEM_DECODE_UK) >> MEM_DECODE_UK_SHIFT;
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bp->um = (val & MEM_DECODE_UM) >> MEM_DECODE_UM_SHIFT;
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bp->lk = (val & MEM_DECODE_LK) >> MEM_DECODE_LK_SHIFT;
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bp->lm = (val & MEM_DECODE_LM) >> MEM_DECODE_LM_SHIFT;
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p->base = (p->um);
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p->base &= ~(p->uk);
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p->base <<= PA_UPPER_BITS_SHIFT;
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bp->base = (bp->um);
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bp->base &= ~(bp->uk);
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bp->base <<= PA_UPPER_BITS_SHIFT;
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switch(p->lk) {
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switch(bp->lk) {
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case 0xf:
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default:
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p->interleave = 1;
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bp->interleave = 1;
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break;
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case 0xe:
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p->interleave = 2;
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bp->interleave = 2;
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break;
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case 0xc:
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p->interleave = 4;
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bp->interleave = 4;
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break;
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case 0x8:
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p->interleave = 8;
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bp->interleave = 8;
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break;
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case 0x0:
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p->interleave = 16;
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bp->interleave = 16;
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break;
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};
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/* UK[10] is reserved, and UK[11] is not set for the SDRAM
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* bank size definition.
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*/
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p->size = (((unsigned long)p->uk &
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((1UL << 10UL) - 1UL)) + 1UL) << PA_UPPER_BITS_SHIFT;
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p->size /= p->interleave;
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bp->size = (((unsigned long)bp->uk &
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((1UL << 10UL) - 1UL)) + 1UL) << PA_UPPER_BITS_SHIFT;
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bp->size /= bp->interleave;
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}
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static void fetch_decode_regs(struct mctrl_info *mp)
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static void chmc_fetch_decode_regs(struct chmc *p)
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{
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if (mp->layout_size == 0)
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if (p->layout_size == 0)
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return;
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interpret_one_decode_reg(mp, 0,
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read_mcreg(mp, CHMCTRL_DECODE1));
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interpret_one_decode_reg(mp, 1,
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read_mcreg(mp, CHMCTRL_DECODE2));
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interpret_one_decode_reg(mp, 2,
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read_mcreg(mp, CHMCTRL_DECODE3));
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interpret_one_decode_reg(mp, 3,
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read_mcreg(mp, CHMCTRL_DECODE4));
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chmc_interpret_one_decode_reg(p, 0,
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chmc_read_mcreg(p, CHMCTRL_DECODE1));
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chmc_interpret_one_decode_reg(p, 1,
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chmc_read_mcreg(p, CHMCTRL_DECODE2));
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chmc_interpret_one_decode_reg(p, 2,
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chmc_read_mcreg(p, CHMCTRL_DECODE3));
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chmc_interpret_one_decode_reg(p, 3,
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chmc_read_mcreg(p, CHMCTRL_DECODE4));
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}
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static int __devinit chmc_probe(struct of_device *op,
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const struct of_device_id *match)
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{
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struct device_node *dp = op->node;
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struct mctrl_info *mp;
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unsigned long ver;
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const void *pval;
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int len, portid;
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struct chmc *p;
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int err;
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err = -ENODEV;
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__asm__ ("rdpr %%ver, %0" : "=r" (ver));
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if ((ver >> 32UL) == __JALAPENO_ID ||
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(ver >> 32UL) == __SERRANO_ID)
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return -ENODEV;
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mp = kzalloc(sizeof(*mp), GFP_KERNEL);
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if (!mp)
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return -ENOMEM;
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goto out;
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portid = of_getintprop_default(dp, "portid", -1);
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if (portid == -1)
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goto fail;
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goto out;
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mp->portid = portid;
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pval = of_get_property(dp, "memory-layout", &len);
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mp->layout_size = len;
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if (pval && len > sizeof(p->layout_prop)) {
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printk(KERN_ERR PFX "Unexpected memory-layout property "
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"size %d.\n", len);
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goto out;
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}
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err = -ENOMEM;
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p = kzalloc(sizeof(*p), GFP_KERNEL);
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if (!p) {
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printk(KERN_ERR PFX "Could not allocate struct chmc.\n");
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goto out;
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}
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p->portid = portid;
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p->layout_size = len;
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if (!pval)
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mp->layout_size = 0;
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else {
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if (mp->layout_size > sizeof(mp->layout_prop)) {
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printk(KERN_ERR PFX "Unexpected memory-layout property "
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"size %d.\n", mp->layout_size);
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goto fail;
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}
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memcpy(&mp->layout_prop, pval, len);
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}
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p->layout_size = 0;
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else
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memcpy(&p->layout_prop, pval, len);
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mp->regs = of_ioremap(&op->resource[0], 0, 0x48, "chmc");
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if (!mp->regs) {
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p->regs = of_ioremap(&op->resource[0], 0, 0x48, "chmc");
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if (!p->regs) {
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printk(KERN_ERR PFX "Could not map registers.\n");
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goto fail;
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goto out_free;
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}
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if (mp->layout_size != 0UL) {
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mp->timing_control1 = read_mcreg(mp, CHMCTRL_TCTRL1);
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mp->timing_control2 = read_mcreg(mp, CHMCTRL_TCTRL2);
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mp->timing_control3 = read_mcreg(mp, CHMCTRL_TCTRL3);
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mp->timing_control4 = read_mcreg(mp, CHMCTRL_TCTRL4);
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mp->memaddr_control = read_mcreg(mp, CHMCTRL_MACTRL);
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if (p->layout_size != 0UL) {
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p->timing_control1 = chmc_read_mcreg(p, CHMCTRL_TCTRL1);
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p->timing_control2 = chmc_read_mcreg(p, CHMCTRL_TCTRL2);
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p->timing_control3 = chmc_read_mcreg(p, CHMCTRL_TCTRL3);
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p->timing_control4 = chmc_read_mcreg(p, CHMCTRL_TCTRL4);
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p->memaddr_control = chmc_read_mcreg(p, CHMCTRL_MACTRL);
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}
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fetch_decode_regs(mp);
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chmc_fetch_decode_regs(p);
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list_add(&mp->list, &mctrl_list);
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list_add(&p->list, &mctrl_list);
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/* Report the device. */
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printk(KERN_INFO PFX "UltraSPARC-III memory controller at %s [%s]\n",
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dp->full_name,
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(mp->layout_size ? "ACTIVE" : "INACTIVE"));
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(p->layout_size ? "ACTIVE" : "INACTIVE"));
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dev_set_drvdata(&op->dev, mp);
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dev_set_drvdata(&op->dev, p);
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return 0;
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err = 0;
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fail:
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if (mp) {
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if (mp->regs != NULL)
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of_iounmap(&op->resource[0], mp->regs, 0x48);
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kfree(mp);
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}
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return -1;
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out:
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return err;
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out_free:
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kfree(p);
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goto out;
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}
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static int __devexit chmc_remove(struct of_device *op)
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{
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struct mctrl_info *mp = dev_get_drvdata(&op->dev);
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struct chmc *p = dev_get_drvdata(&op->dev);
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if (mp) {
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list_del(&mp->list);
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of_iounmap(&op->resource[0], mp->regs, 0x48);
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kfree(mp);
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if (p) {
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list_del(&p->list);
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of_iounmap(&op->resource[0], p->regs, 0x48);
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kfree(p);
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}
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return 0;
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}
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