Another new soc - the rk3228 quad-core cortex-a7, a new rk3036 board,
support for the efuses on Rockchip socs and some improvements for rk3288 regulators. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQEcBAABCAAGBQJWd0xyAAoJEPOmecmc0R2B71UIAJu6jDdfk5kmYzyXjBloBNwd PVRojGzVjCwCiVKX7GWINSf3D7dTKeYUwVs9uouVW4Q/iIk/l4Iq46+yg20ZODNM 3haS2hwztRPEKeU+0qhYdoJf2cWOKzk0RP90umTMMVt2xnqbQCBFAW4NuE4DBLHe 5o7R99ORKHi+IjBaI6Wtk1JoRNNkyYIDW6eLC9mxAJs32mr1ee45uidhPBD+VX+n 1nf/yUPs6bc1yPyNhFN49AywYvjg02y96/4ER6bBtOcEw91uDc0ld0M10H/mvujT B+w8U6xBUWulUU53MS8aVKDZ+bp4o6YZZbIq/FJtaz3c+bhj8Rjl4UnlZh+gaiA= =Zp6y -----END PGP SIGNATURE----- Merge tag 'v4.5-rockchip-dts32-2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into next/dt Another new soc - the rk3228 quad-core cortex-a7, a new rk3036 board, support for the efuses on Rockchip socs and some improvements for rk3288 regulators. * tag 'v4.5-rockchip-dts32-2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: ARM: dts: rockchip: add the kylin board for rk3036 ARM: dts: rockchip: add the sdio/sdmmc node for rk3036 ARM: dts: rockchip: fix the pinctrl bias settings for rk3036 ARM: dts: rockchip: add eFuse node for rk3188 SoCs ARM: dts: rockchip: add eFuse node for rk3066a SoCs ARM: dts: rockchip: add eFuse config of rk3288 SoC ARM: dts: rockchip: add rk3228-evb board ARM: dts: rockchip: add core rk3228 dtsi clk: rockchip: Add the clock ids of rk3288 eFuses ARM: dts: rockchip: Fix typo in rk3288 sdmmc card detect pin name ARM: dts: rockchip: fix voltage ranges for rk3288-evb-act8846 board ARM: dts: rockchip: move the public part to rk3288-evb common ARM: dts: rockchip: add 2 regulators for rk3288-evb-act8846 ARM: dts: rockchip: correct the name of REG8 for rk3288-evb-act8846 clk: rockchip: add dt-binding header for rk3228 clk: rockchip: add id for mipidsi sclk on rk3288 Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson
Коммит
84658cbde8
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@ -1,6 +1,10 @@
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Rockchip platforms device tree bindings
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---------------------------------------
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- Kylin RK3036 board:
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Required root node properties:
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- compatible = "rockchip,kylin-rk3036", "rockchip,rk3036";
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- MarsBoard RK3066 board:
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Required root node properties:
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- compatible = "haoyu,marsboard-rk3066", "rockchip,rk3066a";
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@ -86,3 +90,7 @@ Rockchip platforms device tree bindings
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- Rockchip R88 board:
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Required root node properties:
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- compatible = "rockchip,r88", "rockchip,rk3368";
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- Rockchip RK3228 Evaluation board:
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Required root node properties:
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- compatible = "rockchip,rk3228-evb", "rockchip,rk3228";
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@ -527,10 +527,12 @@ dtb-$(CONFIG_ARCH_REALVIEW) += \
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arm-realview-pb11mp.dtb
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dtb-$(CONFIG_ARCH_ROCKCHIP) += \
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rk3036-evb.dtb \
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rk3036-kylin.dtb \
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rk3066a-bqcurie2.dtb \
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rk3066a-marsboard.dtb \
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rk3066a-rayeager.dtb \
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rk3188-radxarock.dtb \
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rk3228-evb.dtb \
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rk3288-evb-act8846.dtb \
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rk3288-evb-rk808.dtb \
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rk3288-firefly-beta.dtb \
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@ -0,0 +1,300 @@
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/*
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* This file is dual-licensed: you can use it either under the terms
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* of the GPL or the X11 license, at your option. Note that this dual
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* licensing only applies to this file, and not this project as a
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* whole.
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*
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* a) This file is free software; you can redistribute it and/or
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||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of the
|
||||
* License, or (at your option) any later version.
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||||
*
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||||
* This file is distributed in the hope that it will be useful,
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||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
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||||
*
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||||
* Or, alternatively,
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||||
*
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||||
* b) Permission is hereby granted, free of charge, to any person
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||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use,
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||||
* copy, modify, merge, publish, distribute, sublicense, and/or
|
||||
* sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following
|
||||
* conditions:
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||||
*
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||||
* The above copyright notice and this permission notice shall be
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||||
* included in all copies or substantial portions of the Software.
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||||
*
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||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
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*/
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/dts-v1/;
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#include "rk3036.dtsi"
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/ {
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model = "Rockchip RK3036 KylinBoard";
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compatible = "rockchip,rk3036-kylin", "rockchip,rk3036";
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vcc_sys: vsys-regulator {
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compatible = "regulator-fixed";
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regulator-name = "vcc_sys";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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regulator-always-on;
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regulator-boot-on;
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};
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};
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&acodec {
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status = "okay";
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};
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&emmc {
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status = "okay";
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};
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&i2c1 {
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clock-frequency = <400000>;
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status = "okay";
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rk808: pmic@1b {
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compatible = "rockchip,rk808";
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reg = <0x1b>;
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interrupt-parent = <&gpio2>;
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interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
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pinctrl-names = "default";
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pinctrl-0 = <&pmic_int &global_pwroff>;
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rockchip,system-power-controller;
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wakeup-source;
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#clock-cells = <1>;
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clock-output-names = "xin32k", "rk808-clkout2";
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vcc1-supply = <&vcc_sys>;
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vcc2-supply = <&vcc_sys>;
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vcc3-supply = <&vcc_sys>;
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vcc4-supply = <&vcc_sys>;
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vcc6-supply = <&vcc_sys>;
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vcc7-supply = <&vcc_sys>;
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vcc8-supply = <&vcc_18>;
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vcc9-supply = <&vcc_io>;
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vcc10-supply = <&vcc_io>;
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vcc11-supply = <&vcc_sys>;
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vcc12-supply = <&vcc_io>;
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vddio-supply = <&vccio_pmu>;
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regulators {
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vdd_cpu: DCDC_REG1 {
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regulator-always-on;
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regulator-boot-on;
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regulator-min-microvolt = <750000>;
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regulator-max-microvolt = <1350000>;
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regulator-name = "vdd_arm";
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regulator-state-mem {
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regulator-off-in-suspend;
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};
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};
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vdd_gpu: DCDC_REG2 {
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regulator-always-on;
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regulator-boot-on;
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regulator-min-microvolt = <850000>;
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regulator-max-microvolt = <1250000>;
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regulator-name = "vdd_gpu";
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regulator-state-mem {
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regulator-on-in-suspend;
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regulator-suspend-microvolt = <1000000>;
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};
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};
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vcc_ddr: DCDC_REG3 {
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regulator-always-on;
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regulator-boot-on;
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regulator-name = "vcc_ddr";
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regulator-state-mem {
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regulator-on-in-suspend;
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};
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};
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vcc_io: DCDC_REG4 {
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regulator-always-on;
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regulator-boot-on;
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-name = "vcc_io";
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regulator-state-mem {
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regulator-on-in-suspend;
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regulator-suspend-microvolt = <3300000>;
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};
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};
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vccio_pmu: LDO_REG1 {
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regulator-always-on;
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regulator-boot-on;
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-name = "vccio_pmu";
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regulator-state-mem {
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regulator-on-in-suspend;
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regulator-suspend-microvolt = <3300000>;
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};
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};
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vcc_tp: LDO_REG2 {
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regulator-always-on;
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regulator-boot-on;
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-name = "vcc_tp";
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regulator-state-mem {
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regulator-off-in-suspend;
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};
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};
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vdd_10: LDO_REG3 {
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regulator-always-on;
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regulator-boot-on;
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regulator-min-microvolt = <1000000>;
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regulator-max-microvolt = <1000000>;
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regulator-name = "vdd_10";
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regulator-state-mem {
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regulator-on-in-suspend;
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regulator-suspend-microvolt = <1000000>;
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};
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};
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vcc18_lcd: LDO_REG4 {
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regulator-always-on;
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regulator-boot-on;
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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regulator-name = "vcc18_lcd";
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regulator-state-mem {
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regulator-on-in-suspend;
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regulator-suspend-microvolt = <1800000>;
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};
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};
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vccio_sd: LDO_REG5 {
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regulator-always-on;
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regulator-boot-on;
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <3300000>;
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regulator-name = "vccio_sd";
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regulator-state-mem {
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regulator-on-in-suspend;
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regulator-suspend-microvolt = <3300000>;
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};
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};
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vout5: LDO_REG6 {
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regulator-always-on;
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regulator-boot-on;
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <2500000>;
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regulator-name = "vout5";
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regulator-state-mem {
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regulator-on-in-suspend;
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regulator-suspend-microvolt = <1800000>;
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};
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};
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vcc_18: LDO_REG7 {
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regulator-always-on;
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regulator-boot-on;
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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regulator-name = "vcc_18";
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regulator-state-mem {
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regulator-on-in-suspend;
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regulator-suspend-microvolt = <1800000>;
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};
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};
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vcca_codec: LDO_REG8 {
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regulator-always-on;
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regulator-boot-on;
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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regulator-name = "vcca_codec";
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regulator-state-mem {
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regulator-on-in-suspend;
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regulator-suspend-microvolt = <1800000>;
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};
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};
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vcc_wl: SWITCH_REG1 {
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regulator-always-on;
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regulator-boot-on;
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regulator-name = "vcc_wl";
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regulator-state-mem {
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regulator-on-in-suspend;
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};
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};
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vcc_lcd: SWITCH_REG2 {
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regulator-always-on;
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regulator-boot-on;
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regulator-name = "vcc_lcd";
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regulator-state-mem {
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regulator-on-in-suspend;
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};
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};
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};
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};
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};
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&i2c2 {
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status = "okay";
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};
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&sdio {
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status = "okay";
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broken-cd;
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bus-width = <4>;
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cap-sdio-irq;
|
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default-sample-phase = <90>;
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keep-power-in-suspend;
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non-removable;
|
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num-slots = <1>;
|
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pinctrl-names = "default";
|
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pinctrl-0 = <&sdio_clk &sdio_cmd &sdio_bus4>;
|
||||
};
|
||||
|
||||
&uart2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_host {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_otg {
|
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status = "okay";
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
pmic {
|
||||
pmic_int: pmic-int {
|
||||
rockchip,pins = <2 2 RK_FUNC_GPIO &pcfg_pull_default>;
|
||||
};
|
||||
};
|
||||
|
||||
sleep {
|
||||
global_pwroff: global-pwroff {
|
||||
rockchip,pins = <2 7 RK_FUNC_1 &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -55,6 +55,8 @@
|
|||
i2c1 = &i2c1;
|
||||
i2c2 = &i2c2;
|
||||
mshc0 = &emmc;
|
||||
mshc1 = &sdmmc;
|
||||
mshc2 = &sdio;
|
||||
serial0 = &uart0;
|
||||
serial1 = &uart1;
|
||||
serial2 = &uart2;
|
||||
|
|
@ -184,6 +186,30 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
sdmmc: dwmmc@10214000 {
|
||||
compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc";
|
||||
reg = <0x10214000 0x4000>;
|
||||
clock-frequency = <37500000>;
|
||||
clock-freq-min-max = <400000 37500000>;
|
||||
clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
|
||||
clock-names = "biu", "ciu";
|
||||
fifo-depth = <0x100>;
|
||||
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sdio: dwmmc@10218000 {
|
||||
compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc";
|
||||
reg = <0x10218000 0x4000>;
|
||||
clock-freq-min-max = <400000 37500000>;
|
||||
clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
|
||||
<&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
|
||||
clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
|
||||
fifo-depth = <0x100>;
|
||||
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
emmc: dwmmc@1021c000 {
|
||||
compatible = "rockchip,rk3288-dw-mshc";
|
||||
reg = <0x1021c000 0x4000>;
|
||||
|
|
@ -427,12 +453,8 @@
|
|||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
pcfg_pull_up: pcfg-pull-up {
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
pcfg_pull_down: pcfg-pull-down {
|
||||
bias-pull-down;
|
||||
pcfg_pull_default: pcfg_pull_default {
|
||||
bias-pull-pin-default;
|
||||
};
|
||||
|
||||
pcfg_pull_none: pcfg-pull-none {
|
||||
|
|
@ -463,6 +485,52 @@
|
|||
};
|
||||
};
|
||||
|
||||
sdmmc {
|
||||
sdmmc_clk: sdmmc-clk {
|
||||
rockchip,pins = <1 16 RK_FUNC_1 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
sdmmc_cmd: sdmmc-cmd {
|
||||
rockchip,pins = <1 15 RK_FUNC_1 &pcfg_pull_default>;
|
||||
};
|
||||
|
||||
sdmmc_cd: sdmcc-cd {
|
||||
rockchip,pins = <1 17 RK_FUNC_1 &pcfg_pull_default>;
|
||||
};
|
||||
|
||||
sdmmc_bus1: sdmmc-bus1 {
|
||||
rockchip,pins = <1 18 RK_FUNC_1 &pcfg_pull_default>;
|
||||
};
|
||||
|
||||
sdmmc_bus4: sdmmc-bus4 {
|
||||
rockchip,pins = <1 18 RK_FUNC_1 &pcfg_pull_default>,
|
||||
<1 19 RK_FUNC_1 &pcfg_pull_default>,
|
||||
<1 20 RK_FUNC_1 &pcfg_pull_default>,
|
||||
<1 21 RK_FUNC_1 &pcfg_pull_default>;
|
||||
};
|
||||
};
|
||||
|
||||
sdio {
|
||||
sdio_bus1: sdio-bus1 {
|
||||
rockchip,pins = <0 11 RK_FUNC_1 &pcfg_pull_default>;
|
||||
};
|
||||
|
||||
sdio_bus4: sdio-bus4 {
|
||||
rockchip,pins = <0 11 RK_FUNC_1 &pcfg_pull_default>,
|
||||
<0 12 RK_FUNC_1 &pcfg_pull_default>,
|
||||
<0 13 RK_FUNC_1 &pcfg_pull_default>,
|
||||
<0 14 RK_FUNC_1 &pcfg_pull_default>;
|
||||
};
|
||||
|
||||
sdio_cmd: sdio-cmd {
|
||||
rockchip,pins = <0 8 RK_FUNC_1 &pcfg_pull_default>;
|
||||
};
|
||||
|
||||
sdio_clk: sdio-clk {
|
||||
rockchip,pins = <0 9 RK_FUNC_1 &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
emmc {
|
||||
/*
|
||||
* We run eMMC at max speed; bump up drive strength.
|
||||
|
|
@ -473,18 +541,18 @@
|
|||
};
|
||||
|
||||
emmc_cmd: emmc-cmd {
|
||||
rockchip,pins = <2 1 RK_FUNC_2 &pcfg_pull_none>;
|
||||
rockchip,pins = <2 1 RK_FUNC_2 &pcfg_pull_default>;
|
||||
};
|
||||
|
||||
emmc_bus8: emmc-bus8 {
|
||||
rockchip,pins = <1 24 RK_FUNC_2 &pcfg_pull_none>,
|
||||
<1 25 RK_FUNC_2 &pcfg_pull_none>,
|
||||
<1 26 RK_FUNC_2 &pcfg_pull_none>,
|
||||
<1 27 RK_FUNC_2 &pcfg_pull_none>,
|
||||
<1 28 RK_FUNC_2 &pcfg_pull_none>,
|
||||
<1 29 RK_FUNC_2 &pcfg_pull_none>,
|
||||
<1 30 RK_FUNC_2 &pcfg_pull_none>,
|
||||
<1 31 RK_FUNC_2 &pcfg_pull_none>;
|
||||
rockchip,pins = <1 24 RK_FUNC_2 &pcfg_pull_default>,
|
||||
<1 25 RK_FUNC_2 &pcfg_pull_default>,
|
||||
<1 26 RK_FUNC_2 &pcfg_pull_default>,
|
||||
<1 27 RK_FUNC_2 &pcfg_pull_default>,
|
||||
<1 28 RK_FUNC_2 &pcfg_pull_default>,
|
||||
<1 29 RK_FUNC_2 &pcfg_pull_default>,
|
||||
<1 30 RK_FUNC_2 &pcfg_pull_default>,
|
||||
<1 31 RK_FUNC_2 &pcfg_pull_default>;
|
||||
};
|
||||
};
|
||||
|
||||
|
|
@ -522,12 +590,12 @@
|
|||
|
||||
uart0 {
|
||||
uart0_xfer: uart0-xfer {
|
||||
rockchip,pins = <0 16 RK_FUNC_1 &pcfg_pull_up>,
|
||||
rockchip,pins = <0 16 RK_FUNC_1 &pcfg_pull_default>,
|
||||
<0 17 RK_FUNC_1 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
uart0_cts: uart0-cts {
|
||||
rockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_up>;
|
||||
rockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_default>;
|
||||
};
|
||||
|
||||
uart0_rts: uart0-rts {
|
||||
|
|
@ -537,7 +605,7 @@
|
|||
|
||||
uart1 {
|
||||
uart1_xfer: uart1-xfer {
|
||||
rockchip,pins = <2 22 RK_FUNC_1 &pcfg_pull_none>,
|
||||
rockchip,pins = <2 22 RK_FUNC_1 &pcfg_pull_default>,
|
||||
<2 23 RK_FUNC_1 &pcfg_pull_none>;
|
||||
};
|
||||
/* no rts / cts for uart1 */
|
||||
|
|
@ -545,7 +613,7 @@
|
|||
|
||||
uart2 {
|
||||
uart2_xfer: uart2-xfer {
|
||||
rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_none>,
|
||||
rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_default>,
|
||||
<1 19 RK_FUNC_2 &pcfg_pull_none>;
|
||||
};
|
||||
/* no rts / cts for uart2 */
|
||||
|
|
|
|||
|
|
@ -159,6 +159,19 @@
|
|||
clock-names = "timer", "pclk";
|
||||
};
|
||||
|
||||
efuse: efuse@20010000 {
|
||||
compatible = "rockchip,rockchip-efuse";
|
||||
reg = <0x20010000 0x4000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
clocks = <&cru PCLK_EFUSE>;
|
||||
clock-names = "pclk_efuse";
|
||||
|
||||
cpu_leakage: cpu_leakage {
|
||||
reg = <0x17 0x1>;
|
||||
};
|
||||
};
|
||||
|
||||
timer@20038000 {
|
||||
compatible = "snps,dw-apb-timer-osc";
|
||||
reg = <0x20038000 0x100>;
|
||||
|
|
|
|||
|
|
@ -146,6 +146,19 @@
|
|||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
efuse: efuse@20010000 {
|
||||
compatible = "rockchip,rockchip-efuse";
|
||||
reg = <0x20010000 0x4000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
clocks = <&cru PCLK_EFUSE>;
|
||||
clock-names = "pclk_efuse";
|
||||
|
||||
cpu_leakage: cpu_leakage {
|
||||
reg = <0x17 0x1>;
|
||||
};
|
||||
};
|
||||
|
||||
usbphy: phy {
|
||||
compatible = "rockchip,rk3188-usb-phy", "rockchip,rk3288-usb-phy";
|
||||
rockchip,grf = <&grf>;
|
||||
|
|
|
|||
|
|
@ -0,0 +1,66 @@
|
|||
/*
|
||||
* This file is dual-licensed: you can use it either under the terms
|
||||
* of the GPL or the X11 license, at your option. Note that this dual
|
||||
* licensing only applies to this file, and not this project as a
|
||||
* whole.
|
||||
*
|
||||
* a) This file is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of the
|
||||
* License, or (at your option) any later version.
|
||||
*
|
||||
* This file is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* Or, alternatively,
|
||||
*
|
||||
* b) Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use,
|
||||
* copy, modify, merge, publish, distribute, sublicense, and/or
|
||||
* sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following
|
||||
* conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "rk3228.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Rockchip RK3228 Evaluation board";
|
||||
compatible = "rockchip,rk3228-evb", "rockchip,rk3228";
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x60000000 0x40000000>;
|
||||
};
|
||||
};
|
||||
|
||||
&emmc {
|
||||
broken-cd;
|
||||
cap-mmc-highspeed;
|
||||
mmc-ddr-1_8v;
|
||||
disable-wp;
|
||||
non-removable;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -0,0 +1,442 @@
|
|||
/*
|
||||
* This file is dual-licensed: you can use it either under the terms
|
||||
* of the GPL or the X11 license, at your option. Note that this dual
|
||||
* licensing only applies to this file, and not this project as a
|
||||
* whole.
|
||||
*
|
||||
* a) This file is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of the
|
||||
* License, or (at your option) any later version.
|
||||
*
|
||||
* This file is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* Or, alternatively,
|
||||
*
|
||||
* b) Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use,
|
||||
* copy, modify, merge, publish, distribute, sublicense, and/or
|
||||
* sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following
|
||||
* conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/pinctrl/rockchip.h>
|
||||
#include <dt-bindings/clock/rk3228-cru.h>
|
||||
#include "skeleton.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "rockchip,rk3228";
|
||||
|
||||
interrupt-parent = <&gic>;
|
||||
|
||||
aliases {
|
||||
serial0 = &uart0;
|
||||
serial1 = &uart1;
|
||||
serial2 = &uart2;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu0: cpu@f00 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a7";
|
||||
reg = <0xf00>;
|
||||
resets = <&cru SRST_CORE0>;
|
||||
operating-points = <
|
||||
/* KHz uV */
|
||||
816000 1000000
|
||||
>;
|
||||
clock-latency = <40000>;
|
||||
clocks = <&cru ARMCLK>;
|
||||
};
|
||||
|
||||
cpu1: cpu@f01 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a7";
|
||||
reg = <0xf01>;
|
||||
resets = <&cru SRST_CORE1>;
|
||||
};
|
||||
|
||||
cpu2: cpu@f02 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a7";
|
||||
reg = <0xf02>;
|
||||
resets = <&cru SRST_CORE2>;
|
||||
};
|
||||
|
||||
cpu3: cpu@f03 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a7";
|
||||
reg = <0xf03>;
|
||||
resets = <&cru SRST_CORE3>;
|
||||
};
|
||||
};
|
||||
|
||||
amba {
|
||||
compatible = "arm,amba-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
pdma: pdma@110f0000 {
|
||||
compatible = "arm,pl330", "arm,primecell";
|
||||
reg = <0x110f0000 0x4000>;
|
||||
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#dma-cells = <1>;
|
||||
clocks = <&cru ACLK_DMAC>;
|
||||
clock-names = "apb_pclk";
|
||||
};
|
||||
};
|
||||
|
||||
arm-pmu {
|
||||
compatible = "arm,cortex-a7-pmu";
|
||||
interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
|
||||
};
|
||||
|
||||
timer {
|
||||
compatible = "arm,armv7-timer";
|
||||
arm,cpu-registers-not-fw-configured;
|
||||
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
|
||||
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
|
||||
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
|
||||
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
|
||||
clock-frequency = <24000000>;
|
||||
};
|
||||
|
||||
xin24m: oscillator {
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <24000000>;
|
||||
clock-output-names = "xin24m";
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
|
||||
grf: syscon@11000000 {
|
||||
compatible = "syscon";
|
||||
reg = <0x11000000 0x1000>;
|
||||
};
|
||||
|
||||
uart0: serial@11010000 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0x11010000 0x100>;
|
||||
interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-frequency = <24000000>;
|
||||
clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
|
||||
clock-names = "baudclk", "apb_pclk";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart1: serial@11020000 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0x11020000 0x100>;
|
||||
interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-frequency = <24000000>;
|
||||
clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
|
||||
clock-names = "baudclk", "apb_pclk";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart1_xfer>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart2: serial@11030000 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0x11030000 0x100>;
|
||||
interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-frequency = <24000000>;
|
||||
clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
|
||||
clock-names = "baudclk", "apb_pclk";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart2_xfer>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pwm0: pwm@110b0000 {
|
||||
compatible = "rockchip,rk3288-pwm";
|
||||
reg = <0x110b0000 0x10>;
|
||||
#pwm-cells = <3>;
|
||||
clocks = <&cru PCLK_PWM>;
|
||||
clock-names = "pwm";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pwm0_pin>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pwm1: pwm@110b0010 {
|
||||
compatible = "rockchip,rk3288-pwm";
|
||||
reg = <0x110b0010 0x10>;
|
||||
#pwm-cells = <3>;
|
||||
clocks = <&cru PCLK_PWM>;
|
||||
clock-names = "pwm";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pwm1_pin>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pwm2: pwm@110b0020 {
|
||||
compatible = "rockchip,rk3288-pwm";
|
||||
reg = <0x110b0020 0x10>;
|
||||
#pwm-cells = <3>;
|
||||
clocks = <&cru PCLK_PWM>;
|
||||
clock-names = "pwm";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pwm2_pin>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pwm3: pwm@110b0030 {
|
||||
compatible = "rockchip,rk3288-pwm";
|
||||
reg = <0x110b0030 0x10>;
|
||||
#pwm-cells = <2>;
|
||||
clocks = <&cru PCLK_PWM>;
|
||||
clock-names = "pwm";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pwm3_pin>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
timer: timer@110c0000 {
|
||||
compatible = "rockchip,rk3288-timer";
|
||||
reg = <0x110c0000 0x20>;
|
||||
interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&xin24m>, <&cru PCLK_TIMER>;
|
||||
clock-names = "timer", "pclk";
|
||||
};
|
||||
|
||||
cru: clock-controller@110e0000 {
|
||||
compatible = "rockchip,rk3228-cru";
|
||||
reg = <0x110e0000 0x1000>;
|
||||
rockchip,grf = <&grf>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
assigned-clocks = <&cru PLL_GPLL>;
|
||||
assigned-clock-rates = <594000000>;
|
||||
};
|
||||
|
||||
emmc: dwmmc@30020000 {
|
||||
compatible = "rockchip,rk3288-dw-mshc";
|
||||
reg = <0x30020000 0x4000>;
|
||||
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-frequency = <37500000>;
|
||||
clock-freq-min-max = <400000 37500000>;
|
||||
clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
|
||||
<&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
|
||||
clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
|
||||
bus-width = <8>;
|
||||
default-sample-phase = <158>;
|
||||
num-slots = <1>;
|
||||
fifo-depth = <0x100>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gic: interrupt-controller@32010000 {
|
||||
compatible = "arm,gic-400";
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <3>;
|
||||
#address-cells = <0>;
|
||||
|
||||
reg = <0x32011000 0x1000>,
|
||||
<0x32012000 0x1000>,
|
||||
<0x32014000 0x2000>,
|
||||
<0x32016000 0x2000>;
|
||||
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
|
||||
};
|
||||
|
||||
pinctrl: pinctrl {
|
||||
compatible = "rockchip,rk3228-pinctrl";
|
||||
rockchip,grf = <&grf>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
gpio0: gpio0@11110000 {
|
||||
compatible = "rockchip,gpio-bank";
|
||||
reg = <0x11110000 0x100>;
|
||||
interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cru PCLK_GPIO0>;
|
||||
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpio1: gpio1@11120000 {
|
||||
compatible = "rockchip,gpio-bank";
|
||||
reg = <0x11120000 0x100>;
|
||||
interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cru PCLK_GPIO1>;
|
||||
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpio2: gpio2@11130000 {
|
||||
compatible = "rockchip,gpio-bank";
|
||||
reg = <0x11130000 0x100>;
|
||||
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cru PCLK_GPIO2>;
|
||||
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
gpio3: gpio3@11140000 {
|
||||
compatible = "rockchip,gpio-bank";
|
||||
reg = <0x11140000 0x100>;
|
||||
interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cru PCLK_GPIO3>;
|
||||
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
pcfg_pull_up: pcfg-pull-up {
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
pcfg_pull_down: pcfg-pull-down {
|
||||
bias-pull-down;
|
||||
};
|
||||
|
||||
pcfg_pull_none: pcfg-pull-none {
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
emmc {
|
||||
emmc_clk: emmc-clk {
|
||||
rockchip,pins = <2 7 RK_FUNC_2 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
emmc_cmd: emmc-cmd {
|
||||
rockchip,pins = <1 22 RK_FUNC_2 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
emmc_bus8: emmc-bus8 {
|
||||
rockchip,pins = <1 24 RK_FUNC_2 &pcfg_pull_none>,
|
||||
<1 25 RK_FUNC_2 &pcfg_pull_none>,
|
||||
<1 26 RK_FUNC_2 &pcfg_pull_none>,
|
||||
<1 27 RK_FUNC_2 &pcfg_pull_none>,
|
||||
<1 28 RK_FUNC_2 &pcfg_pull_none>,
|
||||
<1 29 RK_FUNC_2 &pcfg_pull_none>,
|
||||
<1 30 RK_FUNC_2 &pcfg_pull_none>,
|
||||
<1 31 RK_FUNC_2 &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
pwm0 {
|
||||
pwm0_pin: pwm0-pin {
|
||||
rockchip,pins = <3 21 RK_FUNC_1 &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
pwm1 {
|
||||
pwm1_pin: pwm1-pin {
|
||||
rockchip,pins = <0 30 RK_FUNC_2 &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
pwm2 {
|
||||
pwm2_pin: pwm2-pin {
|
||||
rockchip,pins = <1 12 RK_FUNC_2 &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
pwm3 {
|
||||
pwm3_pin: pwm3-pin {
|
||||
rockchip,pins = <1 11 RK_FUNC_2 &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
uart0 {
|
||||
uart0_xfer: uart0-xfer {
|
||||
rockchip,pins = <2 26 RK_FUNC_1 &pcfg_pull_none>,
|
||||
<2 27 RK_FUNC_1 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
uart0_cts: uart0-cts {
|
||||
rockchip,pins = <2 29 RK_FUNC_1 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
uart0_rts: uart0-rts {
|
||||
rockchip,pins = <0 17 RK_FUNC_1 &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
uart1 {
|
||||
uart1_xfer: uart1-xfer {
|
||||
rockchip,pins = <1 9 RK_FUNC_1 &pcfg_pull_none>,
|
||||
<1 10 RK_FUNC_1 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
uart1_cts: uart1-cts {
|
||||
rockchip,pins = <1 8 RK_FUNC_1 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
uart1_rts: uart1-rts {
|
||||
rockchip,pins = <1 11 RK_FUNC_1 &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
uart2 {
|
||||
uart2_xfer: uart2-xfer {
|
||||
rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_none>,
|
||||
<1 19 RK_FUNC_2 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
uart2_cts: uart2-cts {
|
||||
rockchip,pins = <0 25 RK_FUNC_1 &pcfg_pull_none>;
|
||||
};
|
||||
|
||||
uart2_rts: uart2-rts {
|
||||
rockchip,pins = <0 24 RK_FUNC_1 &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -43,10 +43,26 @@
|
|||
|
||||
/ {
|
||||
compatible = "rockchip,rk3288-evb-act8846", "rockchip,rk3288";
|
||||
|
||||
vcc_lcd: vcc-lcd {
|
||||
compatible = "regulator-fixed";
|
||||
enable-active-high;
|
||||
gpio = <&gpio7 3 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&lcd_en>;
|
||||
regulator-name = "vcc_lcd";
|
||||
vin-supply = <&vcc_io>;
|
||||
};
|
||||
|
||||
&cpu0 {
|
||||
cpu0-supply = <&vdd_cpu>;
|
||||
vcc_wl: vcc-wl {
|
||||
compatible = "regulator-fixed";
|
||||
enable-active-high;
|
||||
gpio = <&gpio7 9 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&wifi_pwr>;
|
||||
regulator-name = "vcc_wl";
|
||||
vin-supply = <&vcc_18>;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
|
|
@ -119,8 +135,8 @@
|
|||
|
||||
vdd_log: REG3 {
|
||||
regulator-name = "VDD_LOG";
|
||||
regulator-min-microvolt = <1000000>;
|
||||
regulator-max-microvolt = <1000000>;
|
||||
regulator-min-microvolt = <700000>;
|
||||
regulator-max-microvolt = <1500000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
|
|
@ -133,7 +149,7 @@
|
|||
|
||||
vccio_sd: REG5 {
|
||||
regulator-name = "VCCIO_SD";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
|
@ -152,7 +168,7 @@
|
|||
regulator-always-on;
|
||||
};
|
||||
|
||||
vcca_tp: REG8 {
|
||||
vcc_tp: REG8 {
|
||||
regulator-name = "VCCA_TP";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
|
|
@ -189,3 +205,17 @@
|
|||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
lcd {
|
||||
lcd_en: lcd-en {
|
||||
rockchip,pins = <7 3 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
|
||||
wifi {
|
||||
wifi_pwr: wifi-pwr {
|
||||
rockchip,pins = <7 9 RK_FUNC_GPIO &pcfg_pull_none>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -43,17 +43,6 @@
|
|||
|
||||
/ {
|
||||
compatible = "rockchip,rk3288-evb-rk808", "rockchip,rk3288";
|
||||
|
||||
ext_gmac: external-gmac-clock {
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <125000000>;
|
||||
clock-output-names = "ext_gmac";
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
&cpu0 {
|
||||
cpu0-supply = <&vdd_cpu>;
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
|
|
@ -244,19 +233,3 @@
|
|||
};
|
||||
};
|
||||
};
|
||||
|
||||
&gmac {
|
||||
phy-supply = <&vcc_phy>;
|
||||
phy-mode = "rgmii";
|
||||
clock_in_out = "input";
|
||||
snps,reset-gpio = <&gpio4 7 0>;
|
||||
snps,reset-active-low;
|
||||
snps,reset-delays-us = <0 10000 1000000>;
|
||||
assigned-clocks = <&cru SCLK_MAC>;
|
||||
assigned-clock-parents = <&ext_gmac>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&rgmii_pins>;
|
||||
tx_delay = <0x30>;
|
||||
rx_delay = <0x10>;
|
||||
status = "ok";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -89,6 +89,13 @@
|
|||
pwms = <&pwm0 0 1000000 PWM_POLARITY_INVERTED>;
|
||||
};
|
||||
|
||||
ext_gmac: external-gmac-clock {
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <125000000>;
|
||||
clock-output-names = "ext_gmac";
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
|
||||
gpio-keys {
|
||||
compatible = "gpio-keys";
|
||||
#address-cells = <1>;
|
||||
|
|
@ -160,6 +167,10 @@
|
|||
};
|
||||
};
|
||||
|
||||
&cpu0 {
|
||||
cpu0-supply = <&vdd_cpu>;
|
||||
};
|
||||
|
||||
&emmc {
|
||||
broken-cd;
|
||||
bus-width = <8>;
|
||||
|
|
@ -172,11 +183,6 @@
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
&hdmi {
|
||||
ddc-i2c-bus = <&i2c5>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdmmc {
|
||||
bus-width = <4>;
|
||||
cap-mmc-highspeed;
|
||||
|
|
@ -191,6 +197,27 @@
|
|||
vqmmc-supply = <&vccio_sd>;
|
||||
};
|
||||
|
||||
&gmac {
|
||||
phy-supply = <&vcc_phy>;
|
||||
phy-mode = "rgmii";
|
||||
clock_in_out = "input";
|
||||
snps,reset-gpio = <&gpio4 7 0>;
|
||||
snps,reset-active-low;
|
||||
snps,reset-delays-us = <0 10000 1000000>;
|
||||
assigned-clocks = <&cru SCLK_MAC>;
|
||||
assigned-clock-parents = <&ext_gmac>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&rgmii_pins>;
|
||||
tx_delay = <0x30>;
|
||||
rx_delay = <0x10>;
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
&hdmi {
|
||||
ddc-i2c-bus = <&i2c5>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
|
|||
|
|
@ -901,6 +901,19 @@
|
|||
interrupts = <GIC_PPI 9 0xf04>;
|
||||
};
|
||||
|
||||
efuse: efuse@ffb40000 {
|
||||
compatible = "rockchip,rockchip-efuse";
|
||||
reg = <0xffb40000 0x20>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
clocks = <&cru PCLK_EFUSE256>;
|
||||
clock-names = "pclk_efuse";
|
||||
|
||||
cpu_leakage: cpu_leakage@17 {
|
||||
reg = <0x17 0x1>;
|
||||
};
|
||||
};
|
||||
|
||||
usbphy: phy {
|
||||
compatible = "rockchip,rk3288-usb-phy";
|
||||
rockchip,grf = <&grf>;
|
||||
|
|
@ -1159,7 +1172,7 @@
|
|||
rockchip,pins = <6 21 RK_FUNC_1 &pcfg_pull_up>;
|
||||
};
|
||||
|
||||
sdmmc_cd: sdmcc-cd {
|
||||
sdmmc_cd: sdmmc-cd {
|
||||
rockchip,pins = <6 22 RK_FUNC_1 &pcfg_pull_up>;
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -0,0 +1,220 @@
|
|||
/*
|
||||
* Copyright (c) 2015 Rockchip Electronics Co. Ltd.
|
||||
* Author: Jeffy Chen <jeffy.chen@rock-chips.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3228_H
|
||||
#define _DT_BINDINGS_CLK_ROCKCHIP_RK3228_H
|
||||
|
||||
/* core clocks */
|
||||
#define PLL_APLL 1
|
||||
#define PLL_DPLL 2
|
||||
#define PLL_CPLL 3
|
||||
#define PLL_GPLL 4
|
||||
#define ARMCLK 5
|
||||
|
||||
/* sclk gates (special clocks) */
|
||||
#define SCLK_SPI0 65
|
||||
#define SCLK_NANDC 67
|
||||
#define SCLK_SDMMC 68
|
||||
#define SCLK_SDIO 69
|
||||
#define SCLK_EMMC 71
|
||||
#define SCLK_UART0 77
|
||||
#define SCLK_UART1 78
|
||||
#define SCLK_UART2 79
|
||||
#define SCLK_I2S0 80
|
||||
#define SCLK_I2S1 81
|
||||
#define SCLK_I2S2 82
|
||||
#define SCLK_SPDIF 83
|
||||
#define SCLK_TIMER0 85
|
||||
#define SCLK_TIMER1 86
|
||||
#define SCLK_TIMER2 87
|
||||
#define SCLK_TIMER3 88
|
||||
#define SCLK_TIMER4 89
|
||||
#define SCLK_TIMER5 90
|
||||
#define SCLK_I2S_OUT 113
|
||||
#define SCLK_SDMMC_DRV 114
|
||||
#define SCLK_SDIO_DRV 115
|
||||
#define SCLK_EMMC_DRV 117
|
||||
#define SCLK_SDMMC_SAMPLE 118
|
||||
#define SCLK_SDIO_SAMPLE 119
|
||||
#define SCLK_EMMC_SAMPLE 121
|
||||
|
||||
/* aclk gates */
|
||||
#define ACLK_DMAC 194
|
||||
#define ACLK_PERI 210
|
||||
|
||||
/* pclk gates */
|
||||
#define PCLK_GPIO0 320
|
||||
#define PCLK_GPIO1 321
|
||||
#define PCLK_GPIO2 322
|
||||
#define PCLK_GPIO3 323
|
||||
#define PCLK_GRF 329
|
||||
#define PCLK_I2C0 332
|
||||
#define PCLK_I2C1 333
|
||||
#define PCLK_I2C2 334
|
||||
#define PCLK_I2C3 335
|
||||
#define PCLK_SPI0 338
|
||||
#define PCLK_UART0 341
|
||||
#define PCLK_UART1 342
|
||||
#define PCLK_UART2 343
|
||||
#define PCLK_PWM 350
|
||||
#define PCLK_TIMER 353
|
||||
#define PCLK_PERI 363
|
||||
|
||||
/* hclk gates */
|
||||
#define HCLK_NANDC 453
|
||||
#define HCLK_SDMMC 456
|
||||
#define HCLK_SDIO 457
|
||||
#define HCLK_EMMC 459
|
||||
#define HCLK_PERI 478
|
||||
|
||||
#define CLK_NR_CLKS (HCLK_PERI + 1)
|
||||
|
||||
/* soft-reset indices */
|
||||
#define SRST_CORE0_PO 0
|
||||
#define SRST_CORE1_PO 1
|
||||
#define SRST_CORE2_PO 2
|
||||
#define SRST_CORE3_PO 3
|
||||
#define SRST_CORE0 4
|
||||
#define SRST_CORE1 5
|
||||
#define SRST_CORE2 6
|
||||
#define SRST_CORE3 7
|
||||
#define SRST_CORE0_DBG 8
|
||||
#define SRST_CORE1_DBG 9
|
||||
#define SRST_CORE2_DBG 10
|
||||
#define SRST_CORE3_DBG 11
|
||||
#define SRST_TOPDBG 12
|
||||
#define SRST_ACLK_CORE 13
|
||||
#define SRST_NOC 14
|
||||
#define SRST_L2C 15
|
||||
|
||||
#define SRST_CPUSYS_H 18
|
||||
#define SRST_BUSSYS_H 19
|
||||
#define SRST_SPDIF 20
|
||||
#define SRST_INTMEM 21
|
||||
#define SRST_ROM 22
|
||||
#define SRST_OTG_ADP 23
|
||||
#define SRST_I2S0 24
|
||||
#define SRST_I2S1 25
|
||||
#define SRST_I2S2 26
|
||||
#define SRST_ACODEC_P 27
|
||||
#define SRST_DFIMON 28
|
||||
#define SRST_MSCH 29
|
||||
#define SRST_EFUSE1024 30
|
||||
#define SRST_EFUSE256 31
|
||||
|
||||
#define SRST_GPIO0 32
|
||||
#define SRST_GPIO1 33
|
||||
#define SRST_GPIO2 34
|
||||
#define SRST_GPIO3 35
|
||||
#define SRST_PERIPH_NOC_A 36
|
||||
#define SRST_PERIPH_NOC_BUS_H 37
|
||||
#define SRST_PERIPH_NOC_P 38
|
||||
#define SRST_UART0 39
|
||||
#define SRST_UART1 40
|
||||
#define SRST_UART2 41
|
||||
#define SRST_PHYNOC 42
|
||||
#define SRST_I2C0 43
|
||||
#define SRST_I2C1 44
|
||||
#define SRST_I2C2 45
|
||||
#define SRST_I2C3 46
|
||||
|
||||
#define SRST_PWM 48
|
||||
#define SRST_A53_GIC 49
|
||||
#define SRST_DAP 51
|
||||
#define SRST_DAP_NOC 52
|
||||
#define SRST_CRYPTO 53
|
||||
#define SRST_SGRF 54
|
||||
#define SRST_GRF 55
|
||||
#define SRST_GMAC 56
|
||||
#define SRST_PERIPH_NOC_H 58
|
||||
#define SRST_MACPHY 63
|
||||
|
||||
#define SRST_DMA 64
|
||||
#define SRST_NANDC 68
|
||||
#define SRST_USBOTG 69
|
||||
#define SRST_OTGC 70
|
||||
#define SRST_USBHOST0 71
|
||||
#define SRST_HOST_CTRL0 72
|
||||
#define SRST_USBHOST1 73
|
||||
#define SRST_HOST_CTRL1 74
|
||||
#define SRST_USBHOST2 75
|
||||
#define SRST_HOST_CTRL2 76
|
||||
#define SRST_USBPOR0 77
|
||||
#define SRST_USBPOR1 78
|
||||
#define SRST_DDRMSCH 79
|
||||
|
||||
#define SRST_SMART_CARD 80
|
||||
#define SRST_SDMMC 81
|
||||
#define SRST_SDIO 82
|
||||
#define SRST_EMMC 83
|
||||
#define SRST_SPI 84
|
||||
#define SRST_TSP_H 85
|
||||
#define SRST_TSP 86
|
||||
#define SRST_TSADC 87
|
||||
#define SRST_DDRPHY 88
|
||||
#define SRST_DDRPHY_P 89
|
||||
#define SRST_DDRCTRL 90
|
||||
#define SRST_DDRCTRL_P 91
|
||||
#define SRST_HOST0_ECHI 92
|
||||
#define SRST_HOST1_ECHI 93
|
||||
#define SRST_HOST2_ECHI 94
|
||||
#define SRST_VOP_NOC_A 95
|
||||
|
||||
#define SRST_HDMI_P 96
|
||||
#define SRST_VIO_ARBI_H 97
|
||||
#define SRST_IEP_NOC_A 98
|
||||
#define SRST_VIO_NOC_H 99
|
||||
#define SRST_VOP_A 100
|
||||
#define SRST_VOP_H 101
|
||||
#define SRST_VOP_D 102
|
||||
#define SRST_UTMI0 103
|
||||
#define SRST_UTMI1 104
|
||||
#define SRST_UTMI2 105
|
||||
#define SRST_UTMI3 106
|
||||
#define SRST_RGA 107
|
||||
#define SRST_RGA_NOC_A 108
|
||||
#define SRST_RGA_A 109
|
||||
#define SRST_RGA_H 110
|
||||
#define SRST_HDCP_A 111
|
||||
|
||||
#define SRST_VPU_A 112
|
||||
#define SRST_VPU_H 113
|
||||
#define SRST_VPU_NOC_A 116
|
||||
#define SRST_VPU_NOC_H 117
|
||||
#define SRST_RKVDEC_A 118
|
||||
#define SRST_RKVDEC_NOC_A 119
|
||||
#define SRST_RKVDEC_H 120
|
||||
#define SRST_RKVDEC_NOC_H 121
|
||||
#define SRST_RKVDEC_CORE 122
|
||||
#define SRST_RKVDEC_CABAC 123
|
||||
#define SRST_IEP_A 124
|
||||
#define SRST_IEP_H 125
|
||||
#define SRST_GPU_A 126
|
||||
#define SRST_GPU_NOC_A 127
|
||||
|
||||
#define SRST_CORE_DBG 128
|
||||
#define SRST_DBG_P 129
|
||||
#define SRST_TIMER0 130
|
||||
#define SRST_TIMER1 131
|
||||
#define SRST_TIMER2 132
|
||||
#define SRST_TIMER3 133
|
||||
#define SRST_TIMER4 134
|
||||
#define SRST_TIMER5 135
|
||||
#define SRST_VIO_H2P 136
|
||||
#define SRST_HDMIPHY 139
|
||||
#define SRST_VDAC 140
|
||||
#define SRST_TIMER_6CH_P 141
|
||||
|
||||
#endif
|
||||
|
|
@ -87,6 +87,7 @@
|
|||
#define SCLK_PVTM_CORE 123
|
||||
#define SCLK_PVTM_GPU 124
|
||||
#define SCLK_CRYPTO 125
|
||||
#define SCLK_MIPIDSI_24M 126
|
||||
|
||||
#define SCLK_MAC 151
|
||||
#define SCLK_MACREF_OUT 152
|
||||
|
|
@ -165,6 +166,8 @@
|
|||
#define PCLK_DDRUPCTL1 366
|
||||
#define PCLK_PUBL1 367
|
||||
#define PCLK_WDT 368
|
||||
#define PCLK_EFUSE256 369
|
||||
#define PCLK_EFUSE1024 370
|
||||
|
||||
/* hclk gates */
|
||||
#define HCLK_GPS 448
|
||||
|
|
|
|||
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