MIPS: Emulate the new MIPS R6 branch compact (BC) instruction
MIPS R6 uses the <R6 LWC2 opcode for the new BC instruction. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
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f1b44067c1
Коммит
8467ca0122
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@ -31,7 +31,7 @@ enum major_op {
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lbu_op, lhu_op, lwr_op, lwu_op,
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lbu_op, lhu_op, lwr_op, lwu_op,
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sb_op, sh_op, swl_op, sw_op,
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sb_op, sh_op, swl_op, sw_op,
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sdl_op, sdr_op, swr_op, cache_op,
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sdl_op, sdr_op, swr_op, cache_op,
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ll_op, lwc1_op, lwc2_op, pref_op,
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ll_op, lwc1_op, lwc2_op, bc6_op = lwc2_op, pref_op,
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lld_op, ldc1_op, ldc2_op, ld_op,
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lld_op, ldc1_op, ldc2_op, ld_op,
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sc_op, swc1_op, swc2_op, major_3b_op,
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sc_op, swc1_op, swc2_op, major_3b_op,
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scd_op, sdc1_op, sdc2_op, sd_op
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scd_op, sdc1_op, sdc2_op, sd_op
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@ -780,6 +780,15 @@ int __compute_return_epc_for_insn(struct pt_regs *regs,
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epc += 8;
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epc += 8;
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regs->cp0_epc = epc;
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regs->cp0_epc = epc;
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break;
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break;
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#else
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case bc6_op:
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/* Only valid for MIPS R6 */
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if (!cpu_has_mips_r6) {
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ret = -SIGILL;
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break;
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}
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regs->cp0_epc += 8;
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break;
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#endif
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#endif
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}
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}
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@ -648,6 +648,19 @@ static int isBranchInstr(struct pt_regs *regs, struct mm_decoded_insn dec_insn,
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else
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else
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*contpc = regs->cp0_epc + 8;
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*contpc = regs->cp0_epc + 8;
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return 1;
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return 1;
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#else
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case bc6_op:
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/*
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* Only valid for MIPS R6 but we can still end up
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* here from a broken userland so just tell emulator
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* this is not a branch and let it break later on.
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*/
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if (!cpu_has_mips_r6)
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break;
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*contpc = regs->cp0_epc + dec_insn.pc_inc +
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dec_insn.next_pc_inc;
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return 1;
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#endif
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#endif
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case cop0_op:
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case cop0_op:
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case cop1_op:
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case cop1_op:
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