Merge branch 'timers-for-linus-hpet' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip
* 'timers-for-linus-hpet' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip: x86: hpet: Make WARN_ON understandable x86: arch specific support for remapping HPET MSIs intr-remap: generic support for remapping HPET MSIs x86, hpet: Simplify the HPET code x86, hpet: Disable per-cpu hpet timer if ARAT is supported
This commit is contained in:
Linus Torvalds
Коммит
849e8dea09
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@ -65,11 +65,12 @@
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/* hpet memory map physical address */
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extern unsigned long hpet_address;
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extern unsigned long force_hpet_address;
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extern u8 hpet_blockid;
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extern int hpet_force_user;
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extern int is_hpet_enabled(void);
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extern int hpet_enable(void);
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extern void hpet_disable(void);
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extern unsigned long hpet_readl(unsigned long a);
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extern unsigned int hpet_readl(unsigned int a);
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extern void force_hpet_resume(void);
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extern void hpet_msi_unmask(unsigned int irq);
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@ -78,9 +79,9 @@ extern void hpet_msi_write(unsigned int irq, struct msi_msg *msg);
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extern void hpet_msi_read(unsigned int irq, struct msi_msg *msg);
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#ifdef CONFIG_PCI_MSI
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extern int arch_setup_hpet_msi(unsigned int irq);
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extern int arch_setup_hpet_msi(unsigned int irq, unsigned int id);
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#else
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static inline int arch_setup_hpet_msi(unsigned int irq)
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static inline int arch_setup_hpet_msi(unsigned int irq, unsigned int id)
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{
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return -EINVAL;
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}
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@ -624,6 +624,7 @@ static int __init acpi_parse_hpet(struct acpi_table_header *table)
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}
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hpet_address = hpet_tbl->address.address;
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hpet_blockid = hpet_tbl->sequence;
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/*
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* Some broken BIOSes advertise HPET at 0x0. We really do not
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@ -3267,7 +3267,8 @@ void destroy_irq(unsigned int irq)
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* MSI message composition
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*/
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#ifdef CONFIG_PCI_MSI
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static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, struct msi_msg *msg)
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static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq,
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struct msi_msg *msg, u8 hpet_id)
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{
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struct irq_cfg *cfg;
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int err;
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@ -3301,7 +3302,10 @@ static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, struct msi_ms
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irte.dest_id = IRTE_DEST(dest);
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/* Set source-id of interrupt request */
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set_msi_sid(&irte, pdev);
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if (pdev)
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set_msi_sid(&irte, pdev);
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else
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set_hpet_sid(&irte, hpet_id);
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modify_irte(irq, &irte);
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@ -3466,7 +3470,7 @@ static int setup_msi_irq(struct pci_dev *dev, struct msi_desc *msidesc, int irq)
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int ret;
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struct msi_msg msg;
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ret = msi_compose_msg(dev, irq, &msg);
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ret = msi_compose_msg(dev, irq, &msg, -1);
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if (ret < 0)
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return ret;
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@ -3599,7 +3603,7 @@ int arch_setup_dmar_msi(unsigned int irq)
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int ret;
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struct msi_msg msg;
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ret = msi_compose_msg(NULL, irq, &msg);
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ret = msi_compose_msg(NULL, irq, &msg, -1);
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if (ret < 0)
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return ret;
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dmar_msi_write(irq, &msg);
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@ -3639,6 +3643,19 @@ static int hpet_msi_set_affinity(unsigned int irq, const struct cpumask *mask)
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#endif /* CONFIG_SMP */
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static struct irq_chip ir_hpet_msi_type = {
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.name = "IR-HPET_MSI",
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.unmask = hpet_msi_unmask,
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.mask = hpet_msi_mask,
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#ifdef CONFIG_INTR_REMAP
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.ack = ir_ack_apic_edge,
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#ifdef CONFIG_SMP
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.set_affinity = ir_set_msi_irq_affinity,
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#endif
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#endif
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.retrigger = ioapic_retrigger_irq,
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};
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static struct irq_chip hpet_msi_type = {
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.name = "HPET_MSI",
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.unmask = hpet_msi_unmask,
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@ -3650,20 +3667,36 @@ static struct irq_chip hpet_msi_type = {
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.retrigger = ioapic_retrigger_irq,
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};
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int arch_setup_hpet_msi(unsigned int irq)
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int arch_setup_hpet_msi(unsigned int irq, unsigned int id)
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{
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int ret;
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struct msi_msg msg;
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struct irq_desc *desc = irq_to_desc(irq);
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ret = msi_compose_msg(NULL, irq, &msg);
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if (intr_remapping_enabled) {
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struct intel_iommu *iommu = map_hpet_to_ir(id);
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int index;
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if (!iommu)
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return -1;
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index = alloc_irte(iommu, irq, 1);
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if (index < 0)
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return -1;
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}
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ret = msi_compose_msg(NULL, irq, &msg, id);
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if (ret < 0)
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return ret;
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hpet_msi_write(irq, &msg);
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desc->status |= IRQ_MOVE_PCNTXT;
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set_irq_chip_and_handler_name(irq, &hpet_msi_type, handle_edge_irq,
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"edge");
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if (irq_remapped(irq))
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set_irq_chip_and_handler_name(irq, &ir_hpet_msi_type,
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handle_edge_irq, "edge");
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else
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set_irq_chip_and_handler_name(irq, &hpet_msi_type,
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handle_edge_irq, "edge");
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return 0;
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}
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@ -33,6 +33,7 @@
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* HPET address is set in acpi/boot.c, when an ACPI entry exists
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*/
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unsigned long hpet_address;
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u8 hpet_blockid; /* OS timer block num */
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#ifdef CONFIG_PCI_MSI
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static unsigned long hpet_num_timers;
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#endif
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@ -47,12 +48,12 @@ struct hpet_dev {
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char name[10];
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};
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unsigned long hpet_readl(unsigned long a)
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inline unsigned int hpet_readl(unsigned int a)
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{
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return readl(hpet_virt_address + a);
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}
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static inline void hpet_writel(unsigned long d, unsigned long a)
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static inline void hpet_writel(unsigned int d, unsigned int a)
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{
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writel(d, hpet_virt_address + a);
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}
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@ -167,7 +168,7 @@ do { \
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static void hpet_reserve_msi_timers(struct hpet_data *hd);
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static void hpet_reserve_platform_timers(unsigned long id)
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static void hpet_reserve_platform_timers(unsigned int id)
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{
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struct hpet __iomem *hpet = hpet_virt_address;
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struct hpet_timer __iomem *timer = &hpet->hpet_timers[2];
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@ -205,7 +206,7 @@ static void hpet_reserve_platform_timers(unsigned long id)
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}
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#else
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static void hpet_reserve_platform_timers(unsigned long id) { }
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static void hpet_reserve_platform_timers(unsigned int id) { }
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#endif
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/*
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@ -246,7 +247,7 @@ static void hpet_reset_counter(void)
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static void hpet_start_counter(void)
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{
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unsigned long cfg = hpet_readl(HPET_CFG);
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unsigned int cfg = hpet_readl(HPET_CFG);
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cfg |= HPET_CFG_ENABLE;
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hpet_writel(cfg, HPET_CFG);
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}
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@ -271,7 +272,7 @@ static void hpet_resume_counter(void)
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static void hpet_enable_legacy_int(void)
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{
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unsigned long cfg = hpet_readl(HPET_CFG);
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unsigned int cfg = hpet_readl(HPET_CFG);
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cfg |= HPET_CFG_LEGACY;
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hpet_writel(cfg, HPET_CFG);
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@ -314,7 +315,7 @@ static int hpet_setup_msi_irq(unsigned int irq);
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static void hpet_set_mode(enum clock_event_mode mode,
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struct clock_event_device *evt, int timer)
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{
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unsigned long cfg, cmp, now;
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unsigned int cfg, cmp, now;
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uint64_t delta;
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switch (mode) {
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@ -323,7 +324,7 @@ static void hpet_set_mode(enum clock_event_mode mode,
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delta = ((uint64_t)(NSEC_PER_SEC/HZ)) * evt->mult;
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delta >>= evt->shift;
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now = hpet_readl(HPET_COUNTER);
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cmp = now + (unsigned long) delta;
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cmp = now + (unsigned int) delta;
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cfg = hpet_readl(HPET_Tn_CFG(timer));
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/* Make sure we use edge triggered interrupts */
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cfg &= ~HPET_TN_LEVEL;
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@ -339,7 +340,7 @@ static void hpet_set_mode(enum clock_event_mode mode,
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* (See AMD-8111 HyperTransport I/O Hub Data Sheet,
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* Publication # 24674)
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*/
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hpet_writel((unsigned long) delta, HPET_Tn_CMP(timer));
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hpet_writel((unsigned int) delta, HPET_Tn_CMP(timer));
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hpet_start_counter();
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hpet_print_config();
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break;
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@ -383,13 +384,24 @@ static int hpet_next_event(unsigned long delta,
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hpet_writel(cnt, HPET_Tn_CMP(timer));
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/*
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* We need to read back the CMP register to make sure that
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* what we wrote hit the chip before we compare it to the
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* counter.
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* We need to read back the CMP register on certain HPET
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* implementations (ATI chipsets) which seem to delay the
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* transfer of the compare register into the internal compare
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* logic. With small deltas this might actually be too late as
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* the counter could already be higher than the compare value
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* at that point and we would wait for the next hpet interrupt
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* forever. We found out that reading the CMP register back
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* forces the transfer so we can rely on the comparison with
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* the counter register below. If the read back from the
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* compare register does not match the value we programmed
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* then we might have a real hardware problem. We can not do
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* much about it here, but at least alert the user/admin with
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* a prominent warning.
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*/
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WARN_ON_ONCE((u32)hpet_readl(HPET_Tn_CMP(timer)) != cnt);
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WARN_ONCE(hpet_readl(HPET_Tn_CMP(timer)) != cnt,
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KERN_WARNING "hpet: compare register read back failed.\n");
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return (s32)((u32)hpet_readl(HPET_COUNTER) - cnt) >= 0 ? -ETIME : 0;
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return (s32)(hpet_readl(HPET_COUNTER) - cnt) >= 0 ? -ETIME : 0;
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}
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static void hpet_legacy_set_mode(enum clock_event_mode mode,
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@ -415,7 +427,7 @@ static struct hpet_dev *hpet_devs;
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void hpet_msi_unmask(unsigned int irq)
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{
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struct hpet_dev *hdev = get_irq_data(irq);
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unsigned long cfg;
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unsigned int cfg;
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/* unmask it */
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cfg = hpet_readl(HPET_Tn_CFG(hdev->num));
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@ -425,7 +437,7 @@ void hpet_msi_unmask(unsigned int irq)
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void hpet_msi_mask(unsigned int irq)
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{
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unsigned long cfg;
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unsigned int cfg;
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struct hpet_dev *hdev = get_irq_data(irq);
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/* mask it */
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@ -467,7 +479,7 @@ static int hpet_msi_next_event(unsigned long delta,
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static int hpet_setup_msi_irq(unsigned int irq)
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{
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if (arch_setup_hpet_msi(irq)) {
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if (arch_setup_hpet_msi(irq, hpet_blockid)) {
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destroy_irq(irq);
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return -EINVAL;
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}
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@ -584,6 +596,8 @@ static void hpet_msi_capability_lookup(unsigned int start_timer)
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unsigned int num_timers_used = 0;
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int i;
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if (boot_cpu_has(X86_FEATURE_ARAT))
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return;
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id = hpet_readl(HPET_ID);
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num_timers = ((id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT);
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@ -598,7 +612,7 @@ static void hpet_msi_capability_lookup(unsigned int start_timer)
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for (i = start_timer; i < num_timers - RESERVE_TIMERS; i++) {
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struct hpet_dev *hdev = &hpet_devs[num_timers_used];
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unsigned long cfg = hpet_readl(HPET_Tn_CFG(i));
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unsigned int cfg = hpet_readl(HPET_Tn_CFG(i));
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/* Only consider HPET timer with MSI support */
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if (!(cfg & HPET_TN_FSB_CAP))
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@ -813,7 +827,7 @@ static int hpet_clocksource_register(void)
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*/
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int __init hpet_enable(void)
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{
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unsigned long id;
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unsigned int id;
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int i;
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if (!is_hpet_capable())
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@ -872,10 +886,8 @@ int __init hpet_enable(void)
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if (id & HPET_ID_LEGSUP) {
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hpet_legacy_clockevent_register();
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hpet_msi_capability_lookup(2);
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return 1;
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}
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hpet_msi_capability_lookup(0);
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return 0;
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out_nohpet:
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@ -908,9 +920,17 @@ static __init int hpet_late_init(void)
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if (!hpet_virt_address)
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return -ENODEV;
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if (hpet_readl(HPET_ID) & HPET_ID_LEGSUP)
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hpet_msi_capability_lookup(2);
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else
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hpet_msi_capability_lookup(0);
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hpet_reserve_platform_timers(hpet_readl(HPET_ID));
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hpet_print_config();
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if (boot_cpu_has(X86_FEATURE_ARAT))
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return 0;
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for_each_online_cpu(cpu) {
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hpet_cpuhp_notify(NULL, CPU_ONLINE, (void *)(long)cpu);
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}
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@ -925,7 +945,7 @@ fs_initcall(hpet_late_init);
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void hpet_disable(void)
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{
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if (is_hpet_capable()) {
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unsigned long cfg = hpet_readl(HPET_CFG);
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unsigned int cfg = hpet_readl(HPET_CFG);
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if (hpet_legacy_int_enabled) {
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cfg &= ~HPET_CFG_LEGACY;
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@ -965,8 +985,8 @@ static int hpet_prev_update_sec;
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static struct rtc_time hpet_alarm_time;
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static unsigned long hpet_pie_count;
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static u32 hpet_t1_cmp;
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static unsigned long hpet_default_delta;
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static unsigned long hpet_pie_delta;
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static u32 hpet_default_delta;
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static u32 hpet_pie_delta;
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static unsigned long hpet_pie_limit;
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static rtc_irq_handler irq_handler;
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@ -1017,7 +1037,8 @@ EXPORT_SYMBOL_GPL(hpet_unregister_irq_handler);
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*/
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int hpet_rtc_timer_init(void)
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{
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unsigned long cfg, cnt, delta, flags;
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unsigned int cfg, cnt, delta;
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unsigned long flags;
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if (!is_hpet_enabled())
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return 0;
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@ -1027,7 +1048,7 @@ int hpet_rtc_timer_init(void)
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clc = (uint64_t) hpet_clockevent.mult * NSEC_PER_SEC;
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clc >>= hpet_clockevent.shift + DEFAULT_RTC_SHIFT;
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hpet_default_delta = (unsigned long) clc;
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hpet_default_delta = clc;
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}
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if (!(hpet_rtc_flags & RTC_PIE) || hpet_pie_limit)
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@ -1113,7 +1134,7 @@ int hpet_set_periodic_freq(unsigned long freq)
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clc = (uint64_t) hpet_clockevent.mult * NSEC_PER_SEC;
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do_div(clc, freq);
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clc >>= hpet_clockevent.shift;
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hpet_pie_delta = (unsigned long) clc;
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hpet_pie_delta = clc;
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}
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return 1;
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}
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@ -1127,7 +1148,7 @@ EXPORT_SYMBOL_GPL(hpet_rtc_dropped_irq);
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static void hpet_rtc_timer_reinit(void)
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{
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unsigned long cfg, delta;
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unsigned int cfg, delta;
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int lost_ints = -1;
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if (unlikely(!hpet_rtc_flags)) {
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@ -2,6 +2,7 @@
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#include <linux/dmar.h>
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#include <linux/spinlock.h>
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#include <linux/jiffies.h>
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#include <linux/hpet.h>
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#include <linux/pci.h>
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#include <linux/irq.h>
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#include <asm/io_apic.h>
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@ -14,7 +15,8 @@
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#include "pci.h"
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static struct ioapic_scope ir_ioapic[MAX_IO_APICS];
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static int ir_ioapic_num;
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static struct hpet_scope ir_hpet[MAX_HPET_TBS];
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static int ir_ioapic_num, ir_hpet_num;
|
||||
int intr_remapping_enabled;
|
||||
|
||||
static int disable_intremap;
|
||||
|
|
@ -343,6 +345,16 @@ int flush_irte(int irq)
|
|||
return rc;
|
||||
}
|
||||
|
||||
struct intel_iommu *map_hpet_to_ir(u8 hpet_id)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 0; i < MAX_HPET_TBS; i++)
|
||||
if (ir_hpet[i].id == hpet_id)
|
||||
return ir_hpet[i].iommu;
|
||||
return NULL;
|
||||
}
|
||||
|
||||
struct intel_iommu *map_ioapic_to_ir(int apic)
|
||||
{
|
||||
int i;
|
||||
|
|
@ -470,6 +482,36 @@ int set_ioapic_sid(struct irte *irte, int apic)
|
|||
return 0;
|
||||
}
|
||||
|
||||
int set_hpet_sid(struct irte *irte, u8 id)
|
||||
{
|
||||
int i;
|
||||
u16 sid = 0;
|
||||
|
||||
if (!irte)
|
||||
return -1;
|
||||
|
||||
for (i = 0; i < MAX_HPET_TBS; i++) {
|
||||
if (ir_hpet[i].id == id) {
|
||||
sid = (ir_hpet[i].bus << 8) | ir_hpet[i].devfn;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
if (sid == 0) {
|
||||
pr_warning("Failed to set source-id of HPET block (%d)\n", id);
|
||||
return -1;
|
||||
}
|
||||
|
||||
/*
|
||||
* Should really use SQ_ALL_16. Some platforms are broken.
|
||||
* While we figure out the right quirks for these broken platforms, use
|
||||
* SQ_13_IGNORE_3 for now.
|
||||
*/
|
||||
set_irte_sid(irte, SVT_VERIFY_SID_SQ, SQ_13_IGNORE_3, sid);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int set_msi_sid(struct irte *irte, struct pci_dev *dev)
|
||||
{
|
||||
struct pci_dev *bridge;
|
||||
|
|
@ -711,6 +753,34 @@ error:
|
|||
return -1;
|
||||
}
|
||||
|
||||
static void ir_parse_one_hpet_scope(struct acpi_dmar_device_scope *scope,
|
||||
struct intel_iommu *iommu)
|
||||
{
|
||||
struct acpi_dmar_pci_path *path;
|
||||
u8 bus;
|
||||
int count;
|
||||
|
||||
bus = scope->bus;
|
||||
path = (struct acpi_dmar_pci_path *)(scope + 1);
|
||||
count = (scope->length - sizeof(struct acpi_dmar_device_scope))
|
||||
/ sizeof(struct acpi_dmar_pci_path);
|
||||
|
||||
while (--count > 0) {
|
||||
/*
|
||||
* Access PCI directly due to the PCI
|
||||
* subsystem isn't initialized yet.
|
||||
*/
|
||||
bus = read_pci_config_byte(bus, path->dev, path->fn,
|
||||
PCI_SECONDARY_BUS);
|
||||
path++;
|
||||
}
|
||||
ir_hpet[ir_hpet_num].bus = bus;
|
||||
ir_hpet[ir_hpet_num].devfn = PCI_DEVFN(path->dev, path->fn);
|
||||
ir_hpet[ir_hpet_num].iommu = iommu;
|
||||
ir_hpet[ir_hpet_num].id = scope->enumeration_id;
|
||||
ir_hpet_num++;
|
||||
}
|
||||
|
||||
static void ir_parse_one_ioapic_scope(struct acpi_dmar_device_scope *scope,
|
||||
struct intel_iommu *iommu)
|
||||
{
|
||||
|
|
@ -740,8 +810,8 @@ static void ir_parse_one_ioapic_scope(struct acpi_dmar_device_scope *scope,
|
|||
ir_ioapic_num++;
|
||||
}
|
||||
|
||||
static int ir_parse_ioapic_scope(struct acpi_dmar_header *header,
|
||||
struct intel_iommu *iommu)
|
||||
static int ir_parse_ioapic_hpet_scope(struct acpi_dmar_header *header,
|
||||
struct intel_iommu *iommu)
|
||||
{
|
||||
struct acpi_dmar_hardware_unit *drhd;
|
||||
struct acpi_dmar_device_scope *scope;
|
||||
|
|
@ -765,6 +835,17 @@ static int ir_parse_ioapic_scope(struct acpi_dmar_header *header,
|
|||
drhd->address);
|
||||
|
||||
ir_parse_one_ioapic_scope(scope, iommu);
|
||||
} else if (scope->entry_type == ACPI_DMAR_SCOPE_TYPE_HPET) {
|
||||
if (ir_hpet_num == MAX_HPET_TBS) {
|
||||
printk(KERN_WARNING "Exceeded Max HPET blocks\n");
|
||||
return -1;
|
||||
}
|
||||
|
||||
printk(KERN_INFO "HPET id %d under DRHD base"
|
||||
" 0x%Lx\n", scope->enumeration_id,
|
||||
drhd->address);
|
||||
|
||||
ir_parse_one_hpet_scope(scope, iommu);
|
||||
}
|
||||
start += scope->length;
|
||||
}
|
||||
|
|
@ -785,7 +866,7 @@ int __init parse_ioapics_under_ir(void)
|
|||
struct intel_iommu *iommu = drhd->iommu;
|
||||
|
||||
if (ecap_ir_support(iommu->ecap)) {
|
||||
if (ir_parse_ioapic_scope(drhd->hdr, iommu))
|
||||
if (ir_parse_ioapic_hpet_scope(drhd->hdr, iommu))
|
||||
return -1;
|
||||
|
||||
ir_supported = 1;
|
||||
|
|
|
|||
|
|
@ -7,4 +7,11 @@ struct ioapic_scope {
|
|||
unsigned int devfn; /* PCI devfn number */
|
||||
};
|
||||
|
||||
struct hpet_scope {
|
||||
struct intel_iommu *iommu;
|
||||
u8 id;
|
||||
unsigned int bus;
|
||||
unsigned int devfn;
|
||||
};
|
||||
|
||||
#define IR_X2APIC_MODE(mode) (mode ? (1 << 11) : 0)
|
||||
|
|
|
|||
|
|
@ -126,7 +126,9 @@ extern int free_irte(int irq);
|
|||
extern int irq_remapped(int irq);
|
||||
extern struct intel_iommu *map_dev_to_ir(struct pci_dev *dev);
|
||||
extern struct intel_iommu *map_ioapic_to_ir(int apic);
|
||||
extern struct intel_iommu *map_hpet_to_ir(u8 id);
|
||||
extern int set_ioapic_sid(struct irte *irte, int apic);
|
||||
extern int set_hpet_sid(struct irte *irte, u8 id);
|
||||
extern int set_msi_sid(struct irte *irte, struct pci_dev *dev);
|
||||
#else
|
||||
static inline int alloc_irte(struct intel_iommu *iommu, int irq, u16 count)
|
||||
|
|
@ -158,10 +160,18 @@ static inline struct intel_iommu *map_ioapic_to_ir(int apic)
|
|||
{
|
||||
return NULL;
|
||||
}
|
||||
static inline struct intel_iommu *map_hpet_to_ir(unsigned int hpet_id)
|
||||
{
|
||||
return NULL;
|
||||
}
|
||||
static inline int set_ioapic_sid(struct irte *irte, int apic)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
static inline int set_hpet_sid(struct irte *irte, u8 id)
|
||||
{
|
||||
return -1;
|
||||
}
|
||||
static inline int set_msi_sid(struct irte *irte, struct pci_dev *dev)
|
||||
{
|
||||
return 0;
|
||||
|
|
|
|||
|
|
@ -126,4 +126,6 @@ struct hpet_info {
|
|||
#define HPET_DPI _IO('h', 0x05) /* disable periodic */
|
||||
#define HPET_IRQFREQ _IOW('h', 0x6, unsigned long) /* IRQFREQ usec */
|
||||
|
||||
#define MAX_HPET_TBS 8 /* maximum hpet timer blocks */
|
||||
|
||||
#endif /* !__HPET__ */
|
||||
|
|
|
|||
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