drm/i915: extract i9xx_set_pipeconf
Prep-patch to improve the bpc handling in a next patch. Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
This commit is contained in:
Daniel Vetter
Родитель
9e9dd0e889
Коммит
84b046f398
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@ -4525,6 +4525,68 @@ static void intel_set_pipe_timings(struct intel_crtc *intel_crtc,
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((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
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}
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static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
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{
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struct drm_device *dev = intel_crtc->base.dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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uint32_t pipeconf;
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pipeconf = I915_READ(PIPECONF(intel_crtc->pipe));
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if (intel_crtc->pipe == 0 && INTEL_INFO(dev)->gen < 4) {
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/* Enable pixel doubling when the dot clock is > 90% of the (display)
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* core speed.
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*
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* XXX: No double-wide on 915GM pipe B. Is that the only reason for the
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* pipe == 0 check?
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*/
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if (intel_crtc->config.requested_mode.clock >
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dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
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pipeconf |= PIPECONF_DOUBLE_WIDE;
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else
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pipeconf &= ~PIPECONF_DOUBLE_WIDE;
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}
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/* default to 8bpc */
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pipeconf &= ~(PIPECONF_BPC_MASK | PIPECONF_DITHER_EN);
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if (intel_crtc->config.has_dp_encoder) {
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if (intel_crtc->config.dither) {
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pipeconf |= PIPECONF_6BPC |
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PIPECONF_DITHER_EN |
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PIPECONF_DITHER_TYPE_SP;
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}
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}
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if (IS_VALLEYVIEW(dev) && intel_pipe_has_type(&intel_crtc->base,
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INTEL_OUTPUT_EDP)) {
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if (intel_crtc->config.dither) {
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pipeconf |= PIPECONF_6BPC |
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PIPECONF_ENABLE |
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I965_PIPECONF_ACTIVE;
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}
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}
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if (HAS_PIPE_CXSR(dev)) {
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if (intel_crtc->lowfreq_avail) {
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DRM_DEBUG_KMS("enabling CxSR downclocking\n");
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pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
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} else {
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DRM_DEBUG_KMS("disabling CxSR downclocking\n");
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pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
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}
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}
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pipeconf &= ~PIPECONF_INTERLACE_MASK;
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if (!IS_GEN2(dev) &&
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intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
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pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
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else
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pipeconf |= PIPECONF_PROGRESSIVE;
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I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
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POSTING_READ(PIPECONF(intel_crtc->pipe));
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}
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static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
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int x, int y,
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struct drm_framebuffer *fb)
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@ -4539,7 +4601,7 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
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int plane = intel_crtc->plane;
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int refclk, num_connectors = 0;
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intel_clock_t clock, reduced_clock;
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u32 dspcntr, pipeconf;
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u32 dspcntr;
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bool ok, has_reduced_clock = false, is_sdvo = false;
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bool is_lvds = false, is_tv = false;
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struct intel_encoder *encoder;
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@ -4619,9 +4681,6 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
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has_reduced_clock ? &reduced_clock : NULL,
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num_connectors);
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/* setup pipeconf */
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pipeconf = I915_READ(PIPECONF(pipe));
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/* Set up the display plane register */
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dspcntr = DISPPLANE_GAMMA_ENABLE;
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@ -4632,58 +4691,9 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
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dspcntr |= DISPPLANE_SEL_PIPE_B;
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}
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if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
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/* Enable pixel doubling when the dot clock is > 90% of the (display)
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* core speed.
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*
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* XXX: No double-wide on 915GM pipe B. Is that the only reason for the
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* pipe == 0 check?
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*/
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if (mode->clock >
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dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
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pipeconf |= PIPECONF_DOUBLE_WIDE;
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else
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pipeconf &= ~PIPECONF_DOUBLE_WIDE;
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}
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/* default to 8bpc */
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pipeconf &= ~(PIPECONF_BPC_MASK | PIPECONF_DITHER_EN);
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if (intel_crtc->config.has_dp_encoder) {
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if (intel_crtc->config.dither) {
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pipeconf |= PIPECONF_6BPC |
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PIPECONF_DITHER_EN |
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PIPECONF_DITHER_TYPE_SP;
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}
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}
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if (IS_VALLEYVIEW(dev) && intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
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if (intel_crtc->config.dither) {
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pipeconf |= PIPECONF_6BPC |
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PIPECONF_ENABLE |
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I965_PIPECONF_ACTIVE;
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}
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}
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DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
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drm_mode_debug_printmodeline(mode);
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if (HAS_PIPE_CXSR(dev)) {
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if (intel_crtc->lowfreq_avail) {
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DRM_DEBUG_KMS("enabling CxSR downclocking\n");
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pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
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} else {
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DRM_DEBUG_KMS("disabling CxSR downclocking\n");
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pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
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}
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}
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pipeconf &= ~PIPECONF_INTERLACE_MASK;
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if (!IS_GEN2(dev) &&
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adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
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pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
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else
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pipeconf |= PIPECONF_PROGRESSIVE;
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intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
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/* pipesrc and dspsize control the size that is scaled from,
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@ -4694,8 +4704,8 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
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(mode->hdisplay - 1));
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I915_WRITE(DSPPOS(plane), 0);
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I915_WRITE(PIPECONF(pipe), pipeconf);
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POSTING_READ(PIPECONF(pipe));
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i9xx_set_pipeconf(intel_crtc);
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intel_enable_pipe(dev_priv, pipe, false);
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intel_wait_for_vblank(dev, pipe);
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