sparc64: Fix corrupted thread fault code.
Every path that ends up at do_sparc64_fault() must install a valid FAULT_CODE_* bitmask in the per-thread fault code byte. Two paths leading to the label winfix_trampoline (which expects the FAULT_CODE_* mask in register %g4) were not doing so: 1) For pre-hypervisor TLB protection violation traps, if we took the 'winfix_trampoline' path we wouldn't have %g4 initialized with the FAULT_CODE_* value yet. Resulting in using the TLB_TAG_ACCESS register address value instead. 2) In the TSB miss path, when we notice that we are going to use a hugepage mapping, but we haven't allocated the hugepage TSB yet, we still have to take the window fixup case into consideration and in that particular path we leave %g4 not setup properly. Errors on this sort were largely invisible previously, but after commit4ccb927289
("sparc64: sun4v TLB error power off events") we now have a fault_code mask bit (FAULT_CODE_BAD_RA) that triggers due to this bug. FAULT_CODE_BAD_RA triggers because this bit is set in TLB_TAG_ACCESS (see #1 above) and thus we get seemingly random bus errors triggered for user processes. Fixes:4ccb927289
("sparc64: sun4v TLB error power off events") Reported-by: Meelis Roos <mroos@linux.ee> Signed-off-by: David S. Miller <davem@davemloft.net>
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52d589a01d
Коммит
84bd6d8b9c
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@ -24,11 +24,11 @@
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mov TLB_TAG_ACCESS, %g4 ! For reload of vaddr
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/* PROT ** ICACHE line 2: More real fault processing */
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ldxa [%g4] ASI_DMMU, %g5 ! Put tagaccess in %g5
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bgu,pn %xcc, winfix_trampoline ! Yes, perform winfixup
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ldxa [%g4] ASI_DMMU, %g5 ! Put tagaccess in %g5
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ba,pt %xcc, sparc64_realfault_common ! Nope, normal fault
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mov FAULT_CODE_DTLB | FAULT_CODE_WRITE, %g4
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nop
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ba,pt %xcc, sparc64_realfault_common ! Nope, normal fault
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nop
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nop
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nop
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nop
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@ -162,10 +162,10 @@ tsb_miss_page_table_walk_sun4v_fastpath:
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nop
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.previous
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rdpr %tl, %g3
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cmp %g3, 1
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rdpr %tl, %g7
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cmp %g7, 1
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bne,pn %xcc, winfix_trampoline
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nop
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mov %g3, %g4
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ba,pt %xcc, etrap
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rd %pc, %g7
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call hugetlb_setup
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