crypto: inside-secure - Add support for 256 bit wide internal bus
This patch adds support for large EIP197's with a 256 bit wide internal bus, which affects the format of the result descriptor due to internal alignment requirements. Signed-off-by: Pascal van Leeuwen <pvanleeuwen@verimatrix.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
This commit is contained in:
Pascal van Leeuwen
Herbert Xu
Родитель
a9a89624f0
Коммит
84ca4e54ab
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@ -492,12 +492,12 @@ static int safexcel_hw_setup_cdesc_rings(struct safexcel_crypto_priv *priv)
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writel(upper_32_bits(priv->ring[i].cdr.base_dma),
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EIP197_HIA_CDR(priv, i) + EIP197_HIA_xDR_RING_BASE_ADDR_HI);
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writel(EIP197_xDR_DESC_MODE_64BIT | (priv->config.cd_offset << 16) |
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writel(EIP197_xDR_DESC_MODE_64BIT | (priv->config.cd_offset << 14) |
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priv->config.cd_size,
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EIP197_HIA_CDR(priv, i) + EIP197_HIA_xDR_DESC_SIZE);
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writel(((cd_fetch_cnt *
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(cd_size_rnd << priv->hwconfig.hwdataw)) << 16) |
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(cd_fetch_cnt * priv->config.cd_offset),
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(cd_fetch_cnt * (priv->config.cd_offset / sizeof(u32))),
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EIP197_HIA_CDR(priv, i) + EIP197_HIA_xDR_CFG);
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/* Configure DMA tx control */
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@ -540,13 +540,13 @@ static int safexcel_hw_setup_rdesc_rings(struct safexcel_crypto_priv *priv)
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writel(upper_32_bits(priv->ring[i].rdr.base_dma),
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EIP197_HIA_RDR(priv, i) + EIP197_HIA_xDR_RING_BASE_ADDR_HI);
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writel(EIP197_xDR_DESC_MODE_64BIT | (priv->config.rd_offset << 16) |
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writel(EIP197_xDR_DESC_MODE_64BIT | (priv->config.rd_offset << 14) |
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priv->config.rd_size,
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EIP197_HIA_RDR(priv, i) + EIP197_HIA_xDR_DESC_SIZE);
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writel(((rd_fetch_cnt *
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(rd_size_rnd << priv->hwconfig.hwdataw)) << 16) |
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(rd_fetch_cnt * priv->config.rd_offset),
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(rd_fetch_cnt * (priv->config.rd_offset / sizeof(u32))),
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EIP197_HIA_RDR(priv, i) + EIP197_HIA_xDR_CFG);
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/* Configure DMA tx control */
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@ -572,7 +572,7 @@ static int safexcel_hw_setup_rdesc_rings(struct safexcel_crypto_priv *priv)
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static int safexcel_hw_init(struct safexcel_crypto_priv *priv)
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{
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u32 val;
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int i, ret, pe;
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int i, ret, pe, opbuflo, opbufhi;
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dev_dbg(priv->dev, "HW init: using %d pipe(s) and %d ring(s)\n",
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priv->config.pes, priv->config.rings);
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@ -652,9 +652,16 @@ static int safexcel_hw_init(struct safexcel_crypto_priv *priv)
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;
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/* DMA transfer size to use */
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if (priv->hwconfig.hwnumpes > 4) {
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opbuflo = 9;
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opbufhi = 10;
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} else {
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opbuflo = 7;
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opbufhi = 8;
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}
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val = EIP197_HIA_DSE_CFG_DIS_DEBUG;
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val |= EIP197_HIA_DxE_CFG_MIN_DATA_SIZE(7) |
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EIP197_HIA_DxE_CFG_MAX_DATA_SIZE(8);
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val |= EIP197_HIA_DxE_CFG_MIN_DATA_SIZE(opbuflo) |
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EIP197_HIA_DxE_CFG_MAX_DATA_SIZE(opbufhi);
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val |= EIP197_HIA_DxE_CFG_DATA_CACHE_CTRL(WR_CACHE_3BITS);
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val |= EIP197_HIA_DSE_CFG_ALWAYS_BUFFERABLE;
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/* FIXME: instability issues can occur for EIP97 but disabling
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@ -668,8 +675,8 @@ static int safexcel_hw_init(struct safexcel_crypto_priv *priv)
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writel(0, EIP197_HIA_DSE_THR(priv) + EIP197_HIA_DSE_THR_CTRL(pe));
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/* Configure the procesing engine thresholds */
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writel(EIP197_PE_OUT_DBUF_THRES_MIN(7) |
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EIP197_PE_OUT_DBUF_THRES_MAX(8),
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writel(EIP197_PE_OUT_DBUF_THRES_MIN(opbuflo) |
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EIP197_PE_OUT_DBUF_THRES_MAX(opbufhi),
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EIP197_PE(priv) + EIP197_PE_OUT_DBUF_THRES(pe));
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/* Processing Engine configuration */
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@ -709,7 +716,7 @@ static int safexcel_hw_init(struct safexcel_crypto_priv *priv)
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writel(0,
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EIP197_HIA_CDR(priv, i) + EIP197_HIA_xDR_PROC_PNTR);
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writel((EIP197_DEFAULT_RING_SIZE * priv->config.cd_offset) << 2,
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writel((EIP197_DEFAULT_RING_SIZE * priv->config.cd_offset),
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EIP197_HIA_CDR(priv, i) + EIP197_HIA_xDR_RING_SIZE);
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}
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@ -732,7 +739,7 @@ static int safexcel_hw_init(struct safexcel_crypto_priv *priv)
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EIP197_HIA_RDR(priv, i) + EIP197_HIA_xDR_PROC_PNTR);
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/* Ring size */
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writel((EIP197_DEFAULT_RING_SIZE * priv->config.rd_offset) << 2,
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writel((EIP197_DEFAULT_RING_SIZE * priv->config.rd_offset),
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EIP197_HIA_RDR(priv, i) + EIP197_HIA_xDR_RING_SIZE);
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}
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@ -852,20 +859,24 @@ finalize:
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spin_unlock_bh(&priv->ring[ring].lock);
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/* let the RDR know we have pending descriptors */
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writel((rdesc * priv->config.rd_offset) << 2,
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writel((rdesc * priv->config.rd_offset),
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EIP197_HIA_RDR(priv, ring) + EIP197_HIA_xDR_PREP_COUNT);
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/* let the CDR know we have pending descriptors */
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writel((cdesc * priv->config.cd_offset) << 2,
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writel((cdesc * priv->config.cd_offset),
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EIP197_HIA_CDR(priv, ring) + EIP197_HIA_xDR_PREP_COUNT);
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}
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inline int safexcel_rdesc_check_errors(struct safexcel_crypto_priv *priv,
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struct safexcel_result_desc *rdesc)
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void *rdp)
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{
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if (likely((!rdesc->descriptor_overflow) &&
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(!rdesc->buffer_overflow) &&
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(!rdesc->result_data.error_code)))
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struct safexcel_result_desc *rdesc = rdp;
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struct result_data_desc *result_data = rdp + priv->config.res_offset;
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if (likely((!rdesc->last_seg) || /* Rest only valid if last seg! */
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((!rdesc->descriptor_overflow) &&
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(!rdesc->buffer_overflow) &&
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(!result_data->error_code))))
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return 0;
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if (rdesc->descriptor_overflow)
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@ -874,13 +885,14 @@ inline int safexcel_rdesc_check_errors(struct safexcel_crypto_priv *priv,
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if (rdesc->buffer_overflow)
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dev_err(priv->dev, "Buffer overflow detected");
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if (rdesc->result_data.error_code & 0x4066) {
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if (result_data->error_code & 0x4066) {
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/* Fatal error (bits 1,2,5,6 & 14) */
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dev_err(priv->dev,
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"result descriptor error (%x)",
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rdesc->result_data.error_code);
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result_data->error_code);
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return -EIO;
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} else if (rdesc->result_data.error_code &
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} else if (result_data->error_code &
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(BIT(7) | BIT(4) | BIT(3) | BIT(0))) {
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/*
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* Give priority over authentication fails:
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@ -888,7 +900,7 @@ inline int safexcel_rdesc_check_errors(struct safexcel_crypto_priv *priv,
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* something wrong with the input!
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*/
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return -EINVAL;
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} else if (rdesc->result_data.error_code & BIT(9)) {
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} else if (result_data->error_code & BIT(9)) {
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/* Authentication failed */
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return -EBADMSG;
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}
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@ -1019,7 +1031,7 @@ handle_results:
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acknowledge:
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if (i)
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writel(EIP197_xDR_PROC_xD_PKT(i) |
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EIP197_xDR_PROC_xD_COUNT(tot_descs * priv->config.rd_offset),
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(tot_descs * priv->config.rd_offset),
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EIP197_HIA_RDR(priv, ring) + EIP197_HIA_xDR_PROC_COUNT);
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/* If the number of requests overflowed the counter, try to proceed more
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@ -1292,30 +1304,25 @@ static void safexcel_unregister_algorithms(struct safexcel_crypto_priv *priv)
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static void safexcel_configure(struct safexcel_crypto_priv *priv)
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{
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u32 val, mask = 0;
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u32 mask = BIT(priv->hwconfig.hwdataw) - 1;
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val = readl(EIP197_HIA_AIC_G(priv) + EIP197_HIA_OPTIONS);
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priv->config.pes = priv->hwconfig.hwnumpes;
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priv->config.rings = min_t(u32, priv->hwconfig.hwnumrings, max_rings);
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/* Read number of PEs from the engine */
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if (priv->flags & SAFEXCEL_HW_EIP197)
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/* Wider field width for all EIP197 type engines */
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mask = EIP197_N_PES_MASK;
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else
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/* Narrow field width for EIP97 type engine */
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mask = EIP97_N_PES_MASK;
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priv->config.pes = (val >> EIP197_N_PES_OFFSET) & mask;
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priv->config.rings = min_t(u32, val & GENMASK(3, 0), max_rings);
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val = (val & GENMASK(27, 25)) >> 25;
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mask = BIT(val) - 1;
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priv->config.cd_size = (sizeof(struct safexcel_command_desc) / sizeof(u32));
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priv->config.cd_size = EIP197_CD64_FETCH_SIZE;
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priv->config.cd_offset = (priv->config.cd_size + mask) & ~mask;
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priv->config.rd_size = (sizeof(struct safexcel_result_desc) / sizeof(u32));
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/* res token is behind the descr, but ofs must be rounded to buswdth */
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priv->config.res_offset = (EIP197_RD64_FETCH_SIZE + mask) & ~mask;
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/* now the size of the descr is this 1st part plus the result struct */
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priv->config.rd_size = priv->config.res_offset +
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EIP197_RD64_RESULT_SIZE;
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priv->config.rd_offset = (priv->config.rd_size + mask) & ~mask;
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/* convert dwords to bytes */
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priv->config.cd_offset *= sizeof(u32);
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priv->config.rd_offset *= sizeof(u32);
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priv->config.res_offset *= sizeof(u32);
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}
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static void safexcel_init_register_offsets(struct safexcel_crypto_priv *priv)
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@ -1457,6 +1464,10 @@ static int safexcel_probe_generic(void *pdev,
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priv->hwconfig.hwrfsize = ((hiaopt >> EIP197_RFSIZE_OFFSET) &
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EIP197_RFSIZE_MASK) +
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EIP197_RFSIZE_ADJUST;
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priv->hwconfig.hwnumpes = (hiaopt >> EIP197_N_PES_OFFSET) &
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EIP197_N_PES_MASK;
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priv->hwconfig.hwnumrings = (hiaopt >> EIP197_N_RINGS_OFFSET) &
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EIP197_N_RINGS_MASK;
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} else {
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/* EIP97 */
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priv->hwconfig.hwdataw = (hiaopt >> EIP197_HWDATAW_OFFSET) &
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@ -1465,6 +1476,9 @@ static int safexcel_probe_generic(void *pdev,
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EIP97_CFSIZE_MASK;
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priv->hwconfig.hwrfsize = (hiaopt >> EIP97_RFSIZE_OFFSET) &
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EIP97_RFSIZE_MASK;
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priv->hwconfig.hwnumpes = 1; /* by definition */
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priv->hwconfig.hwnumrings = (hiaopt >> EIP197_N_RINGS_OFFSET) &
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EIP197_N_RINGS_MASK;
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}
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/* Get supported algorithms from EIP96 transform engine */
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@ -1472,8 +1486,9 @@ static int safexcel_probe_generic(void *pdev,
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EIP197_PE_EIP96_OPTIONS(0));
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/* Print single info line describing what we just detected */
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dev_info(priv->dev, "EIP%d:%x(%d)-HIA:%x(%d,%d,%d),PE:%x,alg:%08x\n",
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peid, priv->hwconfig.hwver, hwctg, priv->hwconfig.hiaver,
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dev_info(priv->dev, "EIP%d:%x(%d,%d,%d,%d)-HIA:%x(%d,%d,%d),PE:%x,alg:%08x\n",
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peid, priv->hwconfig.hwver, hwctg, priv->hwconfig.hwnumpes,
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priv->hwconfig.hwnumrings, priv->hwconfig.hiaver,
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priv->hwconfig.hwdataw, priv->hwconfig.hwcfsize,
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priv->hwconfig.hwrfsize, priv->hwconfig.pever,
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priv->hwconfig.algo_flags);
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@ -213,7 +213,6 @@
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/* EIP197_HIA_xDR_PROC_COUNT */
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#define EIP197_xDR_PROC_xD_PKT_OFFSET 24
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#define EIP197_xDR_PROC_xD_PKT_MASK GENMASK(6, 0)
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#define EIP197_xDR_PROC_xD_COUNT(n) ((n) << 2)
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#define EIP197_xDR_PROC_xD_PKT(n) ((n) << 24)
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#define EIP197_xDR_PROC_CLR_COUNT BIT(31)
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@ -228,6 +227,8 @@
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#define EIP197_HIA_RA_PE_CTRL_EN BIT(30)
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/* EIP197_HIA_OPTIONS */
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#define EIP197_N_RINGS_OFFSET 0
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#define EIP197_N_RINGS_MASK GENMASK(3, 0)
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#define EIP197_N_PES_OFFSET 4
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#define EIP197_N_PES_MASK GENMASK(4, 0)
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#define EIP97_N_PES_MASK GENMASK(2, 0)
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@ -486,16 +487,15 @@ struct safexcel_result_desc {
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u32 data_lo;
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u32 data_hi;
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struct result_data_desc result_data;
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} __packed;
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/*
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* The EIP(1)97 only needs to fetch the descriptor part of
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* the result descriptor, not the result token part!
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*/
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#define EIP197_RD64_FETCH_SIZE ((sizeof(struct safexcel_result_desc) -\
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sizeof(struct result_data_desc)) /\
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#define EIP197_RD64_FETCH_SIZE (sizeof(struct safexcel_result_desc) /\
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sizeof(u32))
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#define EIP197_RD64_RESULT_SIZE (sizeof(struct result_data_desc) /\
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sizeof(u32))
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struct safexcel_token {
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@ -582,6 +582,9 @@ struct safexcel_command_desc {
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struct safexcel_control_data_desc control_data;
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} __packed;
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#define EIP197_CD64_FETCH_SIZE (sizeof(struct safexcel_command_desc) /\
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sizeof(u32))
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/*
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* Internal structures & functions
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*/
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@ -625,6 +628,7 @@ struct safexcel_config {
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u32 rd_size;
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u32 rd_offset;
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u32 res_offset;
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};
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struct safexcel_work_data {
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@ -734,6 +738,8 @@ struct safexcel_hwconfig {
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int hwdataw;
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int hwcfsize;
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int hwrfsize;
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int hwnumpes;
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int hwnumrings;
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};
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struct safexcel_crypto_priv {
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@ -805,7 +811,7 @@ struct safexcel_inv_result {
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void safexcel_dequeue(struct safexcel_crypto_priv *priv, int ring);
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int safexcel_rdesc_check_errors(struct safexcel_crypto_priv *priv,
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struct safexcel_result_desc *rdesc);
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void *rdp);
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void safexcel_complete(struct safexcel_crypto_priv *priv, int ring);
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int safexcel_invalidate_cache(struct crypto_async_request *async,
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struct safexcel_crypto_priv *priv,
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@ -14,7 +14,7 @@ int safexcel_init_ring_descriptors(struct safexcel_crypto_priv *priv,
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struct safexcel_desc_ring *cdr,
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struct safexcel_desc_ring *rdr)
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{
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cdr->offset = sizeof(u32) * priv->config.cd_offset;
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cdr->offset = priv->config.cd_offset;
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cdr->base = dmam_alloc_coherent(priv->dev,
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cdr->offset * EIP197_DEFAULT_RING_SIZE,
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&cdr->base_dma, GFP_KERNEL);
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@ -24,7 +24,7 @@ int safexcel_init_ring_descriptors(struct safexcel_crypto_priv *priv,
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cdr->base_end = cdr->base + cdr->offset * (EIP197_DEFAULT_RING_SIZE - 1);
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cdr->read = cdr->base;
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rdr->offset = sizeof(u32) * priv->config.rd_offset;
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rdr->offset = priv->config.rd_offset;
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rdr->base = dmam_alloc_coherent(priv->dev,
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rdr->offset * EIP197_DEFAULT_RING_SIZE,
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&rdr->base_dma, GFP_KERNEL);
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