dt-bindings: power: Add Allwinner D1 PPU

The Allwinner D1 family of SoCs contain a PPU power domain controller
separate from the PRCM. It can power down the video engine and DSP, and
it contains special logic for hardware-assisted CPU idle. Other recent
Allwinner SoCs (e.g. TV303) have a PPU with a different set of domains.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Samuel Holland <samuel@sholland.org>
Link: https://lore.kernel.org/r/20230126063419.15971-2-samuel@sholland.org
Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
This commit is contained in:
Samuel Holland 2023-01-26 00:34:17 -06:00 коммит произвёл Jernej Skrabec
Родитель 73b7d7f2dc
Коммит 84def5abbb
2 изменённых файлов: 64 добавлений и 0 удалений

Просмотреть файл

@ -0,0 +1,54 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/power/allwinner,sun20i-d1-ppu.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Allwinner SoCs PPU power domain controller
maintainers:
- Samuel Holland <samuel@sholland.org>
description:
D1 and related SoCs contain a power domain controller for the CPUs, GPU, and
video-related hardware.
properties:
compatible:
enum:
- allwinner,sun20i-d1-ppu
reg:
maxItems: 1
clocks:
description: Bus Clock
maxItems: 1
resets:
maxItems: 1
'#power-domain-cells':
const: 1
required:
- compatible
- reg
- clocks
- resets
- '#power-domain-cells'
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/sun20i-d1-r-ccu.h>
#include <dt-bindings/reset/sun20i-d1-r-ccu.h>
ppu: power-controller@7001000 {
compatible = "allwinner,sun20i-d1-ppu";
reg = <0x7001000 0x1000>;
clocks = <&r_ccu CLK_BUS_R_PPU>;
resets = <&r_ccu RST_BUS_R_PPU>;
#power-domain-cells = <1>;
};

Просмотреть файл

@ -0,0 +1,10 @@
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
#ifndef _DT_BINDINGS_POWER_SUN20I_D1_PPU_H_
#define _DT_BINDINGS_POWER_SUN20I_D1_PPU_H_
#define PD_CPU 0
#define PD_VE 1
#define PD_DSP 2
#endif /* _DT_BINDINGS_POWER_SUN20I_D1_PPU_H_ */