ARM: SoC: fixes for v4.2-rc2
A fairly random colletion of fixes based on -rc1 for OMAP, sunxi and prima2 as well as a few arm64-specific DT fixes. This series also includes a late to support a new Allwinner (sunxi) SoC, but since it's rather simple and isolated to the platform-specific code, it's included it for this -rc. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJVoCLHAAoJEFk3GJrT+8ZlDcQP/jVIDk0MvuvfeIsbgWw4Bhys +ISmgdSTRwSAaI9oHp3ApNSOmq7QspqORdYsZinR6+Em1Seul5vvT9BN9bYAs4fP Uefvcyo9YSgiKQCLVbOkWnp1pJIPq7BKSvfNco159N4vi6RX+4A4XRrHhEbdLkGa OhKDnrh0TmbM5b2RkLXlMZR1vsBYEeKxpUlBe3FhKnXYo16yP9Aix2q6oMJBuf99 1kKNfp0DlGhBwkH+nqbUCgNi8OShFcIBrtR1X4fg7LjANEVNvE1Rv0yAJDzsz5hd g8v2xWaB+ONY08c4NelMLu0ZpspMV+fmeDmTuYpvOEPSYWvGamqEZUsdFMe1Vurm yqxIoMHSG71dW4SK35QtuvB5LJ/QPytaXidTBU4noFzTVqGaAsvZDHjbRh3YbFm1 3mB+l2oiWtS1zTOjNLK7fGpyWMZ5OKtKdIxMrDPdWR+IHQy7RDGomMIyT1KenrgF FO2a/1l4CDHumWFAiDx/vyfAm/KSO9uB8p5XTNIdVqge+uT3dVpmwpVSrl9IGDZy n0YCpqN94lqRR8tEZ+vzyK/zbaUN50t0xOIj3wQKqRUxQxWG//wuX8m1pYW3iJtB q/CbgladY4jYcEZFcKoeddBBVzI7E/ntPfL54O36Ubv/BA3dSUZ8RHmYi97OzhLf YuvxhEnO0zwLHvghibZk =UEUK -----END PGP SIGNATURE----- Merge tag 'armsoc-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC fixes from Kevin Hilman: "A fairly random colletion of fixes based on -rc1 for OMAP, sunxi and prima2 as well as a few arm64-specific DT fixes. This series also includes a late to support a new Allwinner (sunxi) SoC, but since it's rather simple and isolated to the platform-specific code, it's included it for this -rc" * tag 'armsoc-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: arm64: dts: add device tree for ARM SMM-A53x2 on LogicTile Express 20MG arm: dts: vexpress: add missing CCI PMU device node to TC2 arm: dts: vexpress: describe all PMUs in TC2 dts GICv3: Add ITS entry to THUNDER dts arm64: dts: Add poweroff button device node for APM X-Gene platform ARM: dts: am4372.dtsi: disable rfbi ARM: dts: am57xx-beagle-x15: Provide supply for usb2_phy2 ARM: dts: am4372: Add emif node Revert "ARM: dts: am335x-boneblack: disable RTC-only sleep" ARM: sunxi: Enable simplefb in the defconfig ARM: Remove deprecated symbol from defconfig files ARM: sunxi: Add Machine support for A33 ARM: sunxi: Introduce Allwinner H3 support Documentation: sunxi: Update Allwinner SoC documentation ARM: prima2: move to use REGMAP APIs for rtciobrg ARM: dts: atlas7: add pinctrl and gpio descriptions ARM: OMAP2+: Remove unnessary return statement from the void function, omap2_show_dma_caps memory: omap-gpmc: Fix parsing of devices
This commit is contained in:
Linus Torvalds
Коммит
84e3e9d04d
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@ -36,7 +36,7 @@ SunXi family
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+ User Manual
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http://dl.linux-sunxi.org/A20/A20%20User%20Manual%202013-03-22.pdf
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- Allwinner A23
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- Allwinner A23 (sun8i)
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+ Datasheet
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http://dl.linux-sunxi.org/A23/A23%20Datasheet%20V1.0%2020130830.pdf
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+ User Manual
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|
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@ -55,7 +55,23 @@ SunXi family
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+ User Manual
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http://dl.linux-sunxi.org/A31/A3x_release_document/A31s/IC/A31s%20User%20Manual%20%20V1.0%2020130322.pdf
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- Allwinner A33 (sun8i)
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+ Datasheet
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http://dl.linux-sunxi.org/A33/A33%20Datasheet%20release%201.1.pdf
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+ User Manual
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http://dl.linux-sunxi.org/A33/A33%20user%20manual%20release%201.1.pdf
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- Allwinner H3 (sun8i)
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+ Datasheet
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http://dl.linux-sunxi.org/H3/Allwinner_H3_Datasheet_V1.0.pdf
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* Quad ARM Cortex-A15, Quad ARM Cortex-A7 based SoCs
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- Allwinner A80
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+ Datasheet
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http://dl.linux-sunxi.org/A80/A80_Datasheet_Revision_1.0_0404.pdf
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* Octa ARM Cortex-A7 based SoCs
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- Allwinner A83T
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+ Not Supported
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+ Datasheet
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http://dl.linux-sunxi.org/A83T/A83T_datasheet_Revision_1.1.pdf
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|
|
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@ -9,4 +9,6 @@ using one of the following compatible strings:
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allwinner,sun6i-a31
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allwinner,sun7i-a20
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allwinner,sun8i-a23
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allwinner,sun8i-a33
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allwinner,sun8i-h3
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allwinner,sun9i-a80
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@ -8,6 +8,7 @@ of the EMIF IP and memory parts attached to it.
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Required properties:
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- compatible : Should be of the form "ti,emif-<ip-rev>" where <ip-rev>
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is the IP revision of the specific EMIF instance.
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For am437x should be ti,emif-am4372.
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- phy-type : <u32> indicating the DDR phy type. Following are the
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allowed values
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@ -1614,6 +1614,7 @@ M: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
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L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
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S: Maintained
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F: arch/arm/boot/dts/vexpress*
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F: arch/arm64/boot/dts/arm/vexpress*
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F: arch/arm/mach-vexpress/
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F: */*/vexpress*
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F: */*/*/vexpress*
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@ -80,3 +80,7 @@
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status = "okay";
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};
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};
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&rtc {
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system-power-controller;
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};
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@ -132,6 +132,12 @@
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};
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};
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emif: emif@4c000000 {
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compatible = "ti,emif-am4372";
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reg = <0x4c000000 0x1000000>;
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ti,hwmods = "emif";
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};
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edma: edma@49000000 {
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compatible = "ti,edma3";
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ti,hwmods = "tpcc", "tptc0", "tptc1", "tptc2";
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@ -941,6 +947,7 @@
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ti,hwmods = "dss_rfbi";
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clocks = <&disp_clk>;
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clock-names = "fck";
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status = "disabled";
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};
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};
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|
|
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@ -605,6 +605,10 @@
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phy-supply = <&ldousb_reg>;
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};
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&usb2_phy2 {
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phy-supply = <&ldousb_reg>;
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};
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&usb1 {
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dr_mode = "host";
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pinctrl-names = "default";
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|
|
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Разница между файлами не показана из-за своего большого размера
Загрузить разницу
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|
@ -150,6 +150,16 @@
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interface-type = "ace";
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reg = <0x5000 0x1000>;
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};
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pmu@9000 {
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compatible = "arm,cci-400-pmu,r0";
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reg = <0x9000 0x5000>;
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interrupts = <0 105 4>,
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<0 101 4>,
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<0 102 4>,
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<0 103 4>,
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<0 104 4>;
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};
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};
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memory-controller@7ffd0000 {
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@ -187,11 +197,22 @@
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<1 10 0xf08>;
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};
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pmu {
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pmu_a15 {
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compatible = "arm,cortex-a15-pmu";
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interrupts = <0 68 4>,
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<0 69 4>;
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interrupt-affinity = <&cpu0>, <&cpu1>;
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interrupt-affinity = <&cpu0>,
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<&cpu1>;
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};
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pmu_a7 {
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compatible = "arm,cortex-a7-pmu";
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interrupts = <0 128 4>,
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<0 129 4>,
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<0 130 4>;
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interrupt-affinity = <&cpu2>,
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<&cpu3>,
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<&cpu4>;
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};
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oscclk6a: oscclk6a {
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|
|
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|
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@ -353,7 +353,6 @@ CONFIG_POWER_RESET_AS3722=y
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CONFIG_POWER_RESET_GPIO=y
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CONFIG_POWER_RESET_GPIO_RESTART=y
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CONFIG_POWER_RESET_KEYSTONE=y
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CONFIG_POWER_RESET_SUN6I=y
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CONFIG_POWER_RESET_RMOBILE=y
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CONFIG_SENSORS_LM90=y
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CONFIG_SENSORS_LM95245=y
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|
|
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|
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@ -2,6 +2,7 @@ CONFIG_NO_HZ=y
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CONFIG_HIGH_RES_TIMERS=y
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CONFIG_BLK_DEV_INITRD=y
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CONFIG_PERF_EVENTS=y
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CONFIG_MODULES=y
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CONFIG_ARCH_SUNXI=y
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CONFIG_SMP=y
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CONFIG_NR_CPUS=8
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|
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@ -77,7 +78,6 @@ CONFIG_SPI_SUN6I=y
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CONFIG_GPIO_SYSFS=y
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CONFIG_POWER_SUPPLY=y
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CONFIG_POWER_RESET=y
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CONFIG_POWER_RESET_SUN6I=y
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CONFIG_THERMAL=y
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CONFIG_CPU_THERMAL=y
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CONFIG_WATCHDOG=y
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@ -87,6 +87,10 @@ CONFIG_REGULATOR=y
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CONFIG_REGULATOR_FIXED_VOLTAGE=y
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CONFIG_REGULATOR_AXP20X=y
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CONFIG_REGULATOR_GPIO=y
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CONFIG_FB=y
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CONFIG_FB_SIMPLE=y
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CONFIG_FRAMEBUFFER_CONSOLE=y
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CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
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CONFIG_USB=y
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CONFIG_USB_EHCI_HCD=y
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CONFIG_USB_EHCI_HCD_PLATFORM=y
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|
|
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|
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@ -117,7 +117,6 @@ static void omap2_show_dma_caps(void)
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u8 revision = dma_read(REVISION, 0) & 0xff;
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printk(KERN_INFO "OMAP DMA hardware revision %d.%d\n",
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revision >> 4, revision & 0xf);
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return;
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}
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static unsigned configure_dma_errata(void)
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|
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@ -4,6 +4,7 @@ menuconfig ARCH_SIRF
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select ARCH_REQUIRE_GPIOLIB
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select GENERIC_IRQ_CHIP
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select NO_IOPORT_MAP
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select REGMAP
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select PINCTRL
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select PINCTRL_SIRF
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help
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@ -1,5 +1,5 @@
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/*
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* RTC I/O Bridge interfaces for CSR SiRFprimaII
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* RTC I/O Bridge interfaces for CSR SiRFprimaII/atlas7
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* ARM access the registers of SYSRTC, GPSRTC and PWRC through this module
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*
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* Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
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@ -10,6 +10,7 @@
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/io.h>
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#include <linux/regmap.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_device.h>
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@ -66,6 +67,7 @@ u32 sirfsoc_rtc_iobrg_readl(u32 addr)
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{
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unsigned long flags, val;
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/* TODO: add hwspinlock to sync with M3 */
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spin_lock_irqsave(&rtciobrg_lock, flags);
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val = __sirfsoc_rtc_iobrg_readl(addr);
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@ -90,6 +92,7 @@ void sirfsoc_rtc_iobrg_writel(u32 val, u32 addr)
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{
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unsigned long flags;
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/* TODO: add hwspinlock to sync with M3 */
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spin_lock_irqsave(&rtciobrg_lock, flags);
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sirfsoc_rtc_iobrg_pre_writel(val, addr);
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@ -102,6 +105,45 @@ void sirfsoc_rtc_iobrg_writel(u32 val, u32 addr)
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}
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EXPORT_SYMBOL_GPL(sirfsoc_rtc_iobrg_writel);
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static int regmap_iobg_regwrite(void *context, unsigned int reg,
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unsigned int val)
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{
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sirfsoc_rtc_iobrg_writel(val, reg);
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return 0;
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}
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static int regmap_iobg_regread(void *context, unsigned int reg,
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unsigned int *val)
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{
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*val = (u32)sirfsoc_rtc_iobrg_readl(reg);
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return 0;
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}
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static struct regmap_bus regmap_iobg = {
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.reg_write = regmap_iobg_regwrite,
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.reg_read = regmap_iobg_regread,
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};
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/**
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* devm_regmap_init_iobg(): Initialise managed register map
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*
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* @iobg: Device that will be interacted with
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* @config: Configuration for register map
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*
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* The return value will be an ERR_PTR() on error or a valid pointer
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* to a struct regmap. The regmap will be automatically freed by the
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* device management code.
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*/
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struct regmap *devm_regmap_init_iobg(struct device *dev,
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const struct regmap_config *config)
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{
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const struct regmap_bus *bus = ®map_iobg;
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return devm_regmap_init(dev, bus, dev, config);
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}
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EXPORT_SYMBOL_GPL(devm_regmap_init_iobg);
|
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static const struct of_device_id rtciobrg_ids[] = {
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{ .compatible = "sirf,prima2-rtciobg" },
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{}
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|
|
@ -132,7 +174,7 @@ static int __init sirfsoc_rtciobrg_init(void)
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|||
}
|
||||
postcore_initcall(sirfsoc_rtciobrg_init);
|
||||
|
||||
MODULE_AUTHOR("Zhiwu Song <zhiwu.song@csr.com>, "
|
||||
"Barry Song <baohua.song@csr.com>");
|
||||
MODULE_AUTHOR("Zhiwu Song <zhiwu.song@csr.com>");
|
||||
MODULE_AUTHOR("Barry Song <baohua.song@csr.com>");
|
||||
MODULE_DESCRIPTION("CSR SiRFprimaII rtc io bridge");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
|
|
|
|||
|
|
@ -35,7 +35,7 @@ config MACH_SUN7I
|
|||
select SUN5I_HSTIMER
|
||||
|
||||
config MACH_SUN8I
|
||||
bool "Allwinner A23 (sun8i) SoCs support"
|
||||
bool "Allwinner sun8i Family SoCs support"
|
||||
default ARCH_SUNXI
|
||||
select ARM_GIC
|
||||
select MFD_SUN6I_PRCM
|
||||
|
|
|
|||
|
|
@ -67,10 +67,13 @@ MACHINE_END
|
|||
|
||||
static const char * const sun8i_board_dt_compat[] = {
|
||||
"allwinner,sun8i-a23",
|
||||
"allwinner,sun8i-a33",
|
||||
"allwinner,sun8i-h3",
|
||||
NULL,
|
||||
};
|
||||
|
||||
DT_MACHINE_START(SUN8I_DT, "Allwinner sun8i (A23) Family")
|
||||
DT_MACHINE_START(SUN8I_DT, "Allwinner sun8i Family")
|
||||
.init_time = sun6i_timer_init,
|
||||
.dt_compat = sun8i_board_dt_compat,
|
||||
.init_late = sunxi_dt_cpufreq_init,
|
||||
MACHINE_END
|
||||
|
|
|
|||
|
|
@ -23,6 +23,16 @@
|
|||
device_type = "memory";
|
||||
reg = < 0x1 0x00000000 0x0 0x80000000 >; /* Updated by bootloader */
|
||||
};
|
||||
|
||||
gpio-keys {
|
||||
compatible = "gpio-keys";
|
||||
button@1 {
|
||||
label = "POWER";
|
||||
linux,code = <116>;
|
||||
linux,input-type = <0x1>;
|
||||
interrupts = <0x0 0x2d 0x1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pcie0clk {
|
||||
|
|
|
|||
|
|
@ -1,6 +1,7 @@
|
|||
dtb-$(CONFIG_ARCH_VEXPRESS) += foundation-v8.dtb
|
||||
dtb-$(CONFIG_ARCH_VEXPRESS) += juno.dtb juno-r1.dtb
|
||||
dtb-$(CONFIG_ARCH_VEXPRESS) += rtsm_ve-aemv8a.dtb
|
||||
dtb-$(CONFIG_ARCH_VEXPRESS) += vexpress-v2f-1xv7-ca53x2.dtb
|
||||
|
||||
always := $(dtb-y)
|
||||
subdir-y := $(dts-dirs)
|
||||
|
|
|
|||
|
|
@ -0,0 +1,191 @@
|
|||
/*
|
||||
* ARM Ltd. Versatile Express
|
||||
*
|
||||
* LogicTile Express 20MG
|
||||
* V2F-1XV7
|
||||
*
|
||||
* Cortex-A53 (2 cores) Soft Macrocell Model
|
||||
*
|
||||
* HBI-0247C
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
/ {
|
||||
model = "V2F-1XV7 Cortex-A53x2 SMM";
|
||||
arm,hbi = <0x247>;
|
||||
arm,vexpress,site = <0xf>;
|
||||
compatible = "arm,vexpress,v2f-1xv7,ca53x2", "arm,vexpress,v2f-1xv7", "arm,vexpress";
|
||||
interrupt-parent = <&gic>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:38400n8";
|
||||
};
|
||||
|
||||
aliases {
|
||||
serial0 = &v2m_serial0;
|
||||
serial1 = &v2m_serial1;
|
||||
serial2 = &v2m_serial2;
|
||||
serial3 = &v2m_serial3;
|
||||
i2c0 = &v2m_i2c_dvi;
|
||||
i2c1 = &v2m_i2c_pcie;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a53", "arm,armv8";
|
||||
reg = <0 0>;
|
||||
next-level-cache = <&L2_0>;
|
||||
};
|
||||
|
||||
cpu@1 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a53", "arm,armv8";
|
||||
reg = <0 1>;
|
||||
next-level-cache = <&L2_0>;
|
||||
};
|
||||
|
||||
L2_0: l2-cache0 {
|
||||
compatible = "cache";
|
||||
};
|
||||
};
|
||||
|
||||
memory@80000000 {
|
||||
device_type = "memory";
|
||||
reg = <0 0x80000000 0 0x80000000>; /* 2GB @ 2GB */
|
||||
};
|
||||
|
||||
gic: interrupt-controller@2c001000 {
|
||||
compatible = "arm,gic-400";
|
||||
#interrupt-cells = <3>;
|
||||
#address-cells = <0>;
|
||||
interrupt-controller;
|
||||
reg = <0 0x2c001000 0 0x1000>,
|
||||
<0 0x2c002000 0 0x2000>,
|
||||
<0 0x2c004000 0 0x2000>,
|
||||
<0 0x2c006000 0 0x2000>;
|
||||
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
|
||||
};
|
||||
|
||||
timer {
|
||||
compatible = "arm,armv8-timer";
|
||||
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
|
||||
};
|
||||
|
||||
pmu {
|
||||
compatible = "arm,armv8-pmuv3";
|
||||
interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
dcc {
|
||||
compatible = "arm,vexpress,config-bus";
|
||||
arm,vexpress,config-bridge = <&v2m_sysreg>;
|
||||
|
||||
smbclk: osc@4 {
|
||||
/* SMC clock */
|
||||
compatible = "arm,vexpress-osc";
|
||||
arm,vexpress-sysreg,func = <1 4>;
|
||||
freq-range = <40000000 40000000>;
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "smclk";
|
||||
};
|
||||
|
||||
volt@0 {
|
||||
/* VIO to expansion board above */
|
||||
compatible = "arm,vexpress-volt";
|
||||
arm,vexpress-sysreg,func = <2 0>;
|
||||
regulator-name = "VIO_UP";
|
||||
regulator-min-microvolt = <800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
volt@1 {
|
||||
/* 12V from power connector J6 */
|
||||
compatible = "arm,vexpress-volt";
|
||||
arm,vexpress-sysreg,func = <2 1>;
|
||||
regulator-name = "12";
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
temp@0 {
|
||||
/* FPGA temperature */
|
||||
compatible = "arm,vexpress-temp";
|
||||
arm,vexpress-sysreg,func = <4 0>;
|
||||
label = "FPGA";
|
||||
};
|
||||
};
|
||||
|
||||
smb {
|
||||
compatible = "simple-bus";
|
||||
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0 0 0x08000000 0x04000000>,
|
||||
<1 0 0 0x14000000 0x04000000>,
|
||||
<2 0 0 0x18000000 0x04000000>,
|
||||
<3 0 0 0x1c000000 0x04000000>,
|
||||
<4 0 0 0x0c000000 0x04000000>,
|
||||
<5 0 0 0x10000000 0x04000000>;
|
||||
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 63>;
|
||||
interrupt-map = <0 0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 1 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 2 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 3 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 4 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 5 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 6 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 7 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 8 &gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 9 &gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 10 &gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 11 &gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 12 &gic GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 13 &gic GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 14 &gic GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 15 &gic GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 16 &gic GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 17 &gic GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 18 &gic GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 19 &gic GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 20 &gic GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 21 &gic GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 22 &gic GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 23 &gic GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 24 &gic GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 25 &gic GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 26 &gic GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 27 &gic GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 28 &gic GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 29 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 30 &gic GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 31 &gic GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 32 &gic GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 33 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 34 &gic GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 35 &gic GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 36 &gic GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 37 &gic GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 38 &gic GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 39 &gic GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 40 &gic GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 41 &gic GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 0 42 &gic GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
/include/ "../../../../arm/boot/dts/vexpress-v2m-rs1.dtsi"
|
||||
};
|
||||
};
|
||||
|
|
@ -376,10 +376,19 @@
|
|||
gic0: interrupt-controller@8010,00000000 {
|
||||
compatible = "arm,gic-v3";
|
||||
#interrupt-cells = <3>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
interrupt-controller;
|
||||
reg = <0x8010 0x00000000 0x0 0x010000>, /* GICD */
|
||||
<0x8010 0x80000000 0x0 0x600000>; /* GICR */
|
||||
interrupts = <1 9 0xf04>;
|
||||
|
||||
its: gic-its@8010,00020000 {
|
||||
compatible = "arm,gic-v3-its";
|
||||
msi-controller;
|
||||
reg = <0x8010 0x20000 0x0 0x200000>;
|
||||
};
|
||||
};
|
||||
|
||||
uaa0: serial@87e0,24000000 {
|
||||
|
|
|
|||
|
|
@ -1391,6 +1391,7 @@ static void __init sun6i_init_clocks(struct device_node *node)
|
|||
CLK_OF_DECLARE(sun6i_a31_clk_init, "allwinner,sun6i-a31", sun6i_init_clocks);
|
||||
CLK_OF_DECLARE(sun6i_a31s_clk_init, "allwinner,sun6i-a31s", sun6i_init_clocks);
|
||||
CLK_OF_DECLARE(sun8i_a23_clk_init, "allwinner,sun8i-a23", sun6i_init_clocks);
|
||||
CLK_OF_DECLARE(sun8i_a33_clk_init, "allwinner,sun8i-a33", sun6i_init_clocks);
|
||||
|
||||
static void __init sun9i_init_clocks(struct device_node *node)
|
||||
{
|
||||
|
|
|
|||
|
|
@ -2074,14 +2074,8 @@ static int gpmc_probe_dt(struct platform_device *pdev)
|
|||
ret = gpmc_probe_nand_child(pdev, child);
|
||||
else if (of_node_cmp(child->name, "onenand") == 0)
|
||||
ret = gpmc_probe_onenand_child(pdev, child);
|
||||
else if (of_node_cmp(child->name, "ethernet") == 0 ||
|
||||
of_node_cmp(child->name, "nor") == 0 ||
|
||||
of_node_cmp(child->name, "uart") == 0)
|
||||
else
|
||||
ret = gpmc_probe_generic_child(pdev, child);
|
||||
|
||||
if (WARN(ret < 0, "%s: probing gpmc child %s failed\n",
|
||||
__func__, child->full_name))
|
||||
of_node_put(child);
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
|
|
|||
|
|
@ -9,10 +9,14 @@
|
|||
#ifndef _SIRFSOC_RTC_IOBRG_H_
|
||||
#define _SIRFSOC_RTC_IOBRG_H_
|
||||
|
||||
struct regmap_config;
|
||||
|
||||
extern void sirfsoc_rtc_iobrg_besyncing(void);
|
||||
|
||||
extern u32 sirfsoc_rtc_iobrg_readl(u32 addr);
|
||||
|
||||
extern void sirfsoc_rtc_iobrg_writel(u32 val, u32 addr);
|
||||
struct regmap *devm_regmap_init_iobg(struct device *dev,
|
||||
const struct regmap_config *config);
|
||||
|
||||
#endif
|
||||
|
|
|
|||
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