serial: add support for ITE 887x chips
Add support for the it887x-chips (PCI) manufactured by ITE. Signed-off-by: Niels de Vos <niels.devos@wincor-nixdorf.com> Cc: Russell King <rmk@arm.linux.org.uk> Acked-by: Alan Cox <alan@lxorguk.ukuu.org.uk> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
This commit is contained in:
Niels de Vos
Linus Torvalds
Родитель
20620d688a
Коммит
84f8c6fc0e
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@ -580,6 +580,138 @@ static int pci_netmos_init(struct pci_dev *dev)
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return num_serial;
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}
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/*
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* ITE support by Niels de Vos <niels.devos@wincor-nixdorf.com>
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*
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* These chips are available with optionally one parallel port and up to
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* two serial ports. Unfortunately they all have the same product id.
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*
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* Basic configuration is done over a region of 32 I/O ports. The base
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* ioport is called INTA or INTC, depending on docs/other drivers.
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*
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* The region of the 32 I/O ports is configured in POSIO0R...
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*/
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/* registers */
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#define ITE_887x_MISCR 0x9c
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#define ITE_887x_INTCBAR 0x78
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#define ITE_887x_UARTBAR 0x7c
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#define ITE_887x_PS0BAR 0x10
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#define ITE_887x_POSIO0 0x60
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/* I/O space size */
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#define ITE_887x_IOSIZE 32
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/* I/O space size (bits 26-24; 8 bytes = 011b) */
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#define ITE_887x_POSIO_IOSIZE_8 (3 << 24)
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/* I/O space size (bits 26-24; 32 bytes = 101b) */
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#define ITE_887x_POSIO_IOSIZE_32 (5 << 24)
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/* Decoding speed (1 = slow, 2 = medium, 3 = fast) */
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#define ITE_887x_POSIO_SPEED (3 << 29)
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/* enable IO_Space bit */
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#define ITE_887x_POSIO_ENABLE (1 << 31)
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static int __devinit pci_ite887x_init(struct pci_dev *dev)
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{
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/* inta_addr are the configuration addresses of the ITE */
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static const short inta_addr[] = { 0x2a0, 0x2c0, 0x220, 0x240, 0x1e0,
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0x200, 0x280, 0 };
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int ret, i, type;
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struct resource *iobase = NULL;
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u32 miscr, uartbar, ioport;
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/* search for the base-ioport */
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i = 0;
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while (inta_addr[i] && iobase == NULL) {
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iobase = request_region(inta_addr[i], ITE_887x_IOSIZE,
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"ite887x");
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if (iobase != NULL) {
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/* write POSIO0R - speed | size | ioport */
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pci_write_config_dword(dev, ITE_887x_POSIO0,
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ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
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ITE_887x_POSIO_IOSIZE_32 | inta_addr[i]);
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/* write INTCBAR - ioport */
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pci_write_config_dword(dev, ITE_887x_INTCBAR, inta_addr[i]);
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ret = inb(inta_addr[i]);
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if (ret != 0xff) {
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/* ioport connected */
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break;
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}
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release_region(iobase->start, ITE_887x_IOSIZE);
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iobase = NULL;
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}
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i++;
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}
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if (!inta_addr[i]) {
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printk(KERN_ERR "ite887x: could not find iobase\n");
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return -ENODEV;
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}
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/* start of undocumented type checking (see parport_pc.c) */
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type = inb(iobase->start + 0x18) & 0x0f;
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switch (type) {
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case 0x2: /* ITE8871 (1P) */
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case 0xa: /* ITE8875 (1P) */
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ret = 0;
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break;
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case 0xe: /* ITE8872 (2S1P) */
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ret = 2;
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break;
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case 0x6: /* ITE8873 (1S) */
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ret = 1;
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break;
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case 0x8: /* ITE8874 (2S) */
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ret = 2;
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break;
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default:
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moan_device("Unknown ITE887x", dev);
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ret = -ENODEV;
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}
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/* configure all serial ports */
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for (i = 0; i < ret; i++) {
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/* read the I/O port from the device */
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pci_read_config_dword(dev, ITE_887x_PS0BAR + (0x4 * (i + 1)),
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&ioport);
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ioport &= 0x0000FF00; /* the actual base address */
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pci_write_config_dword(dev, ITE_887x_POSIO0 + (0x4 * (i + 1)),
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ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
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ITE_887x_POSIO_IOSIZE_8 | ioport);
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/* write the ioport to the UARTBAR */
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pci_read_config_dword(dev, ITE_887x_UARTBAR, &uartbar);
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uartbar &= ~(0xffff << (16 * i)); /* clear half the reg */
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uartbar |= (ioport << (16 * i)); /* set the ioport */
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pci_write_config_dword(dev, ITE_887x_UARTBAR, uartbar);
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/* get current config */
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pci_read_config_dword(dev, ITE_887x_MISCR, &miscr);
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/* disable interrupts (UARTx_Routing[3:0]) */
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miscr &= ~(0xf << (12 - 4 * i));
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/* activate the UART (UARTx_En) */
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miscr |= 1 << (23 - i);
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/* write new config with activated UART */
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pci_write_config_dword(dev, ITE_887x_MISCR, miscr);
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}
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if (ret <= 0) {
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/* the device has no UARTs if we get here */
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release_region(iobase->start, ITE_887x_IOSIZE);
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}
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return ret;
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}
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static void __devexit pci_ite887x_exit(struct pci_dev *dev)
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{
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u32 ioport;
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/* the ioport is bit 0-15 in POSIO0R */
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pci_read_config_dword(dev, ITE_887x_POSIO0, &ioport);
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ioport &= 0xffff;
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release_region(ioport, ITE_887x_IOSIZE);
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}
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static int
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pci_default_setup(struct serial_private *priv, struct pciserial_board *board,
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struct uart_port *port, int idx)
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@ -652,6 +784,18 @@ static struct pci_serial_quirk pci_serial_quirks[] = {
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.init = pci_inteli960ni_init,
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.setup = pci_default_setup,
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},
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/*
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* ITE
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*/
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{
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.vendor = PCI_VENDOR_ID_ITE,
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.device = PCI_DEVICE_ID_ITE_8872,
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.subvendor = PCI_ANY_ID,
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.subdevice = PCI_ANY_ID,
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.init = pci_ite887x_init,
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.setup = pci_default_setup,
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.exit = __devexit_p(pci_ite887x_exit),
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},
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/*
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* Panacom
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*/
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@ -933,6 +1077,7 @@ enum pci_board_num_t {
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pbn_b1_2_1250000,
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pbn_b1_bt_1_115200,
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pbn_b1_bt_2_921600,
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pbn_b1_1_1382400,
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@ -1211,6 +1356,13 @@ static struct pciserial_board pci_boards[] __devinitdata = {
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.uart_offset = 8,
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},
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[pbn_b1_bt_1_115200] = {
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.flags = FL_BASE1|FL_BASE_BARS,
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.num_ports = 1,
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.base_baud = 115200,
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.uart_offset = 8,
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},
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[pbn_b1_bt_2_921600] = {
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.flags = FL_BASE1|FL_BASE_BARS,
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.num_ports = 2,
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@ -2364,6 +2516,13 @@ static struct pci_device_id serial_pci_tbl[] = {
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{ PCI_VENDOR_ID_TOPIC, PCI_DEVICE_ID_TOPIC_TP560,
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PCI_ANY_ID, PCI_ANY_ID, 0, 0,
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pbn_b0_1_115200 },
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/*
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* ITE
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*/
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{ PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8872,
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PCI_ANY_ID, PCI_ANY_ID,
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0, 0,
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pbn_b1_bt_1_115200 },
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/*
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* IntaShield IS-200
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