net: bcmgenet: code movement
The Hardware Filter Block code will be used by ethtool functions when defining flow types so this commit moves the functions in the file to prevent the need for prototype declarations. This is broken out to facilitate review. Signed-off-by: Doug Berger <opendmb@gmail.com> Acked-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Doug Berger
David S. Miller
Родитель
14da1510fe
Коммит
854295d03c
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@ -459,6 +459,160 @@ static inline void bcmgenet_rdma_ring_writel(struct bcmgenet_priv *priv,
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genet_dma_ring_regs[r]);
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}
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static bool bcmgenet_hfb_is_filter_enabled(struct bcmgenet_priv *priv,
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u32 f_index)
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{
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u32 offset;
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u32 reg;
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offset = HFB_FLT_ENABLE_V3PLUS + (f_index < 32) * sizeof(u32);
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reg = bcmgenet_hfb_reg_readl(priv, offset);
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return !!(reg & (1 << (f_index % 32)));
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}
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static void bcmgenet_hfb_enable_filter(struct bcmgenet_priv *priv, u32 f_index)
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{
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u32 offset;
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u32 reg;
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offset = HFB_FLT_ENABLE_V3PLUS + (f_index < 32) * sizeof(u32);
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reg = bcmgenet_hfb_reg_readl(priv, offset);
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reg |= (1 << (f_index % 32));
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bcmgenet_hfb_reg_writel(priv, reg, offset);
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}
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static void bcmgenet_hfb_set_filter_rx_queue_mapping(struct bcmgenet_priv *priv,
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u32 f_index, u32 rx_queue)
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{
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u32 offset;
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u32 reg;
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offset = f_index / 8;
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reg = bcmgenet_rdma_readl(priv, DMA_INDEX2RING_0 + offset);
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reg &= ~(0xF << (4 * (f_index % 8)));
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reg |= ((rx_queue & 0xF) << (4 * (f_index % 8)));
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bcmgenet_rdma_writel(priv, reg, DMA_INDEX2RING_0 + offset);
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}
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static void bcmgenet_hfb_set_filter_length(struct bcmgenet_priv *priv,
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u32 f_index, u32 f_length)
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{
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u32 offset;
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u32 reg;
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offset = HFB_FLT_LEN_V3PLUS +
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((priv->hw_params->hfb_filter_cnt - 1 - f_index) / 4) *
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sizeof(u32);
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reg = bcmgenet_hfb_reg_readl(priv, offset);
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reg &= ~(0xFF << (8 * (f_index % 4)));
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reg |= ((f_length & 0xFF) << (8 * (f_index % 4)));
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bcmgenet_hfb_reg_writel(priv, reg, offset);
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}
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static int bcmgenet_hfb_find_unused_filter(struct bcmgenet_priv *priv)
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{
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u32 f_index;
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for (f_index = 0; f_index < priv->hw_params->hfb_filter_cnt; f_index++)
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if (!bcmgenet_hfb_is_filter_enabled(priv, f_index))
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return f_index;
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return -ENOMEM;
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}
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/* bcmgenet_hfb_add_filter
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*
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* Add new filter to Hardware Filter Block to match and direct Rx traffic to
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* desired Rx queue.
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*
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* f_data is an array of unsigned 32-bit integers where each 32-bit integer
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* provides filter data for 2 bytes (4 nibbles) of Rx frame:
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*
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* bits 31:20 - unused
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* bit 19 - nibble 0 match enable
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* bit 18 - nibble 1 match enable
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* bit 17 - nibble 2 match enable
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* bit 16 - nibble 3 match enable
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* bits 15:12 - nibble 0 data
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* bits 11:8 - nibble 1 data
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* bits 7:4 - nibble 2 data
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* bits 3:0 - nibble 3 data
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*
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* Example:
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* In order to match:
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* - Ethernet frame type = 0x0800 (IP)
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* - IP version field = 4
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* - IP protocol field = 0x11 (UDP)
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*
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* The following filter is needed:
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* u32 hfb_filter_ipv4_udp[] = {
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* Rx frame offset 0x00: 0x00000000, 0x00000000, 0x00000000, 0x00000000,
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* Rx frame offset 0x08: 0x00000000, 0x00000000, 0x000F0800, 0x00084000,
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* Rx frame offset 0x10: 0x00000000, 0x00000000, 0x00000000, 0x00030011,
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* };
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*
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* To add the filter to HFB and direct the traffic to Rx queue 0, call:
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* bcmgenet_hfb_add_filter(priv, hfb_filter_ipv4_udp,
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* ARRAY_SIZE(hfb_filter_ipv4_udp), 0);
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*/
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int bcmgenet_hfb_add_filter(struct bcmgenet_priv *priv, u32 *f_data,
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u32 f_length, u32 rx_queue)
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{
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int f_index;
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u32 i;
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f_index = bcmgenet_hfb_find_unused_filter(priv);
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if (f_index < 0)
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return -ENOMEM;
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if (f_length > priv->hw_params->hfb_filter_size)
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return -EINVAL;
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for (i = 0; i < f_length; i++)
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bcmgenet_hfb_writel(priv, f_data[i],
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(f_index * priv->hw_params->hfb_filter_size + i) *
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sizeof(u32));
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bcmgenet_hfb_set_filter_length(priv, f_index, 2 * f_length);
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bcmgenet_hfb_set_filter_rx_queue_mapping(priv, f_index, rx_queue);
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bcmgenet_hfb_enable_filter(priv, f_index);
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bcmgenet_hfb_reg_writel(priv, 0x1, HFB_CTRL);
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return 0;
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}
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/* bcmgenet_hfb_clear
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*
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* Clear Hardware Filter Block and disable all filtering.
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*/
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static void bcmgenet_hfb_clear(struct bcmgenet_priv *priv)
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{
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u32 i;
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bcmgenet_hfb_reg_writel(priv, 0x0, HFB_CTRL);
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bcmgenet_hfb_reg_writel(priv, 0x0, HFB_FLT_ENABLE_V3PLUS);
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bcmgenet_hfb_reg_writel(priv, 0x0, HFB_FLT_ENABLE_V3PLUS + 4);
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for (i = DMA_INDEX2RING_0; i <= DMA_INDEX2RING_7; i++)
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bcmgenet_rdma_writel(priv, 0x0, i);
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for (i = 0; i < (priv->hw_params->hfb_filter_cnt / 4); i++)
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bcmgenet_hfb_reg_writel(priv, 0x0,
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HFB_FLT_LEN_V3PLUS + i * sizeof(u32));
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for (i = 0; i < priv->hw_params->hfb_filter_cnt *
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priv->hw_params->hfb_filter_size; i++)
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bcmgenet_hfb_writel(priv, 0x0, i * sizeof(u32));
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}
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static void bcmgenet_hfb_init(struct bcmgenet_priv *priv)
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{
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if (GENET_IS_V1(priv) || GENET_IS_V2(priv))
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return;
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bcmgenet_hfb_clear(priv);
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}
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static int bcmgenet_begin(struct net_device *dev)
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{
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struct bcmgenet_priv *priv = netdev_priv(dev);
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@ -2759,160 +2913,6 @@ static void bcmgenet_enable_dma(struct bcmgenet_priv *priv, u32 dma_ctrl)
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bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
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}
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static bool bcmgenet_hfb_is_filter_enabled(struct bcmgenet_priv *priv,
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u32 f_index)
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{
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u32 offset;
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u32 reg;
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offset = HFB_FLT_ENABLE_V3PLUS + (f_index < 32) * sizeof(u32);
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reg = bcmgenet_hfb_reg_readl(priv, offset);
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return !!(reg & (1 << (f_index % 32)));
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}
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static void bcmgenet_hfb_enable_filter(struct bcmgenet_priv *priv, u32 f_index)
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{
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u32 offset;
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u32 reg;
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offset = HFB_FLT_ENABLE_V3PLUS + (f_index < 32) * sizeof(u32);
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reg = bcmgenet_hfb_reg_readl(priv, offset);
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reg |= (1 << (f_index % 32));
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bcmgenet_hfb_reg_writel(priv, reg, offset);
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}
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static void bcmgenet_hfb_set_filter_rx_queue_mapping(struct bcmgenet_priv *priv,
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u32 f_index, u32 rx_queue)
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{
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u32 offset;
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u32 reg;
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offset = f_index / 8;
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reg = bcmgenet_rdma_readl(priv, DMA_INDEX2RING_0 + offset);
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reg &= ~(0xF << (4 * (f_index % 8)));
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reg |= ((rx_queue & 0xF) << (4 * (f_index % 8)));
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bcmgenet_rdma_writel(priv, reg, DMA_INDEX2RING_0 + offset);
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}
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static void bcmgenet_hfb_set_filter_length(struct bcmgenet_priv *priv,
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u32 f_index, u32 f_length)
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{
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u32 offset;
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u32 reg;
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offset = HFB_FLT_LEN_V3PLUS +
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((priv->hw_params->hfb_filter_cnt - 1 - f_index) / 4) *
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sizeof(u32);
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reg = bcmgenet_hfb_reg_readl(priv, offset);
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reg &= ~(0xFF << (8 * (f_index % 4)));
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reg |= ((f_length & 0xFF) << (8 * (f_index % 4)));
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bcmgenet_hfb_reg_writel(priv, reg, offset);
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}
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static int bcmgenet_hfb_find_unused_filter(struct bcmgenet_priv *priv)
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{
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u32 f_index;
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for (f_index = 0; f_index < priv->hw_params->hfb_filter_cnt; f_index++)
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if (!bcmgenet_hfb_is_filter_enabled(priv, f_index))
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return f_index;
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return -ENOMEM;
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}
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/* bcmgenet_hfb_add_filter
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*
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* Add new filter to Hardware Filter Block to match and direct Rx traffic to
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* desired Rx queue.
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*
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* f_data is an array of unsigned 32-bit integers where each 32-bit integer
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* provides filter data for 2 bytes (4 nibbles) of Rx frame:
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*
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* bits 31:20 - unused
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* bit 19 - nibble 0 match enable
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* bit 18 - nibble 1 match enable
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* bit 17 - nibble 2 match enable
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* bit 16 - nibble 3 match enable
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* bits 15:12 - nibble 0 data
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* bits 11:8 - nibble 1 data
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* bits 7:4 - nibble 2 data
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* bits 3:0 - nibble 3 data
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*
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* Example:
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* In order to match:
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* - Ethernet frame type = 0x0800 (IP)
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* - IP version field = 4
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* - IP protocol field = 0x11 (UDP)
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*
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* The following filter is needed:
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* u32 hfb_filter_ipv4_udp[] = {
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* Rx frame offset 0x00: 0x00000000, 0x00000000, 0x00000000, 0x00000000,
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* Rx frame offset 0x08: 0x00000000, 0x00000000, 0x000F0800, 0x00084000,
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* Rx frame offset 0x10: 0x00000000, 0x00000000, 0x00000000, 0x00030011,
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* };
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*
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* To add the filter to HFB and direct the traffic to Rx queue 0, call:
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* bcmgenet_hfb_add_filter(priv, hfb_filter_ipv4_udp,
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* ARRAY_SIZE(hfb_filter_ipv4_udp), 0);
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*/
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int bcmgenet_hfb_add_filter(struct bcmgenet_priv *priv, u32 *f_data,
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u32 f_length, u32 rx_queue)
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{
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int f_index;
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u32 i;
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f_index = bcmgenet_hfb_find_unused_filter(priv);
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if (f_index < 0)
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return -ENOMEM;
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if (f_length > priv->hw_params->hfb_filter_size)
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return -EINVAL;
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for (i = 0; i < f_length; i++)
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bcmgenet_hfb_writel(priv, f_data[i],
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(f_index * priv->hw_params->hfb_filter_size + i) *
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sizeof(u32));
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bcmgenet_hfb_set_filter_length(priv, f_index, 2 * f_length);
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bcmgenet_hfb_set_filter_rx_queue_mapping(priv, f_index, rx_queue);
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bcmgenet_hfb_enable_filter(priv, f_index);
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bcmgenet_hfb_reg_writel(priv, 0x1, HFB_CTRL);
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return 0;
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}
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/* bcmgenet_hfb_clear
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*
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* Clear Hardware Filter Block and disable all filtering.
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*/
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static void bcmgenet_hfb_clear(struct bcmgenet_priv *priv)
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{
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u32 i;
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bcmgenet_hfb_reg_writel(priv, 0x0, HFB_CTRL);
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bcmgenet_hfb_reg_writel(priv, 0x0, HFB_FLT_ENABLE_V3PLUS);
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bcmgenet_hfb_reg_writel(priv, 0x0, HFB_FLT_ENABLE_V3PLUS + 4);
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for (i = DMA_INDEX2RING_0; i <= DMA_INDEX2RING_7; i++)
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bcmgenet_rdma_writel(priv, 0x0, i);
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for (i = 0; i < (priv->hw_params->hfb_filter_cnt / 4); i++)
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bcmgenet_hfb_reg_writel(priv, 0x0,
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HFB_FLT_LEN_V3PLUS + i * sizeof(u32));
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for (i = 0; i < priv->hw_params->hfb_filter_cnt *
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priv->hw_params->hfb_filter_size; i++)
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bcmgenet_hfb_writel(priv, 0x0, i * sizeof(u32));
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}
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static void bcmgenet_hfb_init(struct bcmgenet_priv *priv)
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{
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if (GENET_IS_V1(priv) || GENET_IS_V2(priv))
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return;
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bcmgenet_hfb_clear(priv);
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}
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static void bcmgenet_netif_start(struct net_device *dev)
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{
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struct bcmgenet_priv *priv = netdev_priv(dev);
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