Add support of MediaTek mt8186 to SOF
Merge series from Tinghan Shen <tinghan.shen@mediatek.com>: Add support of MediaTek mt8186 SoC DSP to SOF.
This commit is contained in:
Mark Brown
Коммит
85780eb54d
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@ -21,6 +21,15 @@ config SND_SOC_SOF_MTK_COMMON
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This option is not user-selectable but automagically handled by
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'select' statements at a higher level
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config SND_SOC_SOF_MT8186
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tristate "SOF support for MT8186 audio DSP"
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select SND_SOC_SOF_MTK_COMMON
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help
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This adds support for Sound Open Firmware for Mediatek platforms
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using the mt8186 processors.
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Say Y if you have such a device.
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If unsure select "N".
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config SND_SOC_SOF_MT8195
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tristate "SOF support for MT8195 audio DSP"
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select SND_SOC_SOF_MTK_COMMON
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@ -1,2 +1,3 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
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obj-$(CONFIG_SND_SOC_SOF_MT8195) += mt8195/
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obj-$(CONFIG_SND_SOC_SOF_MT8186) += mt8186/
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@ -29,6 +29,14 @@ struct mtk_adsp_chip_info {
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void __iomem *shared_dram; /* part of va_dram */
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phys_addr_t adsp_bootup_addr;
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int dram_offset; /*dram offset between system and dsp view*/
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phys_addr_t pa_secreg;
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u32 secregsize;
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void __iomem *va_secreg;
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phys_addr_t pa_busreg;
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u32 busregsize;
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void __iomem *va_busreg;
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};
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struct adsp_priv {
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@ -0,0 +1,4 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
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snd-sof-mt8186-objs := mt8186.o mt8186-clk.o mt8186-loader.o
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obj-$(CONFIG_SND_SOC_SOF_MT8186) += snd-sof-mt8186.o
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@ -0,0 +1,101 @@
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// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
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//
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// Copyright(c) 2022 Mediatek Corporation. All rights reserved.
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//
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// Author: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
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// Tinghan Shen <tinghan.shen@mediatek.com>
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//
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// Hardware interface for mt8186 DSP clock
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#include <linux/clk.h>
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#include <linux/pm_runtime.h>
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#include <linux/io.h>
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#include "../../sof-audio.h"
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#include "../../ops.h"
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#include "../adsp_helper.h"
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#include "mt8186.h"
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#include "mt8186-clk.h"
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static const char *adsp_clks[ADSP_CLK_MAX] = {
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[CLK_TOP_AUDIODSP] = "audiodsp_sel",
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[CLK_TOP_ADSP_BUS] = "adsp_bus_sel",
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};
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int mt8186_adsp_init_clock(struct snd_sof_dev *sdev)
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{
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struct adsp_priv *priv = sdev->pdata->hw_pdata;
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struct device *dev = sdev->dev;
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int i;
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priv->clk = devm_kcalloc(dev, ADSP_CLK_MAX, sizeof(*priv->clk), GFP_KERNEL);
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if (!priv->clk)
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return -ENOMEM;
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for (i = 0; i < ADSP_CLK_MAX; i++) {
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priv->clk[i] = devm_clk_get(dev, adsp_clks[i]);
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if (IS_ERR(priv->clk[i]))
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return PTR_ERR(priv->clk[i]);
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}
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return 0;
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}
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static int adsp_enable_all_clock(struct snd_sof_dev *sdev)
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{
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struct adsp_priv *priv = sdev->pdata->hw_pdata;
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struct device *dev = sdev->dev;
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int ret;
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ret = clk_prepare_enable(priv->clk[CLK_TOP_AUDIODSP]);
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if (ret) {
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dev_err(dev, "%s clk_prepare_enable(audiodsp) fail %d\n",
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__func__, ret);
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return ret;
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}
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ret = clk_prepare_enable(priv->clk[CLK_TOP_ADSP_BUS]);
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if (ret) {
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dev_err(dev, "%s clk_prepare_enable(adsp_bus) fail %d\n",
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__func__, ret);
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clk_disable_unprepare(priv->clk[CLK_TOP_AUDIODSP]);
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return ret;
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}
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return 0;
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}
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static void adsp_disable_all_clock(struct snd_sof_dev *sdev)
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{
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struct adsp_priv *priv = sdev->pdata->hw_pdata;
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clk_disable_unprepare(priv->clk[CLK_TOP_ADSP_BUS]);
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clk_disable_unprepare(priv->clk[CLK_TOP_AUDIODSP]);
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}
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int adsp_clock_on(struct snd_sof_dev *sdev)
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{
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struct device *dev = sdev->dev;
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int ret;
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ret = adsp_enable_all_clock(sdev);
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if (ret) {
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dev_err(dev, "failed to adsp_enable_clock: %d\n", ret);
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return ret;
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}
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snd_sof_dsp_write(sdev, DSP_REG_BAR, ADSP_CK_EN,
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UART_EN | DMA_EN | TIMER_EN | COREDBG_EN | CORE_CLK_EN);
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snd_sof_dsp_write(sdev, DSP_REG_BAR, ADSP_UART_CTRL,
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UART_BCLK_CG | UART_RSTN);
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return 0;
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}
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void adsp_clock_off(struct snd_sof_dev *sdev)
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{
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snd_sof_dsp_write(sdev, DSP_REG_BAR, ADSP_CK_EN, 0);
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snd_sof_dsp_write(sdev, DSP_REG_BAR, ADSP_UART_CTRL, 0);
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adsp_disable_all_clock(sdev);
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}
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@ -0,0 +1,24 @@
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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
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/*
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* Copyright (c) 2022 MediaTek Corporation. All rights reserved.
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*
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* Header file for the mt8186 DSP clock definition
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*/
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#ifndef __MT8186_CLK_H
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#define __MT8186_CLK_H
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struct snd_sof_dev;
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/* DSP clock */
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enum adsp_clk_id {
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CLK_TOP_AUDIODSP,
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CLK_TOP_ADSP_BUS,
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ADSP_CLK_MAX
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};
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int mt8186_adsp_init_clock(struct snd_sof_dev *sdev);
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int adsp_clock_on(struct snd_sof_dev *sdev);
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void adsp_clock_off(struct snd_sof_dev *sdev);
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#endif
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@ -0,0 +1,53 @@
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// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
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//
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// Copyright (c) 2022 Mediatek Corporation. All rights reserved.
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//
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// Author: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
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// Tinghan Shen <tinghan.shen@mediatek.com>
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//
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// Hardware interface for mt8186 DSP code loader
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#include <sound/sof.h>
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#include "mt8186.h"
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#include "../../ops.h"
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void sof_hifixdsp_boot_sequence(struct snd_sof_dev *sdev, u32 boot_addr)
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{
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/* set RUNSTALL to stop core */
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snd_sof_dsp_update_bits(sdev, DSP_REG_BAR, ADSP_HIFI_IO_CONFIG,
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RUNSTALL, RUNSTALL);
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/* set core boot address */
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snd_sof_dsp_write(sdev, DSP_SECREG_BAR, ADSP_ALTVEC_C0, boot_addr);
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snd_sof_dsp_write(sdev, DSP_SECREG_BAR, ADSP_ALTVECSEL, ADSP_ALTVECSEL_C0);
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/* assert core reset */
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snd_sof_dsp_update_bits(sdev, DSP_REG_BAR, ADSP_CFGREG_SW_RSTN,
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SW_RSTN_C0 | SW_DBG_RSTN_C0,
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SW_RSTN_C0 | SW_DBG_RSTN_C0);
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/* hardware requirement */
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udelay(1);
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/* release core reset */
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snd_sof_dsp_update_bits(sdev, DSP_REG_BAR, ADSP_CFGREG_SW_RSTN,
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SW_RSTN_C0 | SW_DBG_RSTN_C0,
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0);
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/* clear RUNSTALL (bit31) to start core */
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snd_sof_dsp_update_bits(sdev, DSP_REG_BAR, ADSP_HIFI_IO_CONFIG,
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RUNSTALL, 0);
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}
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void sof_hifixdsp_shutdown(struct snd_sof_dev *sdev)
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{
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/* set RUNSTALL to stop core */
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snd_sof_dsp_update_bits(sdev, DSP_REG_BAR, ADSP_HIFI_IO_CONFIG,
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RUNSTALL, RUNSTALL);
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/* assert core reset */
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snd_sof_dsp_update_bits(sdev, DSP_REG_BAR, ADSP_CFGREG_SW_RSTN,
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SW_RSTN_C0 | SW_DBG_RSTN_C0,
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SW_RSTN_C0 | SW_DBG_RSTN_C0);
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}
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@ -0,0 +1,413 @@
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// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
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//
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// Copyright(c) 2022 Mediatek Inc. All rights reserved.
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//
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// Author: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
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// Tinghan Shen <tinghan.shen@mediatek.com>
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/*
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* Hardware interface for audio DSP on mt8186
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*/
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#include <linux/delay.h>
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#include <linux/firmware.h>
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#include <linux/io.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <linux/of_platform.h>
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#include <linux/of_reserved_mem.h>
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#include <linux/module.h>
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#include <sound/sof.h>
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#include <sound/sof/xtensa.h>
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#include "../../ops.h"
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#include "../../sof-of-dev.h"
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#include "../../sof-audio.h"
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#include "../adsp_helper.h"
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#include "mt8186.h"
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#include "mt8186-clk.h"
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static int platform_parse_resource(struct platform_device *pdev, void *data)
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{
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struct resource *mmio;
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struct resource res;
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struct device_node *mem_region;
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struct device *dev = &pdev->dev;
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struct mtk_adsp_chip_info *adsp = data;
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int ret;
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mem_region = of_parse_phandle(dev->of_node, "memory-region", 0);
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if (!mem_region) {
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dev_err(dev, "no dma memory-region phandle\n");
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return -ENODEV;
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}
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ret = of_address_to_resource(mem_region, 0, &res);
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of_node_put(mem_region);
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if (ret) {
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dev_err(dev, "of_address_to_resource dma failed\n");
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return ret;
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}
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dev_dbg(dev, "DMA %pR\n", &res);
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ret = of_reserved_mem_device_init(dev);
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if (ret) {
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dev_err(dev, "of_reserved_mem_device_init failed\n");
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return ret;
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}
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mem_region = of_parse_phandle(dev->of_node, "memory-region", 1);
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if (!mem_region) {
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dev_err(dev, "no memory-region sysmem phandle\n");
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return -ENODEV;
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}
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ret = of_address_to_resource(mem_region, 0, &res);
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of_node_put(mem_region);
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if (ret) {
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dev_err(dev, "of_address_to_resource sysmem failed\n");
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return ret;
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}
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adsp->pa_dram = (phys_addr_t)res.start;
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if (adsp->pa_dram & DRAM_REMAP_MASK) {
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dev_err(dev, "adsp memory(%#x) is not 4K-aligned\n",
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(u32)adsp->pa_dram);
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return -EINVAL;
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}
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adsp->dramsize = resource_size(&res);
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if (adsp->dramsize < TOTAL_SIZE_SHARED_DRAM_FROM_TAIL) {
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dev_err(dev, "adsp memory(%#x) is not enough for share\n",
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adsp->dramsize);
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return -EINVAL;
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}
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dev_dbg(dev, "dram pbase=%pa size=%#x\n", &adsp->pa_dram, adsp->dramsize);
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mmio = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cfg");
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if (!mmio) {
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dev_err(dev, "no ADSP-CFG register resource\n");
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return -ENXIO;
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}
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adsp->va_cfgreg = devm_ioremap_resource(dev, mmio);
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if (IS_ERR(adsp->va_cfgreg))
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return PTR_ERR(adsp->va_cfgreg);
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adsp->pa_cfgreg = (phys_addr_t)mmio->start;
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adsp->cfgregsize = resource_size(mmio);
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dev_dbg(dev, "cfgreg pbase=%pa size=%#x\n", &adsp->pa_cfgreg, adsp->cfgregsize);
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mmio = platform_get_resource_byname(pdev, IORESOURCE_MEM, "sram");
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if (!mmio) {
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dev_err(dev, "no SRAM resource\n");
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return -ENXIO;
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}
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adsp->pa_sram = (phys_addr_t)mmio->start;
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adsp->sramsize = resource_size(mmio);
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dev_dbg(dev, "sram pbase=%pa size=%#x\n", &adsp->pa_sram, adsp->sramsize);
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mmio = platform_get_resource_byname(pdev, IORESOURCE_MEM, "sec");
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if (!mmio) {
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dev_err(dev, "no SEC register resource\n");
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return -ENXIO;
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}
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adsp->va_secreg = devm_ioremap_resource(dev, mmio);
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if (IS_ERR(adsp->va_secreg))
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return PTR_ERR(adsp->va_secreg);
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adsp->pa_secreg = (phys_addr_t)mmio->start;
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adsp->secregsize = resource_size(mmio);
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dev_dbg(dev, "secreg pbase=%pa size=%#x\n", &adsp->pa_secreg, adsp->secregsize);
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mmio = platform_get_resource_byname(pdev, IORESOURCE_MEM, "bus");
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if (!mmio) {
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dev_err(dev, "no BUS register resource\n");
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return -ENXIO;
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}
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adsp->va_busreg = devm_ioremap_resource(dev, mmio);
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if (IS_ERR(adsp->va_busreg))
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return PTR_ERR(adsp->va_busreg);
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adsp->pa_busreg = (phys_addr_t)mmio->start;
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adsp->busregsize = resource_size(mmio);
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dev_dbg(dev, "busreg pbase=%pa size=%#x\n", &adsp->pa_busreg, adsp->busregsize);
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return 0;
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}
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static void adsp_sram_power_on(struct snd_sof_dev *sdev)
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{
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snd_sof_dsp_update_bits(sdev, DSP_BUSREG_BAR, ADSP_SRAM_POOL_CON,
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DSP_SRAM_POOL_PD_MASK, 0);
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}
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static void adsp_sram_power_off(struct snd_sof_dev *sdev)
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{
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snd_sof_dsp_update_bits(sdev, DSP_BUSREG_BAR, ADSP_SRAM_POOL_CON,
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DSP_SRAM_POOL_PD_MASK, DSP_SRAM_POOL_PD_MASK);
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}
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/* Init the basic DSP DRAM address */
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static int adsp_memory_remap_init(struct snd_sof_dev *sdev, struct mtk_adsp_chip_info *adsp)
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{
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u32 offset;
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offset = adsp->pa_dram - DRAM_PHYS_BASE_FROM_DSP_VIEW;
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adsp->dram_offset = offset;
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offset >>= DRAM_REMAP_SHIFT;
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dev_dbg(sdev->dev, "adsp->pa_dram %pa, offset %#x\n", &adsp->pa_dram, offset);
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snd_sof_dsp_write(sdev, DSP_BUSREG_BAR, DSP_C0_EMI_MAP_ADDR, offset);
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snd_sof_dsp_write(sdev, DSP_BUSREG_BAR, DSP_C0_DMAEMI_MAP_ADDR, offset);
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if (offset != snd_sof_dsp_read(sdev, DSP_BUSREG_BAR, DSP_C0_EMI_MAP_ADDR) ||
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offset != snd_sof_dsp_read(sdev, DSP_BUSREG_BAR, DSP_C0_DMAEMI_MAP_ADDR)) {
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dev_err(sdev->dev, "emi remap fail\n");
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return -EIO;
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}
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return 0;
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}
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static int adsp_shared_base_ioremap(struct platform_device *pdev, void *data)
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{
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struct device *dev = &pdev->dev;
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struct mtk_adsp_chip_info *adsp = data;
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u32 shared_size;
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/* remap shared-dram base to be non-cachable */
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shared_size = TOTAL_SIZE_SHARED_DRAM_FROM_TAIL;
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adsp->pa_shared_dram = adsp->pa_dram + adsp->dramsize - shared_size;
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if (adsp->va_dram) {
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adsp->shared_dram = adsp->va_dram + DSP_DRAM_SIZE - shared_size;
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} else {
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adsp->shared_dram = devm_ioremap(dev, adsp->pa_shared_dram,
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shared_size);
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if (!adsp->shared_dram) {
|
||||
dev_err(dev, "ioremap failed for shared DRAM\n");
|
||||
return -ENOMEM;
|
||||
}
|
||||
}
|
||||
dev_dbg(dev, "shared-dram vbase=%p, phy addr :%pa, size=%#x\n",
|
||||
adsp->shared_dram, &adsp->pa_shared_dram, shared_size);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int mt8186_run(struct snd_sof_dev *sdev)
|
||||
{
|
||||
u32 adsp_bootup_addr;
|
||||
|
||||
adsp_bootup_addr = SRAM_PHYS_BASE_FROM_DSP_VIEW;
|
||||
dev_dbg(sdev->dev, "HIFIxDSP boot from base : 0x%08X\n", adsp_bootup_addr);
|
||||
sof_hifixdsp_boot_sequence(sdev, adsp_bootup_addr);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int mt8186_dsp_probe(struct snd_sof_dev *sdev)
|
||||
{
|
||||
struct platform_device *pdev = container_of(sdev->dev, struct platform_device, dev);
|
||||
struct adsp_priv *priv;
|
||||
int ret;
|
||||
|
||||
priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
|
||||
if (!priv)
|
||||
return -ENOMEM;
|
||||
|
||||
sdev->pdata->hw_pdata = priv;
|
||||
priv->dev = sdev->dev;
|
||||
priv->sdev = sdev;
|
||||
|
||||
priv->adsp = devm_kzalloc(&pdev->dev, sizeof(struct mtk_adsp_chip_info), GFP_KERNEL);
|
||||
if (!priv->adsp)
|
||||
return -ENOMEM;
|
||||
|
||||
ret = platform_parse_resource(pdev, priv->adsp);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
sdev->bar[SOF_FW_BLK_TYPE_IRAM] = devm_ioremap(sdev->dev,
|
||||
priv->adsp->pa_sram,
|
||||
priv->adsp->sramsize);
|
||||
if (!sdev->bar[SOF_FW_BLK_TYPE_IRAM]) {
|
||||
dev_err(sdev->dev, "failed to ioremap base %pa size %#x\n",
|
||||
&priv->adsp->pa_sram, priv->adsp->sramsize);
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
sdev->bar[SOF_FW_BLK_TYPE_SRAM] = devm_ioremap_wc(sdev->dev,
|
||||
priv->adsp->pa_dram,
|
||||
priv->adsp->dramsize);
|
||||
if (!sdev->bar[SOF_FW_BLK_TYPE_SRAM]) {
|
||||
dev_err(sdev->dev, "failed to ioremap base %pa size %#x\n",
|
||||
&priv->adsp->pa_dram, priv->adsp->dramsize);
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
priv->adsp->va_dram = sdev->bar[SOF_FW_BLK_TYPE_SRAM];
|
||||
|
||||
ret = adsp_shared_base_ioremap(pdev, priv->adsp);
|
||||
if (ret) {
|
||||
dev_err(sdev->dev, "adsp_shared_base_ioremap fail!\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
sdev->bar[DSP_REG_BAR] = priv->adsp->va_cfgreg;
|
||||
sdev->bar[DSP_SECREG_BAR] = priv->adsp->va_secreg;
|
||||
sdev->bar[DSP_BUSREG_BAR] = priv->adsp->va_busreg;
|
||||
|
||||
sdev->mmio_bar = SOF_FW_BLK_TYPE_SRAM;
|
||||
sdev->mailbox_bar = SOF_FW_BLK_TYPE_SRAM;
|
||||
|
||||
ret = adsp_memory_remap_init(sdev, priv->adsp);
|
||||
if (ret) {
|
||||
dev_err(sdev->dev, "adsp_memory_remap_init fail!\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* enable adsp clock before touching registers */
|
||||
ret = mt8186_adsp_init_clock(sdev);
|
||||
if (ret) {
|
||||
dev_err(sdev->dev, "mt8186_adsp_init_clock failed\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = adsp_clock_on(sdev);
|
||||
if (ret) {
|
||||
dev_err(sdev->dev, "adsp_clock_on fail!\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
adsp_sram_power_on(sdev);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int mt8186_dsp_remove(struct snd_sof_dev *sdev)
|
||||
{
|
||||
sof_hifixdsp_shutdown(sdev);
|
||||
adsp_sram_power_off(sdev);
|
||||
adsp_clock_off(sdev);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int mt8186_dsp_suspend(struct snd_sof_dev *sdev, u32 target_state)
|
||||
{
|
||||
sof_hifixdsp_shutdown(sdev);
|
||||
adsp_sram_power_off(sdev);
|
||||
adsp_clock_off(sdev);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int mt8186_dsp_resume(struct snd_sof_dev *sdev)
|
||||
{
|
||||
int ret;
|
||||
|
||||
ret = adsp_clock_on(sdev);
|
||||
if (ret) {
|
||||
dev_err(sdev->dev, "adsp_clock_on fail!\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
adsp_sram_power_on(sdev);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* on mt8186 there is 1 to 1 match between type and BAR idx */
|
||||
static int mt8186_get_bar_index(struct snd_sof_dev *sdev, u32 type)
|
||||
{
|
||||
return type;
|
||||
}
|
||||
|
||||
/* mt8186 ops */
|
||||
static struct snd_sof_dsp_ops sof_mt8186_ops = {
|
||||
/* probe and remove */
|
||||
.probe = mt8186_dsp_probe,
|
||||
.remove = mt8186_dsp_remove,
|
||||
|
||||
/* DSP core boot */
|
||||
.run = mt8186_run,
|
||||
|
||||
/* Block IO */
|
||||
.block_read = sof_block_read,
|
||||
.block_write = sof_block_write,
|
||||
|
||||
/* Register IO */
|
||||
.write = sof_io_write,
|
||||
.read = sof_io_read,
|
||||
.write64 = sof_io_write64,
|
||||
.read64 = sof_io_read64,
|
||||
|
||||
/* misc */
|
||||
.get_bar_index = mt8186_get_bar_index,
|
||||
|
||||
/* firmware loading */
|
||||
.load_firmware = snd_sof_load_firmware_memcpy,
|
||||
|
||||
/* Firmware ops */
|
||||
.dsp_arch_ops = &sof_xtensa_arch_ops,
|
||||
|
||||
/* PM */
|
||||
.suspend = mt8186_dsp_suspend,
|
||||
.resume = mt8186_dsp_resume,
|
||||
|
||||
/* ALSA HW info flags */
|
||||
.hw_info = SNDRV_PCM_INFO_MMAP |
|
||||
SNDRV_PCM_INFO_MMAP_VALID |
|
||||
SNDRV_PCM_INFO_INTERLEAVED |
|
||||
SNDRV_PCM_INFO_PAUSE |
|
||||
SNDRV_PCM_INFO_NO_PERIOD_WAKEUP,
|
||||
};
|
||||
|
||||
static const struct sof_dev_desc sof_of_mt8186_desc = {
|
||||
.ipc_supported_mask = BIT(SOF_IPC),
|
||||
.ipc_default = SOF_IPC,
|
||||
.default_fw_path = {
|
||||
[SOF_IPC] = "mediatek/sof",
|
||||
},
|
||||
.default_tplg_path = {
|
||||
[SOF_IPC] = "mediatek/sof-tplg",
|
||||
},
|
||||
.default_fw_filename = {
|
||||
[SOF_IPC] = "sof-mt8186.ri",
|
||||
},
|
||||
.nocodec_tplg_filename = "sof-mt8186-nocodec.tplg",
|
||||
.ops = &sof_mt8186_ops,
|
||||
};
|
||||
|
||||
static const struct of_device_id sof_of_mt8186_ids[] = {
|
||||
{ .compatible = "mediatek,mt8186-dsp", .data = &sof_of_mt8186_desc},
|
||||
{ }
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, sof_of_mt8186_ids);
|
||||
|
||||
/* DT driver definition */
|
||||
static struct platform_driver snd_sof_of_mt8186_driver = {
|
||||
.probe = sof_of_probe,
|
||||
.remove = sof_of_remove,
|
||||
.driver = {
|
||||
.name = "sof-audio-of-mt8186",
|
||||
.pm = &sof_of_pm,
|
||||
.of_match_table = sof_of_mt8186_ids,
|
||||
},
|
||||
};
|
||||
module_platform_driver(snd_sof_of_mt8186_driver);
|
||||
|
||||
MODULE_IMPORT_NS(SND_SOC_SOF_XTENSA);
|
||||
MODULE_IMPORT_NS(SND_SOC_SOF_MTK_COMMON);
|
||||
MODULE_LICENSE("Dual BSD/GPL");
|
||||
|
|
@ -0,0 +1,80 @@
|
|||
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
|
||||
|
||||
/*
|
||||
* Copyright (c) 2022 MediaTek Corporation. All rights reserved.
|
||||
*
|
||||
* Header file for the mt8186 DSP register definition
|
||||
*/
|
||||
|
||||
#ifndef __MT8186_H
|
||||
#define __MT8186_H
|
||||
|
||||
struct mtk_adsp_chip_info;
|
||||
struct snd_sof_dev;
|
||||
|
||||
#define DSP_REG_BAR 4
|
||||
#define DSP_SECREG_BAR 5
|
||||
#define DSP_BUSREG_BAR 6
|
||||
|
||||
/*****************************************************************************
|
||||
* R E G I S T E R TABLE
|
||||
*****************************************************************************/
|
||||
/* dsp cfg */
|
||||
#define ADSP_CFGREG_SW_RSTN 0x0000
|
||||
#define SW_DBG_RSTN_C0 BIT(0)
|
||||
#define SW_RSTN_C0 BIT(4)
|
||||
#define ADSP_HIFI_IO_CONFIG 0x000C
|
||||
#define TRACEMEMREADY BIT(15)
|
||||
#define RUNSTALL BIT(31)
|
||||
#define ADSP_IRQ_MASK 0x0030
|
||||
#define ADSP_DVFSRC_REQ 0x0040
|
||||
#define ADSP_DDREN_REQ_0 0x0044
|
||||
#define ADSP_SEMAPHORE 0x0064
|
||||
#define ADSP_WDT_CON_C0 0x007C
|
||||
#define ADSP_MBOX_IRQ_EN 0x009C
|
||||
#define DSP_MBOX0_IRQ_EN BIT(0)
|
||||
#define DSP_MBOX1_IRQ_EN BIT(1)
|
||||
#define DSP_MBOX2_IRQ_EN BIT(2)
|
||||
#define DSP_MBOX3_IRQ_EN BIT(3)
|
||||
#define DSP_MBOX4_IRQ_EN BIT(4)
|
||||
#define DSP_PDEBUGPC 0x013C
|
||||
#define ADSP_CK_EN 0x1000
|
||||
#define CORE_CLK_EN BIT(0)
|
||||
#define COREDBG_EN BIT(1)
|
||||
#define TIMER_EN BIT(3)
|
||||
#define DMA_EN BIT(4)
|
||||
#define UART_EN BIT(5)
|
||||
#define ADSP_UART_CTRL 0x1010
|
||||
#define UART_BCLK_CG BIT(0)
|
||||
#define UART_RSTN BIT(3)
|
||||
|
||||
/* dsp sec */
|
||||
#define ADSP_PRID 0x0
|
||||
#define ADSP_ALTVEC_C0 0x04
|
||||
#define ADSP_ALTVECSEL 0x0C
|
||||
#define ADSP_ALTVECSEL_C0 BIT(1)
|
||||
|
||||
/* dsp bus */
|
||||
#define ADSP_SRAM_POOL_CON 0x190
|
||||
#define DSP_SRAM_POOL_PD_MASK 0xF00F /* [0:3] and [12:15] */
|
||||
#define DSP_C0_EMI_MAP_ADDR 0xA00 /* ADSP Core0 To EMI Address Remap */
|
||||
#define DSP_C0_DMAEMI_MAP_ADDR 0xA08 /* DMA0 To EMI Address Remap */
|
||||
|
||||
/* DSP memories */
|
||||
#define MBOX_OFFSET 0x500000 /* DRAM */
|
||||
#define MBOX_SIZE 0x1000 /* consistent with which in memory.h of sof fw */
|
||||
#define DSP_DRAM_SIZE 0xA00000 /* 16M */
|
||||
|
||||
/*remap dram between AP and DSP view, 4KB aligned*/
|
||||
#define SRAM_PHYS_BASE_FROM_DSP_VIEW 0x4E100000 /* MT8186 DSP view */
|
||||
#define DRAM_PHYS_BASE_FROM_DSP_VIEW 0x60000000 /* MT8186 DSP view */
|
||||
#define DRAM_REMAP_SHIFT 12
|
||||
#define DRAM_REMAP_MASK 0xFFF
|
||||
|
||||
#define SIZE_SHARED_DRAM_DL 0x40000 /*Shared buffer for Downlink*/
|
||||
#define SIZE_SHARED_DRAM_UL 0x40000 /*Shared buffer for Uplink*/
|
||||
#define TOTAL_SIZE_SHARED_DRAM_FROM_TAIL (SIZE_SHARED_DRAM_DL + SIZE_SHARED_DRAM_UL)
|
||||
|
||||
void sof_hifixdsp_boot_sequence(struct snd_sof_dev *sdev, u32 boot_addr);
|
||||
void sof_hifixdsp_shutdown(struct snd_sof_dev *sdev);
|
||||
#endif
|
||||
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