arm: vt8500: clk: Add Common Clock Framework support
This patch adds common clock framework support for arch-vt8500. Support for PLL and device clocks on VT8500, WM8505 and WM8650 are included. Signed-off-by: Tony Prisk <linux@prisktech.co.nz> Acked-by: Mike Turquette <mturquette@linaro.org>
This commit is contained in:
Tony Prisk
Родитель
e7b995371f
Коммит
85814d69e6
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@ -10,6 +10,7 @@ obj-$(CONFIG_ARCH_SOCFPGA) += socfpga/
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obj-$(CONFIG_PLAT_SPEAR) += spear/
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obj-$(CONFIG_ARCH_U300) += clk-u300.o
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obj-$(CONFIG_ARCH_INTEGRATOR) += versatile/
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obj-$(CONFIG_ARCH_VT8500) += clk-vt8500.o
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# Chip specific
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obj-$(CONFIG_COMMON_CLK_WM831X) += clk-wm831x.o
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@ -0,0 +1,510 @@
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/*
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* Clock implementation for VIA/Wondermedia SoC's
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* Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz>
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#include <linux/io.h>
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#include <linux/of.h>
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#include <linux/slab.h>
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#include <linux/bitops.h>
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#include <linux/clkdev.h>
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#include <linux/clk-provider.h>
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/* All clocks share the same lock as none can be changed concurrently */
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static DEFINE_SPINLOCK(_lock);
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struct clk_device {
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struct clk_hw hw;
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void __iomem *div_reg;
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unsigned int div_mask;
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void __iomem *en_reg;
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int en_bit;
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spinlock_t *lock;
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};
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/*
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* Add new PLL_TYPE_x definitions here as required. Use the first known model
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* to support the new type as the name.
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* Add case statements to vtwm_pll_recalc_rate(), vtwm_pll_round_round() and
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* vtwm_pll_set_rate() to handle the new PLL_TYPE_x
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*/
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#define PLL_TYPE_VT8500 0
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#define PLL_TYPE_WM8650 1
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struct clk_pll {
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struct clk_hw hw;
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void __iomem *reg;
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spinlock_t *lock;
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int type;
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};
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static void __iomem *pmc_base;
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#define to_clk_device(_hw) container_of(_hw, struct clk_device, hw)
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#define VT8500_PMC_BUSY_MASK 0x18
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static void vt8500_pmc_wait_busy(void)
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{
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while (readl(pmc_base) & VT8500_PMC_BUSY_MASK)
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cpu_relax();
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}
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static int vt8500_dclk_enable(struct clk_hw *hw)
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{
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struct clk_device *cdev = to_clk_device(hw);
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u32 en_val;
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unsigned long flags = 0;
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spin_lock_irqsave(cdev->lock, flags);
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en_val = readl(cdev->en_reg);
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en_val |= BIT(cdev->en_bit);
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writel(en_val, cdev->en_reg);
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spin_unlock_irqrestore(cdev->lock, flags);
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return 0;
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}
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static void vt8500_dclk_disable(struct clk_hw *hw)
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{
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struct clk_device *cdev = to_clk_device(hw);
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u32 en_val;
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unsigned long flags = 0;
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spin_lock_irqsave(cdev->lock, flags);
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en_val = readl(cdev->en_reg);
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en_val &= ~BIT(cdev->en_bit);
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writel(en_val, cdev->en_reg);
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spin_unlock_irqrestore(cdev->lock, flags);
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}
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static int vt8500_dclk_is_enabled(struct clk_hw *hw)
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{
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struct clk_device *cdev = to_clk_device(hw);
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u32 en_val = (readl(cdev->en_reg) & BIT(cdev->en_bit));
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return en_val ? 1 : 0;
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}
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static unsigned long vt8500_dclk_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct clk_device *cdev = to_clk_device(hw);
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u32 div = readl(cdev->div_reg) & cdev->div_mask;
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/* Special case for SDMMC devices */
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if ((cdev->div_mask == 0x3F) && (div & BIT(5)))
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div = 64 * (div & 0x1f);
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/* div == 0 is actually the highest divisor */
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if (div == 0)
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div = (cdev->div_mask + 1);
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return parent_rate / div;
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}
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static long vt8500_dclk_round_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long *prate)
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{
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u32 divisor = *prate / rate;
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return *prate / divisor;
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}
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static int vt8500_dclk_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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struct clk_device *cdev = to_clk_device(hw);
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u32 divisor = parent_rate / rate;
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unsigned long flags = 0;
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if (divisor == cdev->div_mask + 1)
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divisor = 0;
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if (divisor > cdev->div_mask) {
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pr_err("%s: invalid divisor for clock\n", __func__);
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return -EINVAL;
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}
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spin_lock_irqsave(cdev->lock, flags);
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vt8500_pmc_wait_busy();
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writel(divisor, cdev->div_reg);
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vt8500_pmc_wait_busy();
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spin_lock_irqsave(cdev->lock, flags);
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return 0;
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}
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static const struct clk_ops vt8500_gated_clk_ops = {
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.enable = vt8500_dclk_enable,
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.disable = vt8500_dclk_disable,
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.is_enabled = vt8500_dclk_is_enabled,
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};
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static const struct clk_ops vt8500_divisor_clk_ops = {
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.round_rate = vt8500_dclk_round_rate,
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.set_rate = vt8500_dclk_set_rate,
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.recalc_rate = vt8500_dclk_recalc_rate,
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};
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static const struct clk_ops vt8500_gated_divisor_clk_ops = {
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.enable = vt8500_dclk_enable,
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.disable = vt8500_dclk_disable,
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.is_enabled = vt8500_dclk_is_enabled,
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.round_rate = vt8500_dclk_round_rate,
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.set_rate = vt8500_dclk_set_rate,
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.recalc_rate = vt8500_dclk_recalc_rate,
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};
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#define CLK_INIT_GATED BIT(0)
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#define CLK_INIT_DIVISOR BIT(1)
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#define CLK_INIT_GATED_DIVISOR (CLK_INIT_DIVISOR | CLK_INIT_GATED)
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static __init void vtwm_device_clk_init(struct device_node *node)
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{
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u32 en_reg, div_reg;
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struct clk *clk;
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struct clk_device *dev_clk;
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const char *clk_name = node->name;
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const char *parent_name;
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struct clk_init_data init;
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int rc;
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int clk_init_flags = 0;
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dev_clk = kzalloc(sizeof(*dev_clk), GFP_KERNEL);
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if (WARN_ON(!dev_clk))
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return;
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dev_clk->lock = &_lock;
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rc = of_property_read_u32(node, "enable-reg", &en_reg);
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if (!rc) {
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dev_clk->en_reg = pmc_base + en_reg;
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rc = of_property_read_u32(node, "enable-bit", &dev_clk->en_bit);
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if (rc) {
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pr_err("%s: enable-bit property required for gated clock\n",
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__func__);
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return;
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}
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clk_init_flags |= CLK_INIT_GATED;
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}
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rc = of_property_read_u32(node, "divisor-reg", &div_reg);
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if (!rc) {
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dev_clk->div_reg = pmc_base + div_reg;
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/*
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* use 0x1f as the default mask since it covers
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* almost all the clocks and reduces dts properties
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*/
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dev_clk->div_mask = 0x1f;
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of_property_read_u32(node, "divisor-mask", &dev_clk->div_mask);
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clk_init_flags |= CLK_INIT_DIVISOR;
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}
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of_property_read_string(node, "clock-output-names", &clk_name);
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switch (clk_init_flags) {
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case CLK_INIT_GATED:
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init.ops = &vt8500_gated_clk_ops;
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break;
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case CLK_INIT_DIVISOR:
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init.ops = &vt8500_divisor_clk_ops;
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break;
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case CLK_INIT_GATED_DIVISOR:
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init.ops = &vt8500_gated_divisor_clk_ops;
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break;
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default:
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pr_err("%s: Invalid clock description in device tree\n",
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__func__);
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kfree(dev_clk);
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return;
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}
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init.name = clk_name;
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init.flags = 0;
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parent_name = of_clk_get_parent_name(node, 0);
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init.parent_names = &parent_name;
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init.num_parents = 1;
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dev_clk->hw.init = &init;
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clk = clk_register(NULL, &dev_clk->hw);
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if (WARN_ON(IS_ERR(clk))) {
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kfree(dev_clk);
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return;
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}
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rc = of_clk_add_provider(node, of_clk_src_simple_get, clk);
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clk_register_clkdev(clk, clk_name, NULL);
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}
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/* PLL clock related functions */
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#define to_clk_pll(_hw) container_of(_hw, struct clk_pll, hw)
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/* Helper macros for PLL_VT8500 */
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#define VT8500_PLL_MUL(x) ((x & 0x1F) << 1)
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#define VT8500_PLL_DIV(x) ((x & 0x100) ? 1 : 2)
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#define VT8500_BITS_TO_FREQ(r, m, d) \
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((r / d) * m)
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#define VT8500_BITS_TO_VAL(m, d) \
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((d == 2 ? 0 : 0x100) | ((m >> 1) & 0x1F))
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/* Helper macros for PLL_WM8650 */
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#define WM8650_PLL_MUL(x) (x & 0x3FF)
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#define WM8650_PLL_DIV(x) (((x >> 10) & 7) * (1 << ((x >> 13) & 3)))
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#define WM8650_BITS_TO_FREQ(r, m, d1, d2) \
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(r * m / (d1 * (1 << d2)))
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#define WM8650_BITS_TO_VAL(m, d1, d2) \
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((d2 << 13) | (d1 << 10) | (m & 0x3FF))
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static void vt8500_find_pll_bits(unsigned long rate, unsigned long parent_rate,
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u32 *multiplier, u32 *prediv)
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{
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unsigned long tclk;
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/* sanity check */
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if ((rate < parent_rate * 4) || (rate > parent_rate * 62)) {
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pr_err("%s: requested rate out of range\n", __func__);
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*multiplier = 0;
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*prediv = 1;
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return;
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}
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if (rate <= parent_rate * 31)
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/* use the prediv to double the resolution */
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*prediv = 2;
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else
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*prediv = 1;
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*multiplier = rate / (parent_rate / *prediv);
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tclk = (parent_rate / *prediv) * *multiplier;
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if (tclk != rate)
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pr_warn("%s: requested rate %lu, found rate %lu\n", __func__,
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rate, tclk);
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}
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static void wm8650_find_pll_bits(unsigned long rate, unsigned long parent_rate,
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u32 *multiplier, u32 *divisor1, u32 *divisor2)
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{
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u32 mul, div1, div2;
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u32 best_mul, best_div1, best_div2;
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unsigned long tclk, rate_err, best_err;
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best_err = (unsigned long)-1;
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/* Find the closest match (lower or equal to requested) */
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for (div1 = 5; div1 >= 3; div1--)
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for (div2 = 3; div2 >= 0; div2--)
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for (mul = 3; mul <= 1023; mul++) {
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tclk = parent_rate * mul / (div1 * (1 << div2));
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if (tclk > rate)
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continue;
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/* error will always be +ve */
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rate_err = rate - tclk;
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if (rate_err == 0) {
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*multiplier = mul;
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*divisor1 = div1;
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*divisor2 = div2;
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return;
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}
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if (rate_err < best_err) {
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best_err = rate_err;
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best_mul = mul;
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best_div1 = div1;
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best_div2 = div2;
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}
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}
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/* if we got here, it wasn't an exact match */
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pr_warn("%s: requested rate %lu, found rate %lu\n", __func__, rate,
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rate - best_err);
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*multiplier = mul;
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*divisor1 = div1;
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*divisor2 = div2;
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}
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static int vtwm_pll_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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struct clk_pll *pll = to_clk_pll(hw);
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u32 mul, div1, div2;
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u32 pll_val;
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unsigned long flags = 0;
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/* sanity check */
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switch (pll->type) {
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case PLL_TYPE_VT8500:
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vt8500_find_pll_bits(rate, parent_rate, &mul, &div1);
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pll_val = VT8500_BITS_TO_VAL(mul, div1);
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break;
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case PLL_TYPE_WM8650:
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wm8650_find_pll_bits(rate, parent_rate, &mul, &div1, &div2);
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pll_val = WM8650_BITS_TO_VAL(mul, div1, div2);
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break;
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default:
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pr_err("%s: invalid pll type\n", __func__);
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return 0;
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}
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spin_lock_irqsave(pll->lock, flags);
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vt8500_pmc_wait_busy();
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writel(pll_val, pll->reg);
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vt8500_pmc_wait_busy();
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spin_unlock_irqrestore(pll->lock, flags);
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return 0;
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}
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static long vtwm_pll_round_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long *prate)
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{
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struct clk_pll *pll = to_clk_pll(hw);
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u32 mul, div1, div2;
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long round_rate;
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switch (pll->type) {
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case PLL_TYPE_VT8500:
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vt8500_find_pll_bits(rate, *prate, &mul, &div1);
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round_rate = VT8500_BITS_TO_FREQ(*prate, mul, div1);
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break;
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case PLL_TYPE_WM8650:
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wm8650_find_pll_bits(rate, *prate, &mul, &div1, &div2);
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round_rate = WM8650_BITS_TO_FREQ(*prate, mul, div1, div2);
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break;
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default:
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round_rate = 0;
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}
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return round_rate;
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}
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static unsigned long vtwm_pll_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct clk_pll *pll = to_clk_pll(hw);
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u32 pll_val = readl(pll->reg);
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unsigned long pll_freq;
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switch (pll->type) {
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case PLL_TYPE_VT8500:
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pll_freq = parent_rate * VT8500_PLL_MUL(pll_val);
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pll_freq /= VT8500_PLL_DIV(pll_val);
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break;
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case PLL_TYPE_WM8650:
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pll_freq = parent_rate * WM8650_PLL_MUL(pll_val);
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pll_freq /= WM8650_PLL_DIV(pll_val);
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break;
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default:
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pll_freq = 0;
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}
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return pll_freq;
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}
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const struct clk_ops vtwm_pll_ops = {
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.round_rate = vtwm_pll_round_rate,
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.set_rate = vtwm_pll_set_rate,
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.recalc_rate = vtwm_pll_recalc_rate,
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};
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static __init void vtwm_pll_clk_init(struct device_node *node, int pll_type)
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{
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u32 reg;
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struct clk *clk;
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struct clk_pll *pll_clk;
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const char *clk_name = node->name;
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const char *parent_name;
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struct clk_init_data init;
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int rc;
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rc = of_property_read_u32(node, "reg", ®);
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if (WARN_ON(rc))
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return;
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pll_clk = kzalloc(sizeof(*pll_clk), GFP_KERNEL);
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if (WARN_ON(!pll_clk))
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return;
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pll_clk->reg = pmc_base + reg;
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pll_clk->lock = &_lock;
|
||||
pll_clk->type = pll_type;
|
||||
|
||||
of_property_read_string(node, "clock-output-names", &clk_name);
|
||||
|
||||
init.name = clk_name;
|
||||
init.ops = &vtwm_pll_ops;
|
||||
init.flags = 0;
|
||||
parent_name = of_clk_get_parent_name(node, 0);
|
||||
init.parent_names = &parent_name;
|
||||
init.num_parents = 1;
|
||||
|
||||
pll_clk->hw.init = &init;
|
||||
|
||||
clk = clk_register(NULL, &pll_clk->hw);
|
||||
if (WARN_ON(IS_ERR(clk))) {
|
||||
kfree(pll_clk);
|
||||
return;
|
||||
}
|
||||
rc = of_clk_add_provider(node, of_clk_src_simple_get, clk);
|
||||
clk_register_clkdev(clk, clk_name, NULL);
|
||||
}
|
||||
|
||||
|
||||
/* Wrappers for initialization functions */
|
||||
|
||||
static void __init vt8500_pll_init(struct device_node *node)
|
||||
{
|
||||
vtwm_pll_clk_init(node, PLL_TYPE_VT8500);
|
||||
}
|
||||
|
||||
static void __init wm8650_pll_init(struct device_node *node)
|
||||
{
|
||||
vtwm_pll_clk_init(node, PLL_TYPE_WM8650);
|
||||
}
|
||||
|
||||
static const __initconst struct of_device_id clk_match[] = {
|
||||
{ .compatible = "fixed-clock", .data = of_fixed_clk_setup, },
|
||||
{ .compatible = "via,vt8500-pll-clock", .data = vt8500_pll_init, },
|
||||
{ .compatible = "wm,wm8650-pll-clock", .data = wm8650_pll_init, },
|
||||
{ .compatible = "via,vt8500-device-clock",
|
||||
.data = vtwm_device_clk_init, },
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
|
||||
void __init vtwm_clk_init(void __iomem *base)
|
||||
{
|
||||
if (!base)
|
||||
return;
|
||||
|
||||
pmc_base = base;
|
||||
|
||||
of_clk_init(clk_match);
|
||||
}
|
||||
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