mvebu fixes for v3.15 (incremental #2)

- Armada 38x
     - fix PCIe dt nodes for handling more interfaces
 
  - mvebu
     - mvebu-soc-id: fix clock handling and PCIe interface disabling.
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v2.0.22 (GNU/Linux)
 
 iQIcBAABAgAGBQJTfhXqAAoJEP45WPkGe8ZnVQEP/RS+GfrDRdvepgcoMzYAAisy
 iXQ8xcBEah+k8DQFyHrnZRZpYHvt1RpIiGdJa32KnIG9r+rXpxNpW3HRxUksWd4h
 GnhSe+valR3s1MKGxPZOfb6Njqh3LDhJLGNVDuB0iEZscnOQoC9zakPKZ/4Zc6Pj
 mvDdh8Pz500Ctvc7fQxejUhSZVOlXvp+p0DqJr6Jfvw28x/b6ZjcFoPYY/x/ZPgY
 32MztjrrxBqr7U+IQ/GxXFDHdoutbADI4/Q+m/a6zar11MmC2SIJHxPpmkjBxLAf
 zpEW1HnD1ZOlTpj4VYyi0CGEd4606bh5D7xXpkg2XDCa89+Xvv3jjRn6WeAmERaj
 yXiSqCcImuDgWsQ9Mfs5KwsCA245bnveZqjcOX45rkdZ0a0f4uDsKr80ljg2iigX
 x6M1t8hsQe0a04MGCV14tsHTzWyNNdPt6H8sytJMGcEMYYwYvbJgLPY3MI/iDYm7
 keZV697wDQH4XXX0ol9ZRmyGXFcKcGNuOxQnbi59u/HGCYqQqSj4TGMZl9oDIxSB
 CedZc9z6ySc/Jm4qRQ7IXZZEfnmbKPLQrnaIHz6/yfLvqezepVRaMAolGDIZ4f+z
 750i7Al5sL2ohemToXKy0J0dKHcG98Sl4CI1saSkQb4g1M5DpyVX+9lUiUSyZ4QC
 UZucbqj6Suzx2r137pL/
 =iM2f
 -----END PGP SIGNATURE-----

Merge tag 'mvebu-fixes-3.15-2' of git://git.infradead.org/linux-mvebu into fixes

mvebu fixes for v3.15 (incremental #2)

 - Armada 38x
    - fix PCIe dt nodes for handling more interfaces

 - mvebu
    - mvebu-soc-id: fix clock handling and PCIe interface disabling.

* tag 'mvebu-fixes-3.15-2' of git://git.infradead.org/linux-mvebu:
  ARM: mvebu: fix definitions of PCIe interfaces on Armada 38x
  ARM: mvebu: mvebu-soc-id: keep clock enabled if PCIe unit is enabled
  ARM: mvebu: mvebu-soc-id: add missing clk_put() call

Signed-off-by: Arnd Bergmann <arnd@arndb.de>

arch/arm/boot/dts/armada-380.dtsi

@@ -99,7 +99,7 @@
 			pcie@3,0 {
 				device_type = "pci";
 				assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
-				reg = <0x1000 0 0 0 0>;
+				reg = <0x1800 0 0 0 0>;
 				#address-cells = <3>;
 				#size-cells = <2>;
 				#interrupt-cells = <1>;

arch/arm/boot/dts/armada-385.dtsi

@@ -110,7 +110,7 @@
 			pcie@3,0 {
 				device_type = "pci";
 				assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
-				reg = <0x1000 0 0 0 0>;
+				reg = <0x1800 0 0 0 0>;
 				#address-cells = <3>;
 				#size-cells = <2>;
 				#interrupt-cells = <1>;
@@ -131,7 +131,7 @@
 			pcie@4,0 {
 				device_type = "pci";
 				assigned-addresses = <0x82000800 0 0x48000 0 0x2000>;
-				reg = <0x1000 0 0 0 0>;
+				reg = <0x2000 0 0 0 0>;
 				#address-cells = <3>;
 				#size-cells = <2>;
 				#interrupt-cells = <1>;

arch/arm/mach-mvebu/mvebu-soc-id.c

@@ -108,7 +108,18 @@ static int __init mvebu_soc_id_init(void)
 	iounmap(pci_base);
 
 res_ioremap:
+	/*
+	 * If the PCIe unit is actually enabled and we have PCI
+	 * support in the kernel, we intentionally do not release the
+	 * reference to the clock. We want to keep it running since
+	 * the bootloader does some PCIe link configuration that the
+	 * kernel is for now unable to do, and gating the clock would
+	 * make us loose this precious configuration.
+	 */
+	if (!of_device_is_available(child) || !IS_ENABLED(CONFIG_PCI_MVEBU)) {
 		clk_disable_unprepare(clk);
+		clk_put(clk);
+	}
 
 clk_err:
 	of_node_put(child);