ACPI / CPPC: Make CPPC ACPI driver aware of PCC subspace IDs
Based on ACPI 6.2 Section 8.4.7.1.9 If the PCC register space is used, all PCC registers, for all processors in the same performance domain (as defined by _PSD), must be defined to be in the same subspace. Based on Section 14.1 of ACPI specification, it is possible to have a maximum of 256 PCC subspace IDs. Add support of multiple PCC subspace ID instead of using a single global pcc_data structure. While at that, fix the time_delta check in send_pcc_cmd() so that last_mpar_reset and mpar_count are initialized properly. Signed-off-by: George Cherian <george.cherian@cavium.com> Reviewed-by: Prashanth Prakash <pprakash@codeaurora.org> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
This commit is contained in:
George Cherian
Rafael J. Wysocki
Родитель
c4b766c2f3
Коммит
85b1407bf6
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@ -48,7 +48,6 @@
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struct cppc_pcc_data {
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struct mbox_chan *pcc_channel;
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void __iomem *pcc_comm_addr;
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int pcc_subspace_idx;
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bool pcc_channel_acquired;
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ktime_t deadline;
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unsigned int pcc_mpar, pcc_mrtt, pcc_nominal;
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@ -75,13 +74,16 @@ struct cppc_pcc_data {
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/* Wait queue for CPUs whose requests were batched */
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wait_queue_head_t pcc_write_wait_q;
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ktime_t last_cmd_cmpl_time;
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ktime_t last_mpar_reset;
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int mpar_count;
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int refcount;
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};
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/* Structure to represent the single PCC channel */
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static struct cppc_pcc_data pcc_data = {
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.pcc_subspace_idx = -1,
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.platform_owns_pcc = true,
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};
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/* Array to represent the PCC channel per subspace id */
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static struct cppc_pcc_data *pcc_data[MAX_PCC_SUBSPACES];
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/* The cpu_pcc_subspace_idx containsper CPU subspace id */
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static DEFINE_PER_CPU(int, cpu_pcc_subspace_idx);
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/*
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* The cpc_desc structure contains the ACPI register details
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@ -93,7 +95,8 @@ static struct cppc_pcc_data pcc_data = {
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static DEFINE_PER_CPU(struct cpc_desc *, cpc_desc_ptr);
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/* pcc mapped address + header size + offset within PCC subspace */
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#define GET_PCC_VADDR(offs) (pcc_data.pcc_comm_addr + 0x8 + (offs))
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#define GET_PCC_VADDR(offs, pcc_ss_id) (pcc_data[pcc_ss_id]->pcc_comm_addr + \
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0x8 + (offs))
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/* Check if a CPC register is in PCC */
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#define CPC_IN_PCC(cpc) ((cpc)->type == ACPI_TYPE_BUFFER && \
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@ -188,13 +191,16 @@ static struct kobj_type cppc_ktype = {
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.default_attrs = cppc_attrs,
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};
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static int check_pcc_chan(bool chk_err_bit)
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static int check_pcc_chan(int pcc_ss_id, bool chk_err_bit)
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{
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int ret = -EIO, status = 0;
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struct acpi_pcct_shared_memory __iomem *generic_comm_base = pcc_data.pcc_comm_addr;
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ktime_t next_deadline = ktime_add(ktime_get(), pcc_data.deadline);
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struct cppc_pcc_data *pcc_ss_data = pcc_data[pcc_ss_id];
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struct acpi_pcct_shared_memory __iomem *generic_comm_base =
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pcc_ss_data->pcc_comm_addr;
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ktime_t next_deadline = ktime_add(ktime_get(),
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pcc_ss_data->deadline);
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if (!pcc_data.platform_owns_pcc)
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if (!pcc_ss_data->platform_owns_pcc)
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return 0;
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/* Retry in case the remote processor was too slow to catch up. */
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@ -219,7 +225,7 @@ static int check_pcc_chan(bool chk_err_bit)
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}
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if (likely(!ret))
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pcc_data.platform_owns_pcc = false;
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pcc_ss_data->platform_owns_pcc = false;
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else
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pr_err("PCC check channel failed. Status=%x\n", status);
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@ -230,13 +236,12 @@ static int check_pcc_chan(bool chk_err_bit)
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* This function transfers the ownership of the PCC to the platform
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* So it must be called while holding write_lock(pcc_lock)
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*/
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static int send_pcc_cmd(u16 cmd)
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static int send_pcc_cmd(int pcc_ss_id, u16 cmd)
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{
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int ret = -EIO, i;
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struct cppc_pcc_data *pcc_ss_data = pcc_data[pcc_ss_id];
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struct acpi_pcct_shared_memory *generic_comm_base =
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(struct acpi_pcct_shared_memory *) pcc_data.pcc_comm_addr;
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static ktime_t last_cmd_cmpl_time, last_mpar_reset;
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static int mpar_count;
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(struct acpi_pcct_shared_memory *)pcc_ss_data->pcc_comm_addr;
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unsigned int time_delta;
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/*
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@ -249,24 +254,25 @@ static int send_pcc_cmd(u16 cmd)
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* before write completion, so first send a WRITE command to
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* platform
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*/
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if (pcc_data.pending_pcc_write_cmd)
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send_pcc_cmd(CMD_WRITE);
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if (pcc_ss_data->pending_pcc_write_cmd)
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send_pcc_cmd(pcc_ss_id, CMD_WRITE);
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ret = check_pcc_chan(false);
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ret = check_pcc_chan(pcc_ss_id, false);
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if (ret)
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goto end;
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} else /* CMD_WRITE */
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pcc_data.pending_pcc_write_cmd = FALSE;
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pcc_ss_data->pending_pcc_write_cmd = FALSE;
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/*
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* Handle the Minimum Request Turnaround Time(MRTT)
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* "The minimum amount of time that OSPM must wait after the completion
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* of a command before issuing the next command, in microseconds"
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*/
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if (pcc_data.pcc_mrtt) {
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time_delta = ktime_us_delta(ktime_get(), last_cmd_cmpl_time);
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if (pcc_data.pcc_mrtt > time_delta)
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udelay(pcc_data.pcc_mrtt - time_delta);
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if (pcc_ss_data->pcc_mrtt) {
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time_delta = ktime_us_delta(ktime_get(),
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pcc_ss_data->last_cmd_cmpl_time);
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if (pcc_ss_data->pcc_mrtt > time_delta)
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udelay(pcc_ss_data->pcc_mrtt - time_delta);
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}
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/*
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@ -280,18 +286,19 @@ static int send_pcc_cmd(u16 cmd)
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* not send the request to the platform after hitting the MPAR limit in
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* any 60s window
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*/
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if (pcc_data.pcc_mpar) {
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if (mpar_count == 0) {
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time_delta = ktime_ms_delta(ktime_get(), last_mpar_reset);
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if (time_delta < 60 * MSEC_PER_SEC) {
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if (pcc_ss_data->pcc_mpar) {
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if (pcc_ss_data->mpar_count == 0) {
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time_delta = ktime_ms_delta(ktime_get(),
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pcc_ss_data->last_mpar_reset);
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if ((time_delta < 60 * MSEC_PER_SEC) && pcc_ss_data->last_mpar_reset) {
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pr_debug("PCC cmd not sent due to MPAR limit");
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ret = -EIO;
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goto end;
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}
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last_mpar_reset = ktime_get();
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mpar_count = pcc_data.pcc_mpar;
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pcc_ss_data->last_mpar_reset = ktime_get();
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pcc_ss_data->mpar_count = pcc_ss_data->pcc_mpar;
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}
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mpar_count--;
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pcc_ss_data->mpar_count--;
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}
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/* Write to the shared comm region. */
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@ -300,10 +307,10 @@ static int send_pcc_cmd(u16 cmd)
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/* Flip CMD COMPLETE bit */
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writew_relaxed(0, &generic_comm_base->status);
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pcc_data.platform_owns_pcc = true;
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pcc_ss_data->platform_owns_pcc = true;
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/* Ring doorbell */
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ret = mbox_send_message(pcc_data.pcc_channel, &cmd);
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ret = mbox_send_message(pcc_ss_data->pcc_channel, &cmd);
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if (ret < 0) {
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pr_err("Err sending PCC mbox message. cmd:%d, ret:%d\n",
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cmd, ret);
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@ -311,15 +318,15 @@ static int send_pcc_cmd(u16 cmd)
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}
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/* wait for completion and check for PCC errro bit */
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ret = check_pcc_chan(true);
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ret = check_pcc_chan(pcc_ss_id, true);
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if (pcc_data.pcc_mrtt)
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last_cmd_cmpl_time = ktime_get();
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if (pcc_ss_data->pcc_mrtt)
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pcc_ss_data->last_cmd_cmpl_time = ktime_get();
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if (pcc_data.pcc_channel->mbox->txdone_irq)
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mbox_chan_txdone(pcc_data.pcc_channel, ret);
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if (pcc_ss_data->pcc_channel->mbox->txdone_irq)
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mbox_chan_txdone(pcc_ss_data->pcc_channel, ret);
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else
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mbox_client_txdone(pcc_data.pcc_channel, ret);
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mbox_client_txdone(pcc_ss_data->pcc_channel, ret);
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end:
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if (cmd == CMD_WRITE) {
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@ -329,12 +336,12 @@ end:
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if (!desc)
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continue;
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if (desc->write_cmd_id == pcc_data.pcc_write_cnt)
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if (desc->write_cmd_id == pcc_ss_data->pcc_write_cnt)
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desc->write_cmd_status = ret;
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}
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}
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pcc_data.pcc_write_cnt++;
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wake_up_all(&pcc_data.pcc_write_wait_q);
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pcc_ss_data->pcc_write_cnt++;
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wake_up_all(&pcc_ss_data->pcc_write_wait_q);
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}
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return ret;
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@ -536,16 +543,16 @@ err_ret:
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}
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EXPORT_SYMBOL_GPL(acpi_get_psd_map);
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static int register_pcc_channel(int pcc_subspace_idx)
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static int register_pcc_channel(int pcc_ss_idx)
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{
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struct acpi_pcct_hw_reduced *cppc_ss;
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u64 usecs_lat;
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if (pcc_subspace_idx >= 0) {
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pcc_data.pcc_channel = pcc_mbox_request_channel(&cppc_mbox_cl,
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pcc_subspace_idx);
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if (pcc_ss_idx >= 0) {
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pcc_data[pcc_ss_idx]->pcc_channel =
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pcc_mbox_request_channel(&cppc_mbox_cl, pcc_ss_idx);
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if (IS_ERR(pcc_data.pcc_channel)) {
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if (IS_ERR(pcc_data[pcc_ss_idx]->pcc_channel)) {
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pr_err("Failed to find PCC communication channel\n");
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return -ENODEV;
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}
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@ -556,7 +563,7 @@ static int register_pcc_channel(int pcc_subspace_idx)
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* PCC channels) and stored pointers to the
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* subspace communication region in con_priv.
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*/
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cppc_ss = (pcc_data.pcc_channel)->con_priv;
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cppc_ss = (pcc_data[pcc_ss_idx]->pcc_channel)->con_priv;
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if (!cppc_ss) {
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pr_err("No PCC subspace found for CPPC\n");
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@ -569,19 +576,20 @@ static int register_pcc_channel(int pcc_subspace_idx)
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* So add an arbitrary amount of wait on top of Nominal.
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*/
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usecs_lat = NUM_RETRIES * cppc_ss->latency;
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pcc_data.deadline = ns_to_ktime(usecs_lat * NSEC_PER_USEC);
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pcc_data.pcc_mrtt = cppc_ss->min_turnaround_time;
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pcc_data.pcc_mpar = cppc_ss->max_access_rate;
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pcc_data.pcc_nominal = cppc_ss->latency;
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pcc_data[pcc_ss_idx]->deadline = ns_to_ktime(usecs_lat * NSEC_PER_USEC);
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pcc_data[pcc_ss_idx]->pcc_mrtt = cppc_ss->min_turnaround_time;
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pcc_data[pcc_ss_idx]->pcc_mpar = cppc_ss->max_access_rate;
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pcc_data[pcc_ss_idx]->pcc_nominal = cppc_ss->latency;
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pcc_data.pcc_comm_addr = acpi_os_ioremap(cppc_ss->base_address, cppc_ss->length);
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if (!pcc_data.pcc_comm_addr) {
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pcc_data[pcc_ss_idx]->pcc_comm_addr =
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acpi_os_ioremap(cppc_ss->base_address, cppc_ss->length);
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if (!pcc_data[pcc_ss_idx]->pcc_comm_addr) {
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pr_err("Failed to ioremap PCC comm region mem\n");
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return -ENOMEM;
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}
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/* Set flag so that we dont come here for each CPU. */
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pcc_data.pcc_channel_acquired = true;
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pcc_data[pcc_ss_idx]->pcc_channel_acquired = true;
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}
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return 0;
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@ -600,6 +608,34 @@ bool __weak cpc_ffh_supported(void)
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return false;
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}
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/**
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* pcc_data_alloc() - Allocate the pcc_data memory for pcc subspace
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*
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* Check and allocate the cppc_pcc_data memory.
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* In some processor configurations it is possible that same subspace
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* is shared between multiple CPU's. This is seen especially in CPU's
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* with hardware multi-threading support.
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*
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* Return: 0 for success, errno for failure
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*/
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int pcc_data_alloc(int pcc_ss_id)
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{
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if (pcc_ss_id < 0 || pcc_ss_id >= MAX_PCC_SUBSPACES)
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return -EINVAL;
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if (pcc_data[pcc_ss_id]) {
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pcc_data[pcc_ss_id]->refcount++;
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} else {
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pcc_data[pcc_ss_id] = kzalloc(sizeof(struct cppc_pcc_data),
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GFP_KERNEL);
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if (!pcc_data[pcc_ss_id])
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return -ENOMEM;
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pcc_data[pcc_ss_id]->refcount++;
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}
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return 0;
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}
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/*
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* An example CPC table looks like the following.
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*
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@ -661,6 +697,7 @@ int acpi_cppc_processor_probe(struct acpi_processor *pr)
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struct device *cpu_dev;
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acpi_handle handle = pr->handle;
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unsigned int num_ent, i, cpc_rev;
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int pcc_subspace_id = -1;
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acpi_status status;
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int ret = -EFAULT;
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@ -733,9 +770,11 @@ int acpi_cppc_processor_probe(struct acpi_processor *pr)
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* so extract it only once.
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*/
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if (gas_t->space_id == ACPI_ADR_SPACE_PLATFORM_COMM) {
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if (pcc_data.pcc_subspace_idx < 0)
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pcc_data.pcc_subspace_idx = gas_t->access_width;
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else if (pcc_data.pcc_subspace_idx != gas_t->access_width) {
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if (pcc_subspace_id < 0) {
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pcc_subspace_id = gas_t->access_width;
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if (pcc_data_alloc(pcc_subspace_id))
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goto out_free;
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} else if (pcc_subspace_id != gas_t->access_width) {
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pr_debug("Mismatched PCC ids.\n");
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goto out_free;
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}
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@ -763,6 +802,7 @@ int acpi_cppc_processor_probe(struct acpi_processor *pr)
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goto out_free;
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}
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}
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per_cpu(cpu_pcc_subspace_idx, pr->id) = pcc_subspace_id;
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/* Store CPU Logical ID */
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cpc_ptr->cpu_id = pr->id;
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@ -771,14 +811,14 @@ int acpi_cppc_processor_probe(struct acpi_processor *pr)
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if (ret)
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goto out_free;
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/* Register PCC channel once for all CPUs. */
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if (!pcc_data.pcc_channel_acquired) {
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ret = register_pcc_channel(pcc_data.pcc_subspace_idx);
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/* Register PCC channel once for all PCC subspace id. */
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if (pcc_subspace_id >= 0 && !pcc_data[pcc_subspace_id]->pcc_channel_acquired) {
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ret = register_pcc_channel(pcc_subspace_id);
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if (ret)
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goto out_free;
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|
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init_rwsem(&pcc_data.pcc_lock);
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init_waitqueue_head(&pcc_data.pcc_write_wait_q);
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init_rwsem(&pcc_data[pcc_subspace_id]->pcc_lock);
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init_waitqueue_head(&pcc_data[pcc_subspace_id]->pcc_write_wait_q);
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}
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/* Everything looks okay */
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|
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@ -831,6 +871,18 @@ void acpi_cppc_processor_exit(struct acpi_processor *pr)
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struct cpc_desc *cpc_ptr;
|
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unsigned int i;
|
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void __iomem *addr;
|
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int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, pr->id);
|
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|
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if (pcc_ss_id >=0 && pcc_data[pcc_ss_id]) {
|
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if (pcc_data[pcc_ss_id]->pcc_channel_acquired) {
|
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pcc_data[pcc_ss_id]->refcount--;
|
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if (!pcc_data[pcc_ss_id]->refcount) {
|
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pcc_mbox_free_channel(pcc_data[pcc_ss_id]->pcc_channel);
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pcc_data[pcc_ss_id]->pcc_channel_acquired = 0;
|
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kfree(pcc_data[pcc_ss_id]);
|
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}
|
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}
|
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}
|
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|
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cpc_ptr = per_cpu(cpc_desc_ptr, pr->id);
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if (!cpc_ptr)
|
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|
|
@ -888,6 +940,7 @@ static int cpc_read(int cpu, struct cpc_register_resource *reg_res, u64 *val)
|
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{
|
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int ret_val = 0;
|
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void __iomem *vaddr = 0;
|
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int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu);
|
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struct cpc_reg *reg = ®_res->cpc_entry.reg;
|
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|
||||
if (reg_res->type == ACPI_TYPE_INTEGER) {
|
||||
|
|
@ -897,7 +950,7 @@ static int cpc_read(int cpu, struct cpc_register_resource *reg_res, u64 *val)
|
|||
|
||||
*val = 0;
|
||||
if (reg->space_id == ACPI_ADR_SPACE_PLATFORM_COMM)
|
||||
vaddr = GET_PCC_VADDR(reg->address);
|
||||
vaddr = GET_PCC_VADDR(reg->address, pcc_ss_id);
|
||||
else if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY)
|
||||
vaddr = reg_res->sys_mem_vaddr;
|
||||
else if (reg->space_id == ACPI_ADR_SPACE_FIXED_HARDWARE)
|
||||
|
|
@ -932,10 +985,11 @@ static int cpc_write(int cpu, struct cpc_register_resource *reg_res, u64 val)
|
|||
{
|
||||
int ret_val = 0;
|
||||
void __iomem *vaddr = 0;
|
||||
int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu);
|
||||
struct cpc_reg *reg = ®_res->cpc_entry.reg;
|
||||
|
||||
if (reg->space_id == ACPI_ADR_SPACE_PLATFORM_COMM)
|
||||
vaddr = GET_PCC_VADDR(reg->address);
|
||||
vaddr = GET_PCC_VADDR(reg->address, pcc_ss_id);
|
||||
else if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_MEMORY)
|
||||
vaddr = reg_res->sys_mem_vaddr;
|
||||
else if (reg->space_id == ACPI_ADR_SPACE_FIXED_HARDWARE)
|
||||
|
|
@ -980,6 +1034,8 @@ int cppc_get_perf_caps(int cpunum, struct cppc_perf_caps *perf_caps)
|
|||
struct cpc_register_resource *highest_reg, *lowest_reg,
|
||||
*lowest_non_linear_reg, *nominal_reg;
|
||||
u64 high, low, nom, min_nonlinear;
|
||||
int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpunum);
|
||||
struct cppc_pcc_data *pcc_ss_data = pcc_data[pcc_ss_id];
|
||||
int ret = 0, regs_in_pcc = 0;
|
||||
|
||||
if (!cpc_desc) {
|
||||
|
|
@ -996,9 +1052,9 @@ int cppc_get_perf_caps(int cpunum, struct cppc_perf_caps *perf_caps)
|
|||
if (CPC_IN_PCC(highest_reg) || CPC_IN_PCC(lowest_reg) ||
|
||||
CPC_IN_PCC(lowest_non_linear_reg) || CPC_IN_PCC(nominal_reg)) {
|
||||
regs_in_pcc = 1;
|
||||
down_write(&pcc_data.pcc_lock);
|
||||
down_write(&pcc_ss_data->pcc_lock);
|
||||
/* Ring doorbell once to update PCC subspace */
|
||||
if (send_pcc_cmd(CMD_READ) < 0) {
|
||||
if (send_pcc_cmd(pcc_ss_id, CMD_READ) < 0) {
|
||||
ret = -EIO;
|
||||
goto out_err;
|
||||
}
|
||||
|
|
@ -1021,7 +1077,7 @@ int cppc_get_perf_caps(int cpunum, struct cppc_perf_caps *perf_caps)
|
|||
|
||||
out_err:
|
||||
if (regs_in_pcc)
|
||||
up_write(&pcc_data.pcc_lock);
|
||||
up_write(&pcc_ss_data->pcc_lock);
|
||||
return ret;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(cppc_get_perf_caps);
|
||||
|
|
@ -1038,6 +1094,8 @@ int cppc_get_perf_ctrs(int cpunum, struct cppc_perf_fb_ctrs *perf_fb_ctrs)
|
|||
struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpunum);
|
||||
struct cpc_register_resource *delivered_reg, *reference_reg,
|
||||
*ref_perf_reg, *ctr_wrap_reg;
|
||||
int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpunum);
|
||||
struct cppc_pcc_data *pcc_ss_data = pcc_data[pcc_ss_id];
|
||||
u64 delivered, reference, ref_perf, ctr_wrap_time;
|
||||
int ret = 0, regs_in_pcc = 0;
|
||||
|
||||
|
|
@ -1061,10 +1119,10 @@ int cppc_get_perf_ctrs(int cpunum, struct cppc_perf_fb_ctrs *perf_fb_ctrs)
|
|||
/* Are any of the regs PCC ?*/
|
||||
if (CPC_IN_PCC(delivered_reg) || CPC_IN_PCC(reference_reg) ||
|
||||
CPC_IN_PCC(ctr_wrap_reg) || CPC_IN_PCC(ref_perf_reg)) {
|
||||
down_write(&pcc_data.pcc_lock);
|
||||
down_write(&pcc_ss_data->pcc_lock);
|
||||
regs_in_pcc = 1;
|
||||
/* Ring doorbell once to update PCC subspace */
|
||||
if (send_pcc_cmd(CMD_READ) < 0) {
|
||||
if (send_pcc_cmd(pcc_ss_id, CMD_READ) < 0) {
|
||||
ret = -EIO;
|
||||
goto out_err;
|
||||
}
|
||||
|
|
@ -1094,7 +1152,7 @@ int cppc_get_perf_ctrs(int cpunum, struct cppc_perf_fb_ctrs *perf_fb_ctrs)
|
|||
perf_fb_ctrs->wraparound_time = ctr_wrap_time;
|
||||
out_err:
|
||||
if (regs_in_pcc)
|
||||
up_write(&pcc_data.pcc_lock);
|
||||
up_write(&pcc_ss_data->pcc_lock);
|
||||
return ret;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(cppc_get_perf_ctrs);
|
||||
|
|
@ -1110,6 +1168,8 @@ int cppc_set_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls)
|
|||
{
|
||||
struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpu);
|
||||
struct cpc_register_resource *desired_reg;
|
||||
int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu);
|
||||
struct cppc_pcc_data *pcc_ss_data = pcc_data[pcc_ss_id];
|
||||
int ret = 0;
|
||||
|
||||
if (!cpc_desc) {
|
||||
|
|
@ -1127,11 +1187,11 @@ int cppc_set_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls)
|
|||
* achieve that goal here
|
||||
*/
|
||||
if (CPC_IN_PCC(desired_reg)) {
|
||||
down_read(&pcc_data.pcc_lock); /* BEGIN Phase-I */
|
||||
if (pcc_data.platform_owns_pcc) {
|
||||
ret = check_pcc_chan(false);
|
||||
down_read(&pcc_ss_data->pcc_lock); /* BEGIN Phase-I */
|
||||
if (pcc_ss_data->platform_owns_pcc) {
|
||||
ret = check_pcc_chan(pcc_ss_id, false);
|
||||
if (ret) {
|
||||
up_read(&pcc_data.pcc_lock);
|
||||
up_read(&pcc_ss_data->pcc_lock);
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
|
|
@ -1139,8 +1199,8 @@ int cppc_set_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls)
|
|||
* Update the pending_write to make sure a PCC CMD_READ will not
|
||||
* arrive and steal the channel during the switch to write lock
|
||||
*/
|
||||
pcc_data.pending_pcc_write_cmd = true;
|
||||
cpc_desc->write_cmd_id = pcc_data.pcc_write_cnt;
|
||||
pcc_ss_data->pending_pcc_write_cmd = true;
|
||||
cpc_desc->write_cmd_id = pcc_ss_data->pcc_write_cnt;
|
||||
cpc_desc->write_cmd_status = 0;
|
||||
}
|
||||
|
||||
|
|
@ -1151,7 +1211,7 @@ int cppc_set_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls)
|
|||
cpc_write(cpu, desired_reg, perf_ctrls->desired_perf);
|
||||
|
||||
if (CPC_IN_PCC(desired_reg))
|
||||
up_read(&pcc_data.pcc_lock); /* END Phase-I */
|
||||
up_read(&pcc_ss_data->pcc_lock); /* END Phase-I */
|
||||
/*
|
||||
* This is Phase-II where we transfer the ownership of PCC to Platform
|
||||
*
|
||||
|
|
@ -1199,15 +1259,15 @@ int cppc_set_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls)
|
|||
* the write command before servicing the read command
|
||||
*/
|
||||
if (CPC_IN_PCC(desired_reg)) {
|
||||
if (down_write_trylock(&pcc_data.pcc_lock)) { /* BEGIN Phase-II */
|
||||
if (down_write_trylock(&pcc_ss_data->pcc_lock)) {/* BEGIN Phase-II */
|
||||
/* Update only if there are pending write commands */
|
||||
if (pcc_data.pending_pcc_write_cmd)
|
||||
send_pcc_cmd(CMD_WRITE);
|
||||
up_write(&pcc_data.pcc_lock); /* END Phase-II */
|
||||
if (pcc_ss_data->pending_pcc_write_cmd)
|
||||
send_pcc_cmd(pcc_ss_id, CMD_WRITE);
|
||||
up_write(&pcc_ss_data->pcc_lock); /* END Phase-II */
|
||||
} else
|
||||
/* Wait until pcc_write_cnt is updated by send_pcc_cmd */
|
||||
wait_event(pcc_data.pcc_write_wait_q,
|
||||
cpc_desc->write_cmd_id != pcc_data.pcc_write_cnt);
|
||||
wait_event(pcc_ss_data->pcc_write_wait_q,
|
||||
cpc_desc->write_cmd_id != pcc_ss_data->pcc_write_cnt);
|
||||
|
||||
/* send_pcc_cmd updates the status in case of failure */
|
||||
ret = cpc_desc->write_cmd_status;
|
||||
|
|
@ -1240,6 +1300,8 @@ unsigned int cppc_get_transition_latency(int cpu_num)
|
|||
unsigned int latency_ns = 0;
|
||||
struct cpc_desc *cpc_desc;
|
||||
struct cpc_register_resource *desired_reg;
|
||||
int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu_num);
|
||||
struct cppc_pcc_data *pcc_ss_data = pcc_data[pcc_ss_id];
|
||||
|
||||
cpc_desc = per_cpu(cpc_desc_ptr, cpu_num);
|
||||
if (!cpc_desc)
|
||||
|
|
@ -1249,11 +1311,11 @@ unsigned int cppc_get_transition_latency(int cpu_num)
|
|||
if (!CPC_IN_PCC(desired_reg))
|
||||
return CPUFREQ_ETERNAL;
|
||||
|
||||
if (pcc_data.pcc_mpar)
|
||||
latency_ns = 60 * (1000 * 1000 * 1000 / pcc_data.pcc_mpar);
|
||||
if (pcc_ss_data->pcc_mpar)
|
||||
latency_ns = 60 * (1000 * 1000 * 1000 / pcc_ss_data->pcc_mpar);
|
||||
|
||||
latency_ns = max(latency_ns, pcc_data.pcc_nominal * 1000);
|
||||
latency_ns = max(latency_ns, pcc_data.pcc_mrtt * 1000);
|
||||
latency_ns = max(latency_ns, pcc_ss_data->pcc_nominal * 1000);
|
||||
latency_ns = max(latency_ns, pcc_ss_data->pcc_mrtt * 1000);
|
||||
|
||||
return latency_ns;
|
||||
}
|
||||
|
|
|
|||
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