x86: merge mpparse_{32,64}.c
Signed-off-by: Alexey Starikovskiy <astarikovskiy@suse.de> Signed-off-by: Ingo Molnar <mingo@elte.hu>
This commit is contained in:
Alexey Starikovskiy
Ingo Molnar
Родитель
cfa08d6cc3
Коммит
85bdddec5e
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@ -51,7 +51,7 @@ obj-$(CONFIG_X86_SMP) += smpboot.o tsc_sync.o ipi.o tlb_$(BITS).o
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obj-$(CONFIG_X86_32_SMP) += smpcommon.o
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obj-$(CONFIG_X86_64_SMP) += tsc_sync.o smpcommon.o
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obj-$(CONFIG_X86_TRAMPOLINE) += trampoline_$(BITS).o
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obj-$(CONFIG_X86_MPPARSE) += mpparse_$(BITS).o
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obj-$(CONFIG_X86_MPPARSE) += mpparse.o
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obj-$(CONFIG_X86_LOCAL_APIC) += apic_$(BITS).o nmi_$(BITS).o
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obj-$(CONFIG_X86_IO_APIC) += io_apic_$(BITS).o
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obj-$(CONFIG_X86_REBOOTFIXUPS) += reboot_fixups_32.o
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@ -4,34 +4,33 @@
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*
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* (c) 1995 Alan Cox, Building #3 <alan@redhat.com>
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* (c) 1998, 1999, 2000 Ingo Molnar <mingo@redhat.com>
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*
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* Fixes
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* Erich Boleyn : MP v1.4 and additional changes.
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* Alan Cox : Added EBDA scanning
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* Ingo Molnar : various cleanups and rewrites
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* Maciej W. Rozycki: Bits for default MP configurations
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* Paul Diefenbaugh: Added full ACPI support
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* (c) 2008 Alexey Starikovskiy <astarikovskiy@suse.de>
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*/
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#include <linux/mm.h>
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#include <linux/init.h>
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#include <linux/acpi.h>
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#include <linux/delay.h>
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#include <linux/bootmem.h>
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#include <linux/kernel_stat.h>
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#include <linux/mc146818rtc.h>
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#include <linux/bitops.h>
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#include <linux/acpi.h>
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#include <linux/module.h>
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#include <asm/smp.h>
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#include <asm/acpi.h>
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#include <asm/mtrr.h>
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#include <asm/mpspec.h>
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#include <asm/pgalloc.h>
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#include <asm/io_apic.h>
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#include <asm/proto.h>
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#include <asm/acpi.h>
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#include <asm/bios_ebda.h>
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#include <mach_apic.h>
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#ifdef CONFIG_X86_32
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#include <mach_apicdef.h>
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#include <mach_mpparse.h>
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#endif
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/* Have we found an MP table */
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int smp_found_config;
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@ -43,8 +42,10 @@ int smp_found_config;
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#if defined (CONFIG_MCA) || defined (CONFIG_EISA)
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int mp_bus_id_to_type[MAX_MP_BUSSES];
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#endif
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DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES);
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int mp_bus_id_to_pci_bus[MAX_MP_BUSSES] = {[0 ... MAX_MP_BUSSES - 1] = -1 };
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static int mp_current_pci_id;
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int pic_mode;
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@ -582,7 +583,6 @@ static void __init __get_smp_config(unsigned early)
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if (acpi_lapic && early)
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return;
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/*
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* ACPI supports both logical (e.g. Hyper-Threading) and physical
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* processors, where MPS only supports physical.
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@ -1,991 +0,0 @@
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/*
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* Intel Multiprocessor Specification 1.1 and 1.4
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* compliant MP-table parsing routines.
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*
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* (c) 1995 Alan Cox, Building #3 <alan@redhat.com>
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* (c) 1998, 1999, 2000 Ingo Molnar <mingo@redhat.com>
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*
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* Fixes
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* Erich Boleyn : MP v1.4 and additional changes.
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* Alan Cox : Added EBDA scanning
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* Ingo Molnar : various cleanups and rewrites
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* Maciej W. Rozycki: Bits for default MP configurations
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* Paul Diefenbaugh: Added full ACPI support
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*/
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#include <linux/mm.h>
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#include <linux/init.h>
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#include <linux/delay.h>
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#include <linux/bootmem.h>
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#include <linux/kernel_stat.h>
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#include <linux/mc146818rtc.h>
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#include <linux/acpi.h>
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#include <linux/module.h>
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#include <asm/smp.h>
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#include <asm/mtrr.h>
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#include <asm/mpspec.h>
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#include <asm/pgalloc.h>
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#include <asm/io_apic.h>
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#include <asm/proto.h>
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#include <asm/acpi.h>
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#include <asm/bios_ebda.h>
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#include <mach_apic.h>
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/* Have we found an MP table */
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int smp_found_config;
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/*
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* Various Linux-internal data structures created from the
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* MP-table.
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*/
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DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES);
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int mp_bus_id_to_pci_bus[MAX_MP_BUSSES] = {[0 ... MAX_MP_BUSSES - 1] = -1 };
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static int mp_current_pci_id = 0;
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/*
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* Intel MP BIOS table parsing routines:
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*/
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/*
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* Checksum an MP configuration block.
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*/
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static int __init mpf_checksum(unsigned char *mp, int len)
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{
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int sum = 0;
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while (len--)
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sum += *mp++;
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return sum & 0xFF;
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}
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static void __cpuinit MP_processor_info(struct mpc_config_processor *m)
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{
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int apicid;
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char *bootup_cpu = "";
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if (!(m->mpc_cpuflag & CPU_ENABLED)) {
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disabled_cpus++;
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return;
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}
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#ifdef CONFIG_X86_NUMAQ
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apicid = mpc_apic_id(m, translation_table[mpc_record]);
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#else
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apicid = m->mpc_apicid;
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#endif
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if (m->mpc_cpuflag & CPU_BOOTPROCESSOR) {
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bootup_cpu = " (Bootup-CPU)";
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boot_cpu_physical_apicid = m->mpc_apicid;
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}
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printk(KERN_INFO "Processor #%d%s\n", m->mpc_apicid, bootup_cpu);
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generic_processor_info(apicid, m->mpc_apicver);
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}
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static void __init MP_bus_info(struct mpc_config_bus *m)
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{
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char str[7];
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memcpy(str, m->mpc_bustype, 6);
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str[6] = 0;
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#ifdef CONFIG_X86_NUMAQ
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mpc_oem_bus_info(m, str, translation_table[mpc_record]);
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#else
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Dprintk("Bus #%d is %s\n", m->mpc_busid, str);
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#endif
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#if MAX_MP_BUSSES < 256
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if (m->mpc_busid >= MAX_MP_BUSSES) {
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printk(KERN_WARNING "MP table busid value (%d) for bustype %s "
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" is too large, max. supported is %d\n",
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m->mpc_busid, str, MAX_MP_BUSSES - 1);
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return;
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}
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#endif
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if (strncmp(str, BUSTYPE_ISA, sizeof(BUSTYPE_ISA) - 1) == 0) {
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set_bit(m->mpc_busid, mp_bus_not_pci);
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#if defined(CONFIG_EISA) || defined (CONFIG_MCA)
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mp_bus_id_to_type[m->mpc_busid] = MP_BUS_ISA;
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#endif
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} else if (strncmp(str, BUSTYPE_PCI, sizeof(BUSTYPE_PCI) - 1) == 0) {
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#ifdef CONFIG_X86_NUMAQ
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mpc_oem_pci_bus(m, translation_table[mpc_record]);
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#endif
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clear_bit(m->mpc_busid, mp_bus_not_pci);
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mp_bus_id_to_pci_bus[m->mpc_busid] = mp_current_pci_id;
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mp_current_pci_id++;
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#if defined(CONFIG_EISA) || defined (CONFIG_MCA)
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mp_bus_id_to_type[m->mpc_busid] = MP_BUS_PCI;
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} else if (strncmp(str, BUSTYPE_EISA, sizeof(BUSTYPE_EISA) - 1) == 0) {
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mp_bus_id_to_type[m->mpc_busid] = MP_BUS_EISA;
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} else if (strncmp(str, BUSTYPE_MCA, sizeof(BUSTYPE_MCA) - 1) == 0) {
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mp_bus_id_to_type[m->mpc_busid] = MP_BUS_MCA;
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#endif
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} else
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printk(KERN_WARNING "Unknown bustype %s - ignoring\n", str);
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}
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static int bad_ioapic(unsigned long address)
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{
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if (nr_ioapics >= MAX_IO_APICS) {
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printk(KERN_ERR "ERROR: Max # of I/O APICs (%d) exceeded "
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"(found %d)\n", MAX_IO_APICS, nr_ioapics);
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panic("Recompile kernel with bigger MAX_IO_APICS!\n");
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}
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if (!address) {
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printk(KERN_ERR "WARNING: Bogus (zero) I/O APIC address"
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" found in table, skipping!\n");
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return 1;
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}
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return 0;
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}
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static void __init MP_ioapic_info(struct mpc_config_ioapic *m)
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{
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if (!(m->mpc_flags & MPC_APIC_USABLE))
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return;
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printk(KERN_INFO "I/O APIC #%d at 0x%X.\n", m->mpc_apicid,
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m->mpc_apicaddr);
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if (bad_ioapic(m->mpc_apicaddr))
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return;
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mp_ioapics[nr_ioapics] = *m;
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nr_ioapics++;
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}
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static void __init MP_intsrc_info(struct mpc_config_intsrc *m)
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{
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mp_irqs[mp_irq_entries] = *m;
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Dprintk("Int: type %d, pol %d, trig %d, bus %d,"
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" IRQ %02x, APIC ID %x, APIC INT %02x\n",
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m->mpc_irqtype, m->mpc_irqflag & 3,
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(m->mpc_irqflag >> 2) & 3, m->mpc_srcbus,
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m->mpc_srcbusirq, m->mpc_dstapic, m->mpc_dstirq);
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if (++mp_irq_entries >= MAX_IRQ_SOURCES)
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panic("Max # of irq sources exceeded!!\n");
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}
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static void __init MP_lintsrc_info(struct mpc_config_lintsrc *m)
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{
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Dprintk("Lint: type %d, pol %d, trig %d, bus %d,"
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" IRQ %02x, APIC ID %x, APIC LINT %02x\n",
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m->mpc_irqtype, m->mpc_irqflag & 3,
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(m->mpc_irqflag >> 2) & 3, m->mpc_srcbusid,
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m->mpc_srcbusirq, m->mpc_destapic, m->mpc_destapiclint);
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}
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/*
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* Read/parse the MPC
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*/
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static int __init smp_read_mpc(struct mp_config_table *mpc, unsigned early)
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{
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char str[16];
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char oem[10];
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int count = sizeof(*mpc);
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unsigned char *mpt = ((unsigned char *)mpc) + count;
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if (memcmp(mpc->mpc_signature, MPC_SIGNATURE, 4)) {
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printk(KERN_ERR "MPTABLE: bad signature [%c%c%c%c]!\n",
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mpc->mpc_signature[0], mpc->mpc_signature[1],
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mpc->mpc_signature[2], mpc->mpc_signature[3]);
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return 0;
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}
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if (mpf_checksum((unsigned char *)mpc, mpc->mpc_length)) {
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printk(KERN_ERR "MPTABLE: checksum error!\n");
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return 0;
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}
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if (mpc->mpc_spec != 0x01 && mpc->mpc_spec != 0x04) {
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printk(KERN_ERR "MPTABLE: bad table version (%d)!!\n",
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mpc->mpc_spec);
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return 0;
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}
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if (!mpc->mpc_lapic) {
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printk(KERN_ERR "MPTABLE: null local APIC address!\n");
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return 0;
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}
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memcpy(oem, mpc->mpc_oem, 8);
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oem[8] = 0;
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printk(KERN_INFO "MPTABLE: OEM ID: %s ", oem);
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memcpy(str, mpc->mpc_productid, 12);
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str[12] = 0;
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printk("Product ID: %s ", str);
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#ifdef CONFIG_X86_32
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mps_oem_check(mpc, oem, str);
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#endif
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printk(KERN_INFO "MPTABLE: Product ID: %s ", str);
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printk(KERN_INFO "MPTABLE: APIC at: 0x%X\n", mpc->mpc_lapic);
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/* save the local APIC address, it might be non-default */
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if (!acpi_lapic)
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mp_lapic_addr = mpc->mpc_lapic;
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if (early)
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return 1;
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/*
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* Now process the configuration blocks.
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*/
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#ifdef CONFIG_X86_NUMAQ
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mpc_record = 0;
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#endif
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while (count < mpc->mpc_length) {
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switch (*mpt) {
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case MP_PROCESSOR:
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{
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struct mpc_config_processor *m =
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(struct mpc_config_processor *)mpt;
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/* ACPI may have already provided this data */
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if (!acpi_lapic)
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MP_processor_info(m);
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mpt += sizeof(*m);
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count += sizeof(*m);
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break;
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}
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case MP_BUS:
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{
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struct mpc_config_bus *m =
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(struct mpc_config_bus *)mpt;
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MP_bus_info(m);
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mpt += sizeof(*m);
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count += sizeof(*m);
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break;
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}
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case MP_IOAPIC:
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{
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struct mpc_config_ioapic *m =
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(struct mpc_config_ioapic *)mpt;
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MP_ioapic_info(m);
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mpt += sizeof(*m);
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count += sizeof(*m);
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break;
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}
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case MP_INTSRC:
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{
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struct mpc_config_intsrc *m =
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(struct mpc_config_intsrc *)mpt;
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MP_intsrc_info(m);
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mpt += sizeof(*m);
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count += sizeof(*m);
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break;
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}
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case MP_LINTSRC:
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{
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struct mpc_config_lintsrc *m =
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(struct mpc_config_lintsrc *)mpt;
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MP_lintsrc_info(m);
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mpt += sizeof(*m);
|
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count += sizeof(*m);
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break;
|
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}
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default:
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{
|
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count = mpc->mpc_length;
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break;
|
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}
|
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}
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#ifdef CONFIG_X86_NUMAQ
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++mpc_record;
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#endif
|
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}
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setup_apic_routing();
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if (!num_processors)
|
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printk(KERN_ERR "MPTABLE: no processors registered!\n");
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return num_processors;
|
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}
|
||||
|
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static int __init ELCR_trigger(unsigned int irq)
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{
|
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unsigned int port;
|
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|
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port = 0x4d0 + (irq >> 3);
|
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return (inb(port) >> (irq & 7)) & 1;
|
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}
|
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|
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static void __init construct_default_ioirq_mptable(int mpc_default_type)
|
||||
{
|
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struct mpc_config_intsrc intsrc;
|
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int i;
|
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int ELCR_fallback = 0;
|
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|
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intsrc.mpc_type = MP_INTSRC;
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intsrc.mpc_irqflag = 0; /* conforming */
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intsrc.mpc_srcbus = 0;
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intsrc.mpc_dstapic = mp_ioapics[0].mpc_apicid;
|
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intsrc.mpc_irqtype = mp_INT;
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/*
|
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* If true, we have an ISA/PCI system with no IRQ entries
|
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* in the MP table. To prevent the PCI interrupts from being set up
|
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* incorrectly, we try to use the ELCR. The sanity check to see if
|
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* there is good ELCR data is very simple - IRQ0, 1, 2 and 13 can
|
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* never be level sensitive, so we simply see if the ELCR agrees.
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* If it does, we assume it's valid.
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*/
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if (mpc_default_type == 5) {
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printk(KERN_INFO "ISA/PCI bus type with no IRQ information... "
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"falling back to ELCR\n");
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if (ELCR_trigger(0) || ELCR_trigger(1) || ELCR_trigger(2) ||
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ELCR_trigger(13))
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printk(KERN_ERR "ELCR contains invalid data... "
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"not using ELCR\n");
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else {
|
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printk(KERN_INFO
|
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"Using ELCR to identify PCI interrupts\n");
|
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ELCR_fallback = 1;
|
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}
|
||||
}
|
||||
|
||||
for (i = 0; i < 16; i++) {
|
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switch (mpc_default_type) {
|
||||
case 2:
|
||||
if (i == 0 || i == 13)
|
||||
continue; /* IRQ0 & IRQ13 not connected */
|
||||
/* fall through */
|
||||
default:
|
||||
if (i == 2)
|
||||
continue; /* IRQ2 is never connected */
|
||||
}
|
||||
|
||||
if (ELCR_fallback) {
|
||||
/*
|
||||
* If the ELCR indicates a level-sensitive interrupt, we
|
||||
* copy that information over to the MP table in the
|
||||
* irqflag field (level sensitive, active high polarity).
|
||||
*/
|
||||
if (ELCR_trigger(i))
|
||||
intsrc.mpc_irqflag = 13;
|
||||
else
|
||||
intsrc.mpc_irqflag = 0;
|
||||
}
|
||||
|
||||
intsrc.mpc_srcbusirq = i;
|
||||
intsrc.mpc_dstirq = i ? i : 2; /* IRQ0 to INTIN2 */
|
||||
MP_intsrc_info(&intsrc);
|
||||
}
|
||||
|
||||
intsrc.mpc_irqtype = mp_ExtINT;
|
||||
intsrc.mpc_srcbusirq = 0;
|
||||
intsrc.mpc_dstirq = 0; /* 8259A to INTIN0 */
|
||||
MP_intsrc_info(&intsrc);
|
||||
}
|
||||
|
||||
static inline void __init construct_default_ISA_mptable(int mpc_default_type)
|
||||
{
|
||||
struct mpc_config_processor processor;
|
||||
struct mpc_config_bus bus;
|
||||
struct mpc_config_ioapic ioapic;
|
||||
struct mpc_config_lintsrc lintsrc;
|
||||
int linttypes[2] = { mp_ExtINT, mp_NMI };
|
||||
int i;
|
||||
|
||||
/*
|
||||
* local APIC has default address
|
||||
*/
|
||||
mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
|
||||
|
||||
/*
|
||||
* 2 CPUs, numbered 0 & 1.
|
||||
*/
|
||||
processor.mpc_type = MP_PROCESSOR;
|
||||
/* Either an integrated APIC or a discrete 82489DX. */
|
||||
processor.mpc_apicver = mpc_default_type > 4 ? 0x10 : 0x01;
|
||||
processor.mpc_cpuflag = CPU_ENABLED;
|
||||
processor.mpc_cpufeature = (boot_cpu_data.x86 << 8) |
|
||||
(boot_cpu_data.x86_model << 4) | boot_cpu_data.x86_mask;
|
||||
processor.mpc_featureflag = boot_cpu_data.x86_capability[0];
|
||||
processor.mpc_reserved[0] = 0;
|
||||
processor.mpc_reserved[1] = 0;
|
||||
for (i = 0; i < 2; i++) {
|
||||
processor.mpc_apicid = i;
|
||||
MP_processor_info(&processor);
|
||||
}
|
||||
|
||||
bus.mpc_type = MP_BUS;
|
||||
bus.mpc_busid = 0;
|
||||
switch (mpc_default_type) {
|
||||
default:
|
||||
printk(KERN_ERR "???\nUnknown standard configuration %d\n",
|
||||
mpc_default_type);
|
||||
/* fall through */
|
||||
case 1:
|
||||
case 5:
|
||||
memcpy(bus.mpc_bustype, "ISA ", 6);
|
||||
break;
|
||||
case 2:
|
||||
case 6:
|
||||
case 3:
|
||||
memcpy(bus.mpc_bustype, "EISA ", 6);
|
||||
break;
|
||||
case 4:
|
||||
case 7:
|
||||
memcpy(bus.mpc_bustype, "MCA ", 6);
|
||||
}
|
||||
MP_bus_info(&bus);
|
||||
if (mpc_default_type > 4) {
|
||||
bus.mpc_busid = 1;
|
||||
memcpy(bus.mpc_bustype, "PCI ", 6);
|
||||
MP_bus_info(&bus);
|
||||
}
|
||||
|
||||
ioapic.mpc_type = MP_IOAPIC;
|
||||
ioapic.mpc_apicid = 2;
|
||||
ioapic.mpc_apicver = mpc_default_type > 4 ? 0x10 : 0x01;
|
||||
ioapic.mpc_flags = MPC_APIC_USABLE;
|
||||
ioapic.mpc_apicaddr = 0xFEC00000;
|
||||
MP_ioapic_info(&ioapic);
|
||||
|
||||
/*
|
||||
* We set up most of the low 16 IO-APIC pins according to MPS rules.
|
||||
*/
|
||||
construct_default_ioirq_mptable(mpc_default_type);
|
||||
|
||||
lintsrc.mpc_type = MP_LINTSRC;
|
||||
lintsrc.mpc_irqflag = 0; /* conforming */
|
||||
lintsrc.mpc_srcbusid = 0;
|
||||
lintsrc.mpc_srcbusirq = 0;
|
||||
lintsrc.mpc_destapic = MP_APIC_ALL;
|
||||
for (i = 0; i < 2; i++) {
|
||||
lintsrc.mpc_irqtype = linttypes[i];
|
||||
lintsrc.mpc_destapiclint = i;
|
||||
MP_lintsrc_info(&lintsrc);
|
||||
}
|
||||
}
|
||||
|
||||
static struct intel_mp_floating *mpf_found;
|
||||
|
||||
/*
|
||||
* Scan the memory blocks for an SMP configuration block.
|
||||
*/
|
||||
static void __init __get_smp_config(unsigned early)
|
||||
{
|
||||
struct intel_mp_floating *mpf = mpf_found;
|
||||
|
||||
if (acpi_lapic && early)
|
||||
return;
|
||||
/*
|
||||
* ACPI supports both logical (e.g. Hyper-Threading) and physical
|
||||
* processors, where MPS only supports physical.
|
||||
*/
|
||||
if (acpi_lapic && acpi_ioapic) {
|
||||
printk(KERN_INFO "Using ACPI (MADT) for SMP configuration "
|
||||
"information\n");
|
||||
return;
|
||||
} else if (acpi_lapic)
|
||||
printk(KERN_INFO "Using ACPI for processor (LAPIC) "
|
||||
"configuration information\n");
|
||||
|
||||
printk(KERN_INFO "Intel MultiProcessor Specification v1.%d\n",
|
||||
mpf->mpf_specification);
|
||||
#ifdef CONFIG_X86_32
|
||||
if (mpf->mpf_feature2 & (1 << 7)) {
|
||||
printk(KERN_INFO " IMCR and PIC compatibility mode.\n");
|
||||
pic_mode = 1;
|
||||
} else {
|
||||
printk(KERN_INFO " Virtual Wire compatibility mode.\n");
|
||||
pic_mode = 0;
|
||||
}
|
||||
#endif
|
||||
/*
|
||||
* Now see if we need to read further.
|
||||
*/
|
||||
if (mpf->mpf_feature1 != 0) {
|
||||
if (early) {
|
||||
/*
|
||||
* local APIC has default address
|
||||
*/
|
||||
mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
|
||||
return;
|
||||
}
|
||||
|
||||
printk(KERN_INFO "Default MP configuration #%d\n",
|
||||
mpf->mpf_feature1);
|
||||
construct_default_ISA_mptable(mpf->mpf_feature1);
|
||||
|
||||
} else if (mpf->mpf_physptr) {
|
||||
|
||||
/*
|
||||
* Read the physical hardware table. Anything here will
|
||||
* override the defaults.
|
||||
*/
|
||||
if (!smp_read_mpc(phys_to_virt(mpf->mpf_physptr), early)) {
|
||||
smp_found_config = 0;
|
||||
printk(KERN_ERR
|
||||
"BIOS bug, MP table errors detected!...\n");
|
||||
printk(KERN_ERR "... disabling SMP support. "
|
||||
"(tell your hw vendor)\n");
|
||||
return;
|
||||
}
|
||||
|
||||
if (early)
|
||||
return;
|
||||
/*
|
||||
* If there are no explicit MP IRQ entries, then we are
|
||||
* broken. We set up most of the low 16 IO-APIC pins to
|
||||
* ISA defaults and hope it will work.
|
||||
*/
|
||||
if (!mp_irq_entries) {
|
||||
struct mpc_config_bus bus;
|
||||
|
||||
printk(KERN_ERR "BIOS bug, no explicit IRQ entries, "
|
||||
"using default mptable. "
|
||||
"(tell your hw vendor)\n");
|
||||
|
||||
bus.mpc_type = MP_BUS;
|
||||
bus.mpc_busid = 0;
|
||||
memcpy(bus.mpc_bustype, "ISA ", 6);
|
||||
MP_bus_info(&bus);
|
||||
|
||||
construct_default_ioirq_mptable(0);
|
||||
}
|
||||
|
||||
} else
|
||||
BUG();
|
||||
|
||||
if (!early)
|
||||
printk(KERN_INFO "Processors: %d\n", num_processors);
|
||||
/*
|
||||
* Only use the first configuration found.
|
||||
*/
|
||||
}
|
||||
|
||||
void __init early_get_smp_config(void)
|
||||
{
|
||||
__get_smp_config(1);
|
||||
}
|
||||
|
||||
void __init get_smp_config(void)
|
||||
{
|
||||
__get_smp_config(0);
|
||||
}
|
||||
|
||||
static int __init smp_scan_config(unsigned long base, unsigned long length,
|
||||
unsigned reserve)
|
||||
{
|
||||
extern void __bad_mpf_size(void);
|
||||
unsigned int *bp = phys_to_virt(base);
|
||||
struct intel_mp_floating *mpf;
|
||||
|
||||
Dprintk("Scan SMP from %p for %ld bytes.\n", bp, length);
|
||||
if (sizeof(*mpf) != 16)
|
||||
__bad_mpf_size();
|
||||
|
||||
while (length > 0) {
|
||||
mpf = (struct intel_mp_floating *)bp;
|
||||
if ((*bp == SMP_MAGIC_IDENT) &&
|
||||
(mpf->mpf_length == 1) &&
|
||||
!mpf_checksum((unsigned char *)bp, 16) &&
|
||||
((mpf->mpf_specification == 1)
|
||||
|| (mpf->mpf_specification == 4))) {
|
||||
|
||||
smp_found_config = 1;
|
||||
mpf_found = mpf;
|
||||
#ifdef CONFIG_X86_32
|
||||
printk(KERN_INFO "found SMP MP-table at [%p] %08lx\n",
|
||||
mpf, virt_to_phys(mpf));
|
||||
reserve_bootmem(virt_to_phys(mpf), PAGE_SIZE,
|
||||
BOOTMEM_DEFAULT);
|
||||
if (mpf->mpf_physptr) {
|
||||
/*
|
||||
* We cannot access to MPC table to compute
|
||||
* table size yet, as only few megabytes from
|
||||
* the bottom is mapped now.
|
||||
* PC-9800's MPC table places on the very last
|
||||
* of physical memory; so that simply reserving
|
||||
* PAGE_SIZE from mpg->mpf_physptr yields BUG()
|
||||
* in reserve_bootmem.
|
||||
*/
|
||||
unsigned long size = PAGE_SIZE;
|
||||
unsigned long end = max_low_pfn * PAGE_SIZE;
|
||||
if (mpf->mpf_physptr + size > end)
|
||||
size = end - mpf->mpf_physptr;
|
||||
reserve_bootmem(mpf->mpf_physptr, size,
|
||||
BOOTMEM_DEFAULT);
|
||||
}
|
||||
|
||||
#else
|
||||
if (!reserve)
|
||||
return 1;
|
||||
|
||||
reserve_bootmem_generic(virt_to_phys(mpf), PAGE_SIZE);
|
||||
if (mpf->mpf_physptr)
|
||||
reserve_bootmem_generic(mpf->mpf_physptr,
|
||||
PAGE_SIZE);
|
||||
#endif
|
||||
return 1;
|
||||
}
|
||||
bp += 4;
|
||||
length -= 16;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void __init __find_smp_config(unsigned reserve)
|
||||
{
|
||||
unsigned int address;
|
||||
|
||||
/*
|
||||
* FIXME: Linux assumes you have 640K of base ram..
|
||||
* this continues the error...
|
||||
*
|
||||
* 1) Scan the bottom 1K for a signature
|
||||
* 2) Scan the top 1K of base RAM
|
||||
* 3) Scan the 64K of bios
|
||||
*/
|
||||
if (smp_scan_config(0x0, 0x400, reserve) ||
|
||||
smp_scan_config(639 * 0x400, 0x400, reserve) ||
|
||||
smp_scan_config(0xF0000, 0x10000, reserve))
|
||||
return;
|
||||
/*
|
||||
* If it is an SMP machine we should know now.
|
||||
*
|
||||
* there is a real-mode segmented pointer pointing to the
|
||||
* 4K EBDA area at 0x40E, calculate and scan it here.
|
||||
*
|
||||
* NOTE! There are Linux loaders that will corrupt the EBDA
|
||||
* area, and as such this kind of SMP config may be less
|
||||
* trustworthy, simply because the SMP table may have been
|
||||
* stomped on during early boot. These loaders are buggy and
|
||||
* should be fixed.
|
||||
*
|
||||
* MP1.4 SPEC states to only scan first 1K of 4K EBDA.
|
||||
*/
|
||||
|
||||
address = get_bios_ebda();
|
||||
if (address)
|
||||
smp_scan_config(address, 0x400, reserve);
|
||||
}
|
||||
|
||||
void __init early_find_smp_config(void)
|
||||
{
|
||||
__find_smp_config(0);
|
||||
}
|
||||
|
||||
void __init find_smp_config(void)
|
||||
{
|
||||
__find_smp_config(1);
|
||||
}
|
||||
|
||||
/* --------------------------------------------------------------------------
|
||||
ACPI-based MP Configuration
|
||||
-------------------------------------------------------------------------- */
|
||||
|
||||
#ifdef CONFIG_ACPI
|
||||
|
||||
#ifdef CONFIG_X86_IO_APIC
|
||||
|
||||
#define MP_ISA_BUS 0
|
||||
#define MP_MAX_IOAPIC_PIN 127
|
||||
|
||||
extern struct mp_ioapic_routing mp_ioapic_routing[MAX_IO_APICS];
|
||||
|
||||
static int mp_find_ioapic(int gsi)
|
||||
{
|
||||
int i = 0;
|
||||
|
||||
/* Find the IOAPIC that manages this GSI. */
|
||||
for (i = 0; i < nr_ioapics; i++) {
|
||||
if ((gsi >= mp_ioapic_routing[i].gsi_base)
|
||||
&& (gsi <= mp_ioapic_routing[i].gsi_end))
|
||||
return i;
|
||||
}
|
||||
|
||||
printk(KERN_ERR "ERROR: Unable to locate IOAPIC for GSI %d\n", gsi);
|
||||
return -1;
|
||||
}
|
||||
|
||||
static u8 uniq_ioapic_id(u8 id)
|
||||
{
|
||||
#ifdef CONFIG_X86_32
|
||||
if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) &&
|
||||
!APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
|
||||
return io_apic_get_unique_id(nr_ioapics, id);
|
||||
else
|
||||
return id;
|
||||
#else
|
||||
int i;
|
||||
DECLARE_BITMAP(used, 256);
|
||||
bitmap_zero(used, 256);
|
||||
for (i = 0; i < nr_ioapics; i++) {
|
||||
struct mpc_config_ioapic *ia = &mp_ioapics[i];
|
||||
__set_bit(ia->mpc_apicid, used);
|
||||
}
|
||||
if (!test_bit(id, used))
|
||||
return id;
|
||||
return find_first_zero_bit(used, 256);
|
||||
#endif
|
||||
}
|
||||
|
||||
void __init mp_register_ioapic(int id, u32 address, u32 gsi_base)
|
||||
{
|
||||
int idx = 0;
|
||||
|
||||
if (bad_ioapic(address))
|
||||
return;
|
||||
|
||||
idx = nr_ioapics;
|
||||
|
||||
mp_ioapics[idx].mpc_type = MP_IOAPIC;
|
||||
mp_ioapics[idx].mpc_flags = MPC_APIC_USABLE;
|
||||
mp_ioapics[idx].mpc_apicaddr = address;
|
||||
|
||||
set_fixmap_nocache(FIX_IO_APIC_BASE_0 + idx, address);
|
||||
mp_ioapics[idx].mpc_apicid = uniq_ioapic_id(id);
|
||||
#ifdef CONFIG_X86_32
|
||||
mp_ioapics[idx].mpc_apicver = io_apic_get_version(idx);
|
||||
#else
|
||||
mp_ioapics[idx].mpc_apicver = 0;
|
||||
#endif
|
||||
/*
|
||||
* Build basic GSI lookup table to facilitate gsi->io_apic lookups
|
||||
* and to prevent reprogramming of IOAPIC pins (PCI GSIs).
|
||||
*/
|
||||
mp_ioapic_routing[idx].apic_id = mp_ioapics[idx].mpc_apicid;
|
||||
mp_ioapic_routing[idx].gsi_base = gsi_base;
|
||||
mp_ioapic_routing[idx].gsi_end = gsi_base +
|
||||
io_apic_get_redir_entries(idx);
|
||||
|
||||
printk(KERN_INFO "IOAPIC[%d]: apic_id %d, address 0x%x, "
|
||||
"GSI %d-%d\n", idx, mp_ioapics[idx].mpc_apicid,
|
||||
mp_ioapics[idx].mpc_apicver, mp_ioapics[idx].mpc_apicaddr,
|
||||
mp_ioapic_routing[idx].gsi_base, mp_ioapic_routing[idx].gsi_end);
|
||||
|
||||
nr_ioapics++;
|
||||
}
|
||||
|
||||
void __init mp_override_legacy_irq(u8 bus_irq, u8 polarity, u8 trigger, u32 gsi)
|
||||
{
|
||||
struct mpc_config_intsrc intsrc;
|
||||
int ioapic = -1;
|
||||
int pin = -1;
|
||||
|
||||
/*
|
||||
* Convert 'gsi' to 'ioapic.pin'.
|
||||
*/
|
||||
ioapic = mp_find_ioapic(gsi);
|
||||
if (ioapic < 0)
|
||||
return;
|
||||
pin = gsi - mp_ioapic_routing[ioapic].gsi_base;
|
||||
|
||||
/*
|
||||
* TBD: This check is for faulty timer entries, where the override
|
||||
* erroneously sets the trigger to level, resulting in a HUGE
|
||||
* increase of timer interrupts!
|
||||
*/
|
||||
if ((bus_irq == 0) && (trigger == 3))
|
||||
trigger = 1;
|
||||
|
||||
intsrc.mpc_type = MP_INTSRC;
|
||||
intsrc.mpc_irqtype = mp_INT;
|
||||
intsrc.mpc_irqflag = (trigger << 2) | polarity;
|
||||
intsrc.mpc_srcbus = MP_ISA_BUS;
|
||||
intsrc.mpc_srcbusirq = bus_irq; /* IRQ */
|
||||
intsrc.mpc_dstapic = mp_ioapics[ioapic].mpc_apicid; /* APIC ID */
|
||||
intsrc.mpc_dstirq = pin; /* INTIN# */
|
||||
|
||||
Dprintk("Int: type %d, pol %d, trig %d, bus %d, irq %d, %d-%d\n",
|
||||
intsrc.mpc_irqtype, intsrc.mpc_irqflag & 3,
|
||||
(intsrc.mpc_irqflag >> 2) & 3, intsrc.mpc_srcbus,
|
||||
intsrc.mpc_srcbusirq, intsrc.mpc_dstapic, intsrc.mpc_dstirq);
|
||||
|
||||
mp_irqs[mp_irq_entries] = intsrc;
|
||||
if (++mp_irq_entries == MAX_IRQ_SOURCES)
|
||||
panic("Max # of irq sources exceeded!\n");
|
||||
}
|
||||
|
||||
int es7000_plat;
|
||||
|
||||
void __init mp_config_acpi_legacy_irqs(void)
|
||||
{
|
||||
struct mpc_config_intsrc intsrc;
|
||||
int i = 0;
|
||||
int ioapic = -1;
|
||||
|
||||
#if defined (CONFIG_MCA) || defined (CONFIG_EISA)
|
||||
/*
|
||||
* Fabricate the legacy ISA bus (bus #31).
|
||||
*/
|
||||
mp_bus_id_to_type[MP_ISA_BUS] = MP_BUS_ISA;
|
||||
#endif
|
||||
set_bit(MP_ISA_BUS, mp_bus_not_pci);
|
||||
Dprintk("Bus #%d is ISA\n", MP_ISA_BUS);
|
||||
|
||||
/*
|
||||
* Older generations of ES7000 have no legacy identity mappings
|
||||
*/
|
||||
if (es7000_plat == 1)
|
||||
return;
|
||||
|
||||
/*
|
||||
* Locate the IOAPIC that manages the ISA IRQs (0-15).
|
||||
*/
|
||||
ioapic = mp_find_ioapic(0);
|
||||
if (ioapic < 0)
|
||||
return;
|
||||
|
||||
intsrc.mpc_type = MP_INTSRC;
|
||||
intsrc.mpc_irqflag = 0; /* Conforming */
|
||||
intsrc.mpc_srcbus = MP_ISA_BUS;
|
||||
intsrc.mpc_dstapic = mp_ioapics[ioapic].mpc_apicid;
|
||||
|
||||
/*
|
||||
* Use the default configuration for the IRQs 0-15. Unless
|
||||
* overridden by (MADT) interrupt source override entries.
|
||||
*/
|
||||
for (i = 0; i < 16; i++) {
|
||||
int idx;
|
||||
|
||||
for (idx = 0; idx < mp_irq_entries; idx++) {
|
||||
struct mpc_config_intsrc *irq = mp_irqs + idx;
|
||||
|
||||
/* Do we already have a mapping for this ISA IRQ? */
|
||||
if (irq->mpc_srcbus == MP_ISA_BUS
|
||||
&& irq->mpc_srcbusirq == i)
|
||||
break;
|
||||
|
||||
/* Do we already have a mapping for this IOAPIC pin */
|
||||
if ((irq->mpc_dstapic == intsrc.mpc_dstapic) &&
|
||||
(irq->mpc_dstirq == i))
|
||||
break;
|
||||
}
|
||||
|
||||
if (idx != mp_irq_entries) {
|
||||
printk(KERN_DEBUG "ACPI: IRQ%d used by override.\n", i);
|
||||
continue; /* IRQ already used */
|
||||
}
|
||||
|
||||
intsrc.mpc_irqtype = mp_INT;
|
||||
intsrc.mpc_srcbusirq = i; /* Identity mapped */
|
||||
intsrc.mpc_dstirq = i;
|
||||
|
||||
Dprintk("Int: type %d, pol %d, trig %d, bus %d, irq %d, "
|
||||
"%d-%d\n", intsrc.mpc_irqtype, intsrc.mpc_irqflag & 3,
|
||||
(intsrc.mpc_irqflag >> 2) & 3, intsrc.mpc_srcbus,
|
||||
intsrc.mpc_srcbusirq, intsrc.mpc_dstapic,
|
||||
intsrc.mpc_dstirq);
|
||||
|
||||
mp_irqs[mp_irq_entries] = intsrc;
|
||||
if (++mp_irq_entries == MAX_IRQ_SOURCES)
|
||||
panic("Max # of irq sources exceeded!\n");
|
||||
}
|
||||
}
|
||||
|
||||
int mp_register_gsi(u32 gsi, int triggering, int polarity)
|
||||
{
|
||||
int ioapic = -1;
|
||||
int ioapic_pin = 0;
|
||||
int idx, bit = 0;
|
||||
#ifdef CONFIG_X86_32
|
||||
#define MAX_GSI_NUM 4096
|
||||
#define IRQ_COMPRESSION_START 64
|
||||
|
||||
static int pci_irq = IRQ_COMPRESSION_START;
|
||||
/*
|
||||
* Mapping between Global System Interrupts, which
|
||||
* represent all possible interrupts, and IRQs
|
||||
* assigned to actual devices.
|
||||
*/
|
||||
static int gsi_to_irq[MAX_GSI_NUM];
|
||||
#else
|
||||
|
||||
if (acpi_irq_model != ACPI_IRQ_MODEL_IOAPIC)
|
||||
return gsi;
|
||||
#endif
|
||||
|
||||
/* Don't set up the ACPI SCI because it's already set up */
|
||||
if (acpi_gbl_FADT.sci_interrupt == gsi)
|
||||
return gsi;
|
||||
|
||||
ioapic = mp_find_ioapic(gsi);
|
||||
if (ioapic < 0) {
|
||||
printk(KERN_WARNING "No IOAPIC for GSI %u\n", gsi);
|
||||
return gsi;
|
||||
}
|
||||
|
||||
ioapic_pin = gsi - mp_ioapic_routing[ioapic].gsi_base;
|
||||
|
||||
#ifdef CONFIG_X86_32
|
||||
if (ioapic_renumber_irq)
|
||||
gsi = ioapic_renumber_irq(ioapic, gsi);
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Avoid pin reprogramming. PRTs typically include entries
|
||||
* with redundant pin->gsi mappings (but unique PCI devices);
|
||||
* we only program the IOAPIC on the first.
|
||||
*/
|
||||
bit = ioapic_pin % 32;
|
||||
idx = (ioapic_pin < 32) ? 0 : (ioapic_pin / 32);
|
||||
if (idx > 3) {
|
||||
printk(KERN_ERR "Invalid reference to IOAPIC pin "
|
||||
"%d-%d\n", mp_ioapic_routing[ioapic].apic_id,
|
||||
ioapic_pin);
|
||||
return gsi;
|
||||
}
|
||||
if ((1 << bit) & mp_ioapic_routing[ioapic].pin_programmed[idx]) {
|
||||
Dprintk(KERN_DEBUG "Pin %d-%d already programmed\n",
|
||||
mp_ioapic_routing[ioapic].apic_id, ioapic_pin);
|
||||
#ifdef CONFIG_X86_32
|
||||
return (gsi < IRQ_COMPRESSION_START ? gsi : gsi_to_irq[gsi]);
|
||||
#else
|
||||
return gsi;
|
||||
#endif
|
||||
}
|
||||
|
||||
mp_ioapic_routing[ioapic].pin_programmed[idx] |= (1 << bit);
|
||||
#ifdef CONFIG_X86_32
|
||||
/*
|
||||
* For GSI >= 64, use IRQ compression
|
||||
*/
|
||||
if ((gsi >= IRQ_COMPRESSION_START)
|
||||
&& (triggering == ACPI_LEVEL_SENSITIVE)) {
|
||||
/*
|
||||
* For PCI devices assign IRQs in order, avoiding gaps
|
||||
* due to unused I/O APIC pins.
|
||||
*/
|
||||
int irq = gsi;
|
||||
if (gsi < MAX_GSI_NUM) {
|
||||
/*
|
||||
* Retain the VIA chipset work-around (gsi > 15), but
|
||||
* avoid a problem where the 8254 timer (IRQ0) is setup
|
||||
* via an override (so it's not on pin 0 of the ioapic),
|
||||
* and at the same time, the pin 0 interrupt is a PCI
|
||||
* type. The gsi > 15 test could cause these two pins
|
||||
* to be shared as IRQ0, and they are not shareable.
|
||||
* So test for this condition, and if necessary, avoid
|
||||
* the pin collision.
|
||||
*/
|
||||
gsi = pci_irq++;
|
||||
/*
|
||||
* Don't assign IRQ used by ACPI SCI
|
||||
*/
|
||||
if (gsi == acpi_gbl_FADT.sci_interrupt)
|
||||
gsi = pci_irq++;
|
||||
gsi_to_irq[irq] = gsi;
|
||||
} else {
|
||||
printk(KERN_ERR "GSI %u is too high\n", gsi);
|
||||
return gsi;
|
||||
}
|
||||
}
|
||||
#endif
|
||||
io_apic_set_pci_routing(ioapic, ioapic_pin, gsi,
|
||||
triggering == ACPI_EDGE_SENSITIVE ? 0 : 1,
|
||||
polarity == ACPI_ACTIVE_HIGH ? 0 : 1);
|
||||
return gsi;
|
||||
}
|
||||
|
||||
#endif /* CONFIG_X86_IO_APIC */
|
||||
#endif /* CONFIG_ACPI */
|
||||
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