Merge branch 'drm-fixes' of git://people.freedesktop.org/~airlied/linux
Pull drm fixes from Dave Airlie:
"Nothing too scary, we have one outstanding i915 regression but Daniel
has promised the fix as soon as he's finished testing it a bit.
Fixes for the main x86 drivers:
- radeon: dpm fixes, displayport regression fix
- i915: quirks for backlight regression, edp reboot fix, valleyview
black screen fixes
- nouveau: display port regression fixes, fix for memory reclocking"
* 'drm-fixes' of git://people.freedesktop.org/~airlied/linux:
drm/radeon/dpm: Reenabling SS on Cayman
drm/radeon: fix typo in ci_stop_dpm()
drm/radeon: fix typo in golden register setup on evergreen
drm/radeon: only print meaningful VM faults
drm/radeon/dp: return -EIO for flags not zero case
drm/i915/vlv: T12 eDP panel timing enforcement during reboot
drm/i915: Only unbind vgacon, not other console drivers
drm/i915: Don't clobber the GTT when it's within stolen memory
drm/i915/vlv: Update the DSI ULPS entry/exit sequence
drm/i915/vlv: DPI FIFO empty check is not needed
drm/i915: Toshiba CB35 has a controllable backlight
drm/i915: Acer C720 and C720P have controllable backlights
drm/i915: quirk asserts controllable backlight presence, overriding VBT
drm/nouveau/ram: fix test for gpio presence
drm/nouveau/dp: workaround broken display
drm/nouveau/dp: fix required link bandwidth calculations
drm/nouveau/kms: restore fbcon after display has been resumed
drm/nv50-/kms: pass a non-zero value for head to sor dpms methods
drm/nouveau/fb: Prevent inlining of ramfuc_reg
drm/gk104/ram: bash mpll bit 31 on
This commit is contained in:
Linus Torvalds
Коммит
85d90faed3
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@ -1464,12 +1464,13 @@ static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
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#else
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static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
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{
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int ret;
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int ret = 0;
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DRM_INFO("Replacing VGA console driver\n");
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console_lock();
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ret = do_take_over_console(&dummy_con, 0, MAX_NR_CONSOLES - 1, 1);
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if (con_is_bound(&vga_con))
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ret = do_take_over_console(&dummy_con, 0, MAX_NR_CONSOLES - 1, 1);
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if (ret == 0) {
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ret = do_unregister_con_driver(&vga_con);
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@ -656,6 +656,7 @@ enum intel_sbi_destination {
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#define QUIRK_PIPEA_FORCE (1<<0)
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#define QUIRK_LVDS_SSC_DISABLE (1<<1)
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#define QUIRK_INVERT_BRIGHTNESS (1<<2)
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#define QUIRK_BACKLIGHT_PRESENT (1<<3)
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struct intel_fbdev;
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struct intel_fbc_work;
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@ -74,6 +74,50 @@ static unsigned long i915_stolen_to_physical(struct drm_device *dev)
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if (base == 0)
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return 0;
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/* make sure we don't clobber the GTT if it's within stolen memory */
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if (INTEL_INFO(dev)->gen <= 4 && !IS_G33(dev) && !IS_G4X(dev)) {
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struct {
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u32 start, end;
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} stolen[2] = {
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{ .start = base, .end = base + dev_priv->gtt.stolen_size, },
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{ .start = base, .end = base + dev_priv->gtt.stolen_size, },
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};
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u64 gtt_start, gtt_end;
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gtt_start = I915_READ(PGTBL_CTL);
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if (IS_GEN4(dev))
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gtt_start = (gtt_start & PGTBL_ADDRESS_LO_MASK) |
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(gtt_start & PGTBL_ADDRESS_HI_MASK) << 28;
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else
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gtt_start &= PGTBL_ADDRESS_LO_MASK;
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gtt_end = gtt_start + gtt_total_entries(dev_priv->gtt) * 4;
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if (gtt_start >= stolen[0].start && gtt_start < stolen[0].end)
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stolen[0].end = gtt_start;
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if (gtt_end > stolen[1].start && gtt_end <= stolen[1].end)
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stolen[1].start = gtt_end;
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/* pick the larger of the two chunks */
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if (stolen[0].end - stolen[0].start >
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stolen[1].end - stolen[1].start) {
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base = stolen[0].start;
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dev_priv->gtt.stolen_size = stolen[0].end - stolen[0].start;
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} else {
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base = stolen[1].start;
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dev_priv->gtt.stolen_size = stolen[1].end - stolen[1].start;
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}
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if (stolen[0].start != stolen[1].start ||
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stolen[0].end != stolen[1].end) {
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DRM_DEBUG_KMS("GTT within stolen memory at 0x%llx-0x%llx\n",
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(unsigned long long) gtt_start,
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(unsigned long long) gtt_end - 1);
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DRM_DEBUG_KMS("Stolen memory adjusted to 0x%x-0x%x\n",
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base, base + (u32) dev_priv->gtt.stolen_size - 1);
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}
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}
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/* Verify that nothing else uses this physical address. Stolen
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* memory should be reserved by the BIOS and hidden from the
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* kernel. So if the region is already marked as busy, something
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@ -942,6 +942,9 @@ enum punit_power_well {
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/*
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* Instruction and interrupt control regs
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*/
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#define PGTBL_CTL 0x02020
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#define PGTBL_ADDRESS_LO_MASK 0xfffff000 /* bits [31:12] */
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#define PGTBL_ADDRESS_HI_MASK 0x000000f0 /* bits [35:32] (gen4) */
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#define PGTBL_ER 0x02024
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#define RENDER_RING_BASE 0x02000
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#define BSD_RING_BASE 0x04000
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|
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@ -11591,6 +11591,14 @@ static void quirk_invert_brightness(struct drm_device *dev)
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DRM_INFO("applying inverted panel brightness quirk\n");
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}
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/* Some VBT's incorrectly indicate no backlight is present */
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static void quirk_backlight_present(struct drm_device *dev)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
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DRM_INFO("applying backlight present quirk\n");
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}
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struct intel_quirk {
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int device;
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int subsystem_vendor;
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@ -11659,6 +11667,12 @@ static struct intel_quirk intel_quirks[] = {
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/* Acer Aspire 5336 */
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{ 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
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/* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
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{ 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
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/* Toshiba CB35 Chromebook (Celeron 2955U) */
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{ 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
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};
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static void intel_init_quirks(struct drm_device *dev)
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@ -28,6 +28,8 @@
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#include <linux/i2c.h>
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#include <linux/slab.h>
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#include <linux/export.h>
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#include <linux/notifier.h>
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#include <linux/reboot.h>
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#include <drm/drmP.h>
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#include <drm/drm_crtc.h>
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#include <drm/drm_crtc_helper.h>
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@ -336,6 +338,37 @@ static u32 _pp_stat_reg(struct intel_dp *intel_dp)
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return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp));
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}
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/* Reboot notifier handler to shutdown panel power to guarantee T12 timing
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This function only applicable when panel PM state is not to be tracked */
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static int edp_notify_handler(struct notifier_block *this, unsigned long code,
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void *unused)
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{
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struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp),
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edp_notifier);
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struct drm_device *dev = intel_dp_to_dev(intel_dp);
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struct drm_i915_private *dev_priv = dev->dev_private;
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u32 pp_div;
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u32 pp_ctrl_reg, pp_div_reg;
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enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
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if (!is_edp(intel_dp) || code != SYS_RESTART)
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return 0;
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if (IS_VALLEYVIEW(dev)) {
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pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
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pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
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pp_div = I915_READ(pp_div_reg);
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pp_div &= PP_REFERENCE_DIVIDER_MASK;
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/* 0x1F write to PP_DIV_REG sets max cycle delay */
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I915_WRITE(pp_div_reg, pp_div | 0x1F);
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I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS | PANEL_POWER_OFF);
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msleep(intel_dp->panel_power_cycle_delay);
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}
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return 0;
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}
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static bool edp_have_panel_power(struct intel_dp *intel_dp)
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{
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struct drm_device *dev = intel_dp_to_dev(intel_dp);
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@ -3707,6 +3740,10 @@ void intel_dp_encoder_destroy(struct drm_encoder *encoder)
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drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
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edp_panel_vdd_off_sync(intel_dp);
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drm_modeset_unlock(&dev->mode_config.connection_mutex);
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if (intel_dp->edp_notifier.notifier_call) {
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unregister_reboot_notifier(&intel_dp->edp_notifier);
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intel_dp->edp_notifier.notifier_call = NULL;
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}
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}
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kfree(intel_dig_port);
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}
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@ -4184,6 +4221,11 @@ static bool intel_edp_init_connector(struct intel_dp *intel_dp,
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}
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mutex_unlock(&dev->mode_config.mutex);
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if (IS_VALLEYVIEW(dev)) {
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intel_dp->edp_notifier.notifier_call = edp_notify_handler;
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register_reboot_notifier(&intel_dp->edp_notifier);
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}
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intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
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intel_panel_setup_backlight(connector);
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@ -538,6 +538,8 @@ struct intel_dp {
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unsigned long last_power_on;
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unsigned long last_backlight_off;
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bool psr_setup_done;
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struct notifier_block edp_notifier;
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bool use_tps3;
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struct intel_connector *attached_connector;
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@ -117,17 +117,18 @@ static void intel_dsi_device_ready(struct intel_encoder *encoder)
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/* bandgap reset is needed after everytime we do power gate */
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band_gap_reset(dev_priv);
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I915_WRITE(MIPI_DEVICE_READY(pipe), ULPS_STATE_ENTER);
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usleep_range(2500, 3000);
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val = I915_READ(MIPI_PORT_CTRL(pipe));
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I915_WRITE(MIPI_PORT_CTRL(pipe), val | LP_OUTPUT_HOLD);
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usleep_range(1000, 1500);
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I915_WRITE(MIPI_DEVICE_READY(pipe), DEVICE_READY | ULPS_STATE_EXIT);
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usleep_range(2000, 2500);
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I915_WRITE(MIPI_DEVICE_READY(pipe), ULPS_STATE_EXIT);
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usleep_range(2500, 3000);
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I915_WRITE(MIPI_DEVICE_READY(pipe), DEVICE_READY);
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usleep_range(2000, 2500);
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I915_WRITE(MIPI_DEVICE_READY(pipe), 0x00);
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usleep_range(2000, 2500);
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I915_WRITE(MIPI_DEVICE_READY(pipe), DEVICE_READY);
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usleep_range(2000, 2500);
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usleep_range(2500, 3000);
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}
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static void intel_dsi_enable(struct intel_encoder *encoder)
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@ -271,23 +272,23 @@ static void intel_dsi_clear_device_ready(struct intel_encoder *encoder)
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DRM_DEBUG_KMS("\n");
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I915_WRITE(MIPI_DEVICE_READY(pipe), ULPS_STATE_ENTER);
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I915_WRITE(MIPI_DEVICE_READY(pipe), DEVICE_READY | ULPS_STATE_ENTER);
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usleep_range(2000, 2500);
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|
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I915_WRITE(MIPI_DEVICE_READY(pipe), ULPS_STATE_EXIT);
|
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I915_WRITE(MIPI_DEVICE_READY(pipe), DEVICE_READY | ULPS_STATE_EXIT);
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usleep_range(2000, 2500);
|
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|
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I915_WRITE(MIPI_DEVICE_READY(pipe), ULPS_STATE_ENTER);
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I915_WRITE(MIPI_DEVICE_READY(pipe), DEVICE_READY | ULPS_STATE_ENTER);
|
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usleep_range(2000, 2500);
|
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|
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val = I915_READ(MIPI_PORT_CTRL(pipe));
|
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I915_WRITE(MIPI_PORT_CTRL(pipe), val & ~LP_OUTPUT_HOLD);
|
||||
usleep_range(1000, 1500);
|
||||
|
||||
if (wait_for(((I915_READ(MIPI_PORT_CTRL(pipe)) & AFE_LATCHOUT)
|
||||
== 0x00000), 30))
|
||||
DRM_ERROR("DSI LP not going Low\n");
|
||||
|
||||
val = I915_READ(MIPI_PORT_CTRL(pipe));
|
||||
I915_WRITE(MIPI_PORT_CTRL(pipe), val & ~LP_OUTPUT_HOLD);
|
||||
usleep_range(1000, 1500);
|
||||
|
||||
I915_WRITE(MIPI_DEVICE_READY(pipe), 0x00);
|
||||
usleep_range(2000, 2500);
|
||||
|
||||
|
|
|
|||
|
|
@ -404,12 +404,6 @@ int dpi_send_cmd(struct intel_dsi *intel_dsi, u32 cmd, bool hs)
|
|||
else
|
||||
cmd |= DPI_LP_MODE;
|
||||
|
||||
/* DPI virtual channel?! */
|
||||
|
||||
mask = DPI_FIFO_EMPTY;
|
||||
if (wait_for((I915_READ(MIPI_GEN_FIFO_STAT(pipe)) & mask) == mask, 50))
|
||||
DRM_ERROR("Timeout waiting for DPI FIFO empty.\n");
|
||||
|
||||
/* clear bit */
|
||||
I915_WRITE(MIPI_INTR_STAT(pipe), SPL_PKT_SENT_INTERRUPT);
|
||||
|
||||
|
|
|
|||
|
|
@ -1118,8 +1118,12 @@ int intel_panel_setup_backlight(struct drm_connector *connector)
|
|||
int ret;
|
||||
|
||||
if (!dev_priv->vbt.backlight.present) {
|
||||
DRM_DEBUG_KMS("native backlight control not available per VBT\n");
|
||||
return 0;
|
||||
if (dev_priv->quirks & QUIRK_BACKLIGHT_PRESENT) {
|
||||
DRM_DEBUG_KMS("no backlight present per VBT, but present per quirk\n");
|
||||
} else {
|
||||
DRM_DEBUG_KMS("no backlight present per VBT\n");
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
|
||||
/* set level and max in panel struct */
|
||||
|
|
|
|||
|
|
@ -1516,11 +1516,11 @@ nv50_disp_intr_unk20_2(struct nv50_disp_priv *priv, int head)
|
|||
}
|
||||
|
||||
switch ((ctrl & 0x000f0000) >> 16) {
|
||||
case 6: datarate = pclk * 30 / 8; break;
|
||||
case 5: datarate = pclk * 24 / 8; break;
|
||||
case 6: datarate = pclk * 30; break;
|
||||
case 5: datarate = pclk * 24; break;
|
||||
case 2:
|
||||
default:
|
||||
datarate = pclk * 18 / 8;
|
||||
datarate = pclk * 18;
|
||||
break;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -1159,11 +1159,11 @@ nvd0_disp_intr_unk2_2(struct nv50_disp_priv *priv, int head)
|
|||
if (outp->info.type == DCB_OUTPUT_DP) {
|
||||
u32 sync = nv_rd32(priv, 0x660404 + (head * 0x300));
|
||||
switch ((sync & 0x000003c0) >> 6) {
|
||||
case 6: pclk = pclk * 30 / 8; break;
|
||||
case 5: pclk = pclk * 24 / 8; break;
|
||||
case 6: pclk = pclk * 30; break;
|
||||
case 5: pclk = pclk * 24; break;
|
||||
case 2:
|
||||
default:
|
||||
pclk = pclk * 18 / 8;
|
||||
pclk = pclk * 18;
|
||||
break;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -34,7 +34,7 @@ nvkm_output_dp_train(struct nvkm_output *base, u32 datarate, bool wait)
|
|||
struct nvkm_output_dp *outp = (void *)base;
|
||||
bool retrain = true;
|
||||
u8 link[2], stat[3];
|
||||
u32 rate;
|
||||
u32 linkrate;
|
||||
int ret, i;
|
||||
|
||||
/* check that the link is trained at a high enough rate */
|
||||
|
|
@ -44,8 +44,10 @@ nvkm_output_dp_train(struct nvkm_output *base, u32 datarate, bool wait)
|
|||
goto done;
|
||||
}
|
||||
|
||||
rate = link[0] * 27000 * (link[1] & DPCD_LC01_LANE_COUNT_SET);
|
||||
if (rate < ((datarate / 8) * 10)) {
|
||||
linkrate = link[0] * 27000 * (link[1] & DPCD_LC01_LANE_COUNT_SET);
|
||||
linkrate = (linkrate * 8) / 10; /* 8B/10B coding overhead */
|
||||
datarate = (datarate + 9) / 10; /* -> decakilobits */
|
||||
if (linkrate < datarate) {
|
||||
DBG("link not trained at sufficient rate\n");
|
||||
goto done;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -87,6 +87,7 @@ nv50_sor_mthd(struct nouveau_object *object, u32 mthd, void *args, u32 size)
|
|||
struct nvkm_output_dp *outpdp = (void *)outp;
|
||||
switch (data) {
|
||||
case NV94_DISP_SOR_DP_PWR_STATE_OFF:
|
||||
nouveau_event_put(outpdp->irq);
|
||||
((struct nvkm_output_dp_impl *)nv_oclass(outp))
|
||||
->lnk_pwr(outpdp, 0);
|
||||
atomic_set(&outpdp->lt.done, 0);
|
||||
|
|
|
|||
|
|
@ -26,7 +26,7 @@ ramfuc_reg2(u32 addr1, u32 addr2)
|
|||
};
|
||||
}
|
||||
|
||||
static inline struct ramfuc_reg
|
||||
static noinline struct ramfuc_reg
|
||||
ramfuc_reg(u32 addr)
|
||||
{
|
||||
return ramfuc_reg2(addr, addr);
|
||||
|
|
@ -107,7 +107,7 @@ ramfuc_nsec(struct ramfuc *ram, u32 nsec)
|
|||
|
||||
#define ram_init(s,p) ramfuc_init(&(s)->base, (p))
|
||||
#define ram_exec(s,e) ramfuc_exec(&(s)->base, (e))
|
||||
#define ram_have(s,r) ((s)->r_##r.addr != 0x000000)
|
||||
#define ram_have(s,r) ((s)->r_##r.addr[0] != 0x000000)
|
||||
#define ram_rd32(s,r) ramfuc_rd32(&(s)->base, &(s)->r_##r)
|
||||
#define ram_wr32(s,r,d) ramfuc_wr32(&(s)->base, &(s)->r_##r, (d))
|
||||
#define ram_nuke(s,r) ramfuc_nuke(&(s)->base, &(s)->r_##r)
|
||||
|
|
|
|||
|
|
@ -200,6 +200,7 @@ r1373f4_init(struct nve0_ramfuc *fuc)
|
|||
/* (re)program mempll, if required */
|
||||
if (ram->mode == 2) {
|
||||
ram_mask(fuc, 0x1373f4, 0x00010000, 0x00000000);
|
||||
ram_mask(fuc, 0x132000, 0x80000000, 0x80000000);
|
||||
ram_mask(fuc, 0x132000, 0x00000001, 0x00000000);
|
||||
ram_mask(fuc, 0x132004, 0x103fffff, mcoef);
|
||||
ram_mask(fuc, 0x132000, 0x00000001, 0x00000001);
|
||||
|
|
|
|||
|
|
@ -652,12 +652,12 @@ int nouveau_pmops_resume(struct device *dev)
|
|||
ret = nouveau_do_resume(drm_dev);
|
||||
if (ret)
|
||||
return ret;
|
||||
if (drm_dev->mode_config.num_crtc)
|
||||
nouveau_fbcon_set_suspend(drm_dev, 0);
|
||||
|
||||
nouveau_fbcon_zfill_all(drm_dev);
|
||||
if (drm_dev->mode_config.num_crtc)
|
||||
if (drm_dev->mode_config.num_crtc) {
|
||||
nouveau_display_resume(drm_dev);
|
||||
nouveau_fbcon_set_suspend(drm_dev, 0);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
@ -683,11 +683,12 @@ static int nouveau_pmops_thaw(struct device *dev)
|
|||
ret = nouveau_do_resume(drm_dev);
|
||||
if (ret)
|
||||
return ret;
|
||||
if (drm_dev->mode_config.num_crtc)
|
||||
nouveau_fbcon_set_suspend(drm_dev, 0);
|
||||
nouveau_fbcon_zfill_all(drm_dev);
|
||||
if (drm_dev->mode_config.num_crtc)
|
||||
|
||||
if (drm_dev->mode_config.num_crtc) {
|
||||
nouveau_display_resume(drm_dev);
|
||||
nouveau_fbcon_set_suspend(drm_dev, 0);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -531,17 +531,10 @@ nouveau_fbcon_set_suspend(struct drm_device *dev, int state)
|
|||
if (state == 1)
|
||||
nouveau_fbcon_save_disable_accel(dev);
|
||||
fb_set_suspend(drm->fbcon->helper.fbdev, state);
|
||||
if (state == 0)
|
||||
if (state == 0) {
|
||||
nouveau_fbcon_restore_accel(dev);
|
||||
nouveau_fbcon_zfill(dev, drm->fbcon);
|
||||
}
|
||||
console_unlock();
|
||||
}
|
||||
}
|
||||
|
||||
void
|
||||
nouveau_fbcon_zfill_all(struct drm_device *dev)
|
||||
{
|
||||
struct nouveau_drm *drm = nouveau_drm(dev);
|
||||
if (drm->fbcon) {
|
||||
nouveau_fbcon_zfill(dev, drm->fbcon);
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -61,7 +61,6 @@ void nouveau_fbcon_gpu_lockup(struct fb_info *info);
|
|||
int nouveau_fbcon_init(struct drm_device *dev);
|
||||
void nouveau_fbcon_fini(struct drm_device *dev);
|
||||
void nouveau_fbcon_set_suspend(struct drm_device *dev, int state);
|
||||
void nouveau_fbcon_zfill_all(struct drm_device *dev);
|
||||
void nouveau_fbcon_save_disable_accel(struct drm_device *dev);
|
||||
void nouveau_fbcon_restore_accel(struct drm_device *dev);
|
||||
|
||||
|
|
|
|||
|
|
@ -1741,7 +1741,8 @@ nv50_sor_dpms(struct drm_encoder *encoder, int mode)
|
|||
}
|
||||
}
|
||||
|
||||
mthd = (ffs(nv_encoder->dcb->sorconf.link) - 1) << 2;
|
||||
mthd = (ffs(nv_encoder->dcb->heads) - 1) << 3;
|
||||
mthd |= (ffs(nv_encoder->dcb->sorconf.link) - 1) << 2;
|
||||
mthd |= nv_encoder->or;
|
||||
|
||||
if (nv_encoder->dcb->type == DCB_OUTPUT_DP) {
|
||||
|
|
|
|||
|
|
@ -127,7 +127,7 @@ static int radeon_process_aux_ch(struct radeon_i2c_chan *chan,
|
|||
/* flags not zero */
|
||||
if (args.v1.ucReplyStatus == 2) {
|
||||
DRM_DEBUG_KMS("dp_aux_ch flags not zero\n");
|
||||
r = -EBUSY;
|
||||
r = -EIO;
|
||||
goto done;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -1179,7 +1179,7 @@ static int ci_stop_dpm(struct radeon_device *rdev)
|
|||
tmp &= ~GLOBAL_PWRMGT_EN;
|
||||
WREG32_SMC(GENERAL_PWRMGT, tmp);
|
||||
|
||||
tmp = RREG32(SCLK_PWRMGT_CNTL);
|
||||
tmp = RREG32_SMC(SCLK_PWRMGT_CNTL);
|
||||
tmp &= ~DYNAMIC_PM_EN;
|
||||
WREG32_SMC(SCLK_PWRMGT_CNTL, tmp);
|
||||
|
||||
|
|
|
|||
|
|
@ -7676,14 +7676,16 @@ restart_ih:
|
|||
addr = RREG32(VM_CONTEXT1_PROTECTION_FAULT_ADDR);
|
||||
status = RREG32(VM_CONTEXT1_PROTECTION_FAULT_STATUS);
|
||||
mc_client = RREG32(VM_CONTEXT1_PROTECTION_FAULT_MCCLIENT);
|
||||
/* reset addr and status */
|
||||
WREG32_P(VM_CONTEXT1_CNTL2, 1, ~1);
|
||||
if (addr == 0x0 && status == 0x0)
|
||||
break;
|
||||
dev_err(rdev->dev, "GPU fault detected: %d 0x%08x\n", src_id, src_data);
|
||||
dev_err(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n",
|
||||
addr);
|
||||
dev_err(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
|
||||
status);
|
||||
cik_vm_decode_fault(rdev, status, addr, mc_client);
|
||||
/* reset addr and status */
|
||||
WREG32_P(VM_CONTEXT1_CNTL2, 1, ~1);
|
||||
break;
|
||||
case 167: /* VCE */
|
||||
DRM_DEBUG("IH: VCE int: 0x%08x\n", src_data);
|
||||
|
|
|
|||
|
|
@ -189,7 +189,7 @@ static const u32 evergreen_golden_registers[] =
|
|||
0x8c1c, 0xffffffff, 0x00001010,
|
||||
0x28350, 0xffffffff, 0x00000000,
|
||||
0xa008, 0xffffffff, 0x00010000,
|
||||
0x5cc, 0xffffffff, 0x00000001,
|
||||
0x5c4, 0xffffffff, 0x00000001,
|
||||
0x9508, 0xffffffff, 0x00000002,
|
||||
0x913c, 0x0000000f, 0x0000000a
|
||||
};
|
||||
|
|
@ -476,7 +476,7 @@ static const u32 cedar_golden_registers[] =
|
|||
0x8c1c, 0xffffffff, 0x00001010,
|
||||
0x28350, 0xffffffff, 0x00000000,
|
||||
0xa008, 0xffffffff, 0x00010000,
|
||||
0x5cc, 0xffffffff, 0x00000001,
|
||||
0x5c4, 0xffffffff, 0x00000001,
|
||||
0x9508, 0xffffffff, 0x00000002
|
||||
};
|
||||
|
||||
|
|
@ -635,7 +635,7 @@ static const u32 juniper_mgcg_init[] =
|
|||
static const u32 supersumo_golden_registers[] =
|
||||
{
|
||||
0x5eb4, 0xffffffff, 0x00000002,
|
||||
0x5cc, 0xffffffff, 0x00000001,
|
||||
0x5c4, 0xffffffff, 0x00000001,
|
||||
0x7030, 0xffffffff, 0x00000011,
|
||||
0x7c30, 0xffffffff, 0x00000011,
|
||||
0x6104, 0x01000300, 0x00000000,
|
||||
|
|
@ -719,7 +719,7 @@ static const u32 sumo_golden_registers[] =
|
|||
static const u32 wrestler_golden_registers[] =
|
||||
{
|
||||
0x5eb4, 0xffffffff, 0x00000002,
|
||||
0x5cc, 0xffffffff, 0x00000001,
|
||||
0x5c4, 0xffffffff, 0x00000001,
|
||||
0x7030, 0xffffffff, 0x00000011,
|
||||
0x7c30, 0xffffffff, 0x00000011,
|
||||
0x6104, 0x01000300, 0x00000000,
|
||||
|
|
@ -5066,14 +5066,16 @@ restart_ih:
|
|||
case 147:
|
||||
addr = RREG32(VM_CONTEXT1_PROTECTION_FAULT_ADDR);
|
||||
status = RREG32(VM_CONTEXT1_PROTECTION_FAULT_STATUS);
|
||||
/* reset addr and status */
|
||||
WREG32_P(VM_CONTEXT1_CNTL2, 1, ~1);
|
||||
if (addr == 0x0 && status == 0x0)
|
||||
break;
|
||||
dev_err(rdev->dev, "GPU fault detected: %d 0x%08x\n", src_id, src_data);
|
||||
dev_err(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n",
|
||||
addr);
|
||||
dev_err(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
|
||||
status);
|
||||
cayman_vm_decode_fault(rdev, status, addr);
|
||||
/* reset addr and status */
|
||||
WREG32_P(VM_CONTEXT1_CNTL2, 1, ~1);
|
||||
break;
|
||||
case 176: /* CP_INT in ring buffer */
|
||||
case 177: /* CP_INT in IB1 */
|
||||
|
|
|
|||
|
|
@ -2329,12 +2329,6 @@ void rv770_get_engine_memory_ss(struct radeon_device *rdev)
|
|||
pi->mclk_ss = radeon_atombios_get_asic_ss_info(rdev, &ss,
|
||||
ASIC_INTERNAL_MEMORY_SS, 0);
|
||||
|
||||
/* disable ss, causes hangs on some cayman boards */
|
||||
if (rdev->family == CHIP_CAYMAN) {
|
||||
pi->sclk_ss = false;
|
||||
pi->mclk_ss = false;
|
||||
}
|
||||
|
||||
if (pi->sclk_ss || pi->mclk_ss)
|
||||
pi->dynamic_ss = true;
|
||||
else
|
||||
|
|
|
|||
|
|
@ -6376,14 +6376,16 @@ restart_ih:
|
|||
case 147:
|
||||
addr = RREG32(VM_CONTEXT1_PROTECTION_FAULT_ADDR);
|
||||
status = RREG32(VM_CONTEXT1_PROTECTION_FAULT_STATUS);
|
||||
/* reset addr and status */
|
||||
WREG32_P(VM_CONTEXT1_CNTL2, 1, ~1);
|
||||
if (addr == 0x0 && status == 0x0)
|
||||
break;
|
||||
dev_err(rdev->dev, "GPU fault detected: %d 0x%08x\n", src_id, src_data);
|
||||
dev_err(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n",
|
||||
addr);
|
||||
dev_err(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
|
||||
status);
|
||||
si_vm_decode_fault(rdev, status, addr);
|
||||
/* reset addr and status */
|
||||
WREG32_P(VM_CONTEXT1_CNTL2, 1, ~1);
|
||||
break;
|
||||
case 176: /* RINGID0 CP_INT */
|
||||
radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
|
||||
|
|
|
|||
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