Merge branch 'dice-driver-playback-only' of git://git.alsa-project.org/alsa-kprivate into for-next
This commit is contained in:
Takashi Iwai
Коммит
861e66d341
|
|
@ -138,6 +138,7 @@ Code Seq#(hex) Include File Comments
|
|||
'H' C0-DF net/bluetooth/cmtp/cmtp.h conflict!
|
||||
'H' C0-DF net/bluetooth/bnep/bnep.h conflict!
|
||||
'H' F1 linux/hid-roccat.h <mailto:erazor_de@users.sourceforge.net>
|
||||
'H' F8-FA sound/firewire.h
|
||||
'I' all linux/isdn.h conflict!
|
||||
'I' 00-0F drivers/isdn/divert/isdn_divert.h conflict!
|
||||
'I' 40-4F linux/mISDNif.h conflict!
|
||||
|
|
|
|||
|
|
@ -5,6 +5,7 @@ header-y += asound_fm.h
|
|||
header-y += compress_offload.h
|
||||
header-y += compress_params.h
|
||||
header-y += emu10k1.h
|
||||
header-y += firewire.h
|
||||
header-y += hdsp.h
|
||||
header-y += hdspm.h
|
||||
header-y += sb16_csp.h
|
||||
|
|
|
|||
|
|
@ -93,9 +93,10 @@ enum {
|
|||
SNDRV_HWDEP_IFACE_SB_RC, /* SB Extigy/Audigy2NX remote control */
|
||||
SNDRV_HWDEP_IFACE_HDA, /* HD-audio */
|
||||
SNDRV_HWDEP_IFACE_USB_STREAM, /* direct access to usb stream */
|
||||
SNDRV_HWDEP_IFACE_FW_DICE, /* TC DICE FireWire device */
|
||||
|
||||
/* Don't forget to change the following: */
|
||||
SNDRV_HWDEP_IFACE_LAST = SNDRV_HWDEP_IFACE_USB_STREAM
|
||||
SNDRV_HWDEP_IFACE_LAST = SNDRV_HWDEP_IFACE_FW_DICE
|
||||
};
|
||||
|
||||
struct snd_hwdep_info {
|
||||
|
|
|
|||
|
|
@ -0,0 +1,51 @@
|
|||
#ifndef UAPI_SOUND_FIREWIRE_H_INCLUDED
|
||||
#define UAPI_SOUND_FIREWIRE_H_INCLUDED
|
||||
|
||||
#include <linux/ioctl.h>
|
||||
|
||||
/* events can be read() from the hwdep device */
|
||||
|
||||
#define SNDRV_FIREWIRE_EVENT_LOCK_STATUS 0x000010cc
|
||||
#define SNDRV_FIREWIRE_EVENT_DICE_NOTIFICATION 0xd1ce004e
|
||||
|
||||
struct snd_firewire_event_common {
|
||||
unsigned int type; /* SNDRV_FIREWIRE_EVENT_xxx */
|
||||
};
|
||||
|
||||
struct snd_firewire_event_lock_status {
|
||||
unsigned int type;
|
||||
unsigned int status; /* 0/1 = unlocked/locked */
|
||||
};
|
||||
|
||||
struct snd_firewire_event_dice_notification {
|
||||
unsigned int type;
|
||||
unsigned int notification; /* DICE-specific bits */
|
||||
};
|
||||
|
||||
union snd_firewire_event {
|
||||
struct snd_firewire_event_common common;
|
||||
struct snd_firewire_event_lock_status lock_status;
|
||||
struct snd_firewire_event_dice_notification dice_notification;
|
||||
};
|
||||
|
||||
|
||||
#define SNDRV_FIREWIRE_IOCTL_GET_INFO _IOR('H', 0xf8, struct snd_firewire_get_info)
|
||||
#define SNDRV_FIREWIRE_IOCTL_LOCK _IO('H', 0xf9)
|
||||
#define SNDRV_FIREWIRE_IOCTL_UNLOCK _IO('H', 0xfa)
|
||||
|
||||
#define SNDRV_FIREWIRE_TYPE_DICE 1
|
||||
/* Fireworks, AV/C, RME, MOTU, ... */
|
||||
|
||||
struct snd_firewire_get_info {
|
||||
unsigned int type; /* SNDRV_FIREWIRE_TYPE_xxx */
|
||||
unsigned int card; /* same as fw_cdev_get_info.card */
|
||||
unsigned char guid[8];
|
||||
char device_name[16]; /* device node in /dev */
|
||||
};
|
||||
|
||||
/*
|
||||
* SNDRV_FIREWIRE_IOCTL_LOCK prevents the driver from streaming.
|
||||
* Returns -EBUSY if the driver is already streaming.
|
||||
*/
|
||||
|
||||
#endif
|
||||
|
|
@ -11,6 +11,21 @@ config SND_FIREWIRE_LIB
|
|||
tristate
|
||||
depends on SND_PCM
|
||||
|
||||
config SND_DICE
|
||||
tristate "DICE-based DACs (EXPERIMENTAL)"
|
||||
select SND_HWDEP
|
||||
select SND_PCM
|
||||
select SND_FIREWIRE_LIB
|
||||
help
|
||||
Say Y here to include support for many DACs based on the DICE
|
||||
chip family (DICE-II/Jr/Mini) from TC Applied Technologies.
|
||||
|
||||
At the moment, this driver supports playback only. If you
|
||||
want to use devices that support capturing, use FFADO instead.
|
||||
|
||||
To compile this driver as a module, choose M here: the module
|
||||
will be called snd-dice.
|
||||
|
||||
config SND_FIREWIRE_SPEAKERS
|
||||
tristate "FireWire speakers"
|
||||
select SND_PCM
|
||||
|
|
|
|||
|
|
@ -1,10 +1,12 @@
|
|||
snd-firewire-lib-objs := lib.o iso-resources.o packets-buffer.o \
|
||||
fcp.o cmp.o amdtp.o
|
||||
snd-dice-objs := dice.o
|
||||
snd-firewire-speakers-objs := speakers.o
|
||||
snd-isight-objs := isight.o
|
||||
snd-scs1x-objs := scs1x.o
|
||||
|
||||
obj-$(CONFIG_SND_FIREWIRE_LIB) += snd-firewire-lib.o
|
||||
obj-$(CONFIG_SND_DICE) += snd-dice.o
|
||||
obj-$(CONFIG_SND_FIREWIRE_SPEAKERS) += snd-firewire-speakers.o
|
||||
obj-$(CONFIG_SND_ISIGHT) += snd-isight.o
|
||||
obj-$(CONFIG_SND_SCS1X) += snd-scs1x.o
|
||||
|
|
|
|||
|
|
@ -42,9 +42,6 @@ static void pcm_period_tasklet(unsigned long data);
|
|||
int amdtp_out_stream_init(struct amdtp_out_stream *s, struct fw_unit *unit,
|
||||
enum cip_out_flags flags)
|
||||
{
|
||||
if (flags != CIP_NONBLOCKING)
|
||||
return -EINVAL;
|
||||
|
||||
s->unit = fw_unit_get(unit);
|
||||
s->flags = flags;
|
||||
s->context = ERR_PTR(-1);
|
||||
|
|
@ -62,73 +59,91 @@ EXPORT_SYMBOL(amdtp_out_stream_init);
|
|||
*/
|
||||
void amdtp_out_stream_destroy(struct amdtp_out_stream *s)
|
||||
{
|
||||
WARN_ON(!IS_ERR(s->context));
|
||||
WARN_ON(amdtp_out_stream_running(s));
|
||||
mutex_destroy(&s->mutex);
|
||||
fw_unit_put(s->unit);
|
||||
}
|
||||
EXPORT_SYMBOL(amdtp_out_stream_destroy);
|
||||
|
||||
const unsigned int amdtp_syt_intervals[CIP_SFC_COUNT] = {
|
||||
[CIP_SFC_32000] = 8,
|
||||
[CIP_SFC_44100] = 8,
|
||||
[CIP_SFC_48000] = 8,
|
||||
[CIP_SFC_88200] = 16,
|
||||
[CIP_SFC_96000] = 16,
|
||||
[CIP_SFC_176400] = 32,
|
||||
[CIP_SFC_192000] = 32,
|
||||
};
|
||||
EXPORT_SYMBOL(amdtp_syt_intervals);
|
||||
|
||||
/**
|
||||
* amdtp_out_stream_set_rate - set the sample rate
|
||||
* amdtp_out_stream_set_parameters - set stream parameters
|
||||
* @s: the AMDTP output stream to configure
|
||||
* @rate: the sample rate
|
||||
* @pcm_channels: the number of PCM samples in each data block, to be encoded
|
||||
* as AM824 multi-bit linear audio
|
||||
* @midi_ports: the number of MIDI ports (i.e., MPX-MIDI Data Channels)
|
||||
*
|
||||
* The sample rate must be set before the stream is started, and must not be
|
||||
* The parameters must be set before the stream is started, and must not be
|
||||
* changed while the stream is running.
|
||||
*/
|
||||
void amdtp_out_stream_set_rate(struct amdtp_out_stream *s, unsigned int rate)
|
||||
void amdtp_out_stream_set_parameters(struct amdtp_out_stream *s,
|
||||
unsigned int rate,
|
||||
unsigned int pcm_channels,
|
||||
unsigned int midi_ports)
|
||||
{
|
||||
static const struct {
|
||||
unsigned int rate;
|
||||
unsigned int syt_interval;
|
||||
} rate_info[] = {
|
||||
[CIP_SFC_32000] = { 32000, 8, },
|
||||
[CIP_SFC_44100] = { 44100, 8, },
|
||||
[CIP_SFC_48000] = { 48000, 8, },
|
||||
[CIP_SFC_88200] = { 88200, 16, },
|
||||
[CIP_SFC_96000] = { 96000, 16, },
|
||||
[CIP_SFC_176400] = { 176400, 32, },
|
||||
[CIP_SFC_192000] = { 192000, 32, },
|
||||
static const unsigned int rates[] = {
|
||||
[CIP_SFC_32000] = 32000,
|
||||
[CIP_SFC_44100] = 44100,
|
||||
[CIP_SFC_48000] = 48000,
|
||||
[CIP_SFC_88200] = 88200,
|
||||
[CIP_SFC_96000] = 96000,
|
||||
[CIP_SFC_176400] = 176400,
|
||||
[CIP_SFC_192000] = 192000,
|
||||
};
|
||||
unsigned int sfc;
|
||||
|
||||
if (WARN_ON(!IS_ERR(s->context)))
|
||||
if (WARN_ON(amdtp_out_stream_running(s)))
|
||||
return;
|
||||
|
||||
for (sfc = 0; sfc < ARRAY_SIZE(rate_info); ++sfc)
|
||||
if (rate_info[sfc].rate == rate) {
|
||||
s->sfc = sfc;
|
||||
s->syt_interval = rate_info[sfc].syt_interval;
|
||||
return;
|
||||
}
|
||||
for (sfc = 0; sfc < CIP_SFC_COUNT; ++sfc)
|
||||
if (rates[sfc] == rate)
|
||||
goto sfc_found;
|
||||
WARN_ON(1);
|
||||
return;
|
||||
|
||||
sfc_found:
|
||||
s->dual_wire = (s->flags & CIP_HI_DUALWIRE) && sfc > CIP_SFC_96000;
|
||||
if (s->dual_wire) {
|
||||
sfc -= 2;
|
||||
rate /= 2;
|
||||
pcm_channels *= 2;
|
||||
}
|
||||
s->sfc = sfc;
|
||||
s->data_block_quadlets = pcm_channels + DIV_ROUND_UP(midi_ports, 8);
|
||||
s->pcm_channels = pcm_channels;
|
||||
s->midi_ports = midi_ports;
|
||||
|
||||
s->syt_interval = amdtp_syt_intervals[sfc];
|
||||
|
||||
/* default buffering in the device */
|
||||
s->transfer_delay = TRANSFER_DELAY_TICKS - TICKS_PER_CYCLE;
|
||||
if (s->flags & CIP_BLOCKING)
|
||||
/* additional buffering needed to adjust for no-data packets */
|
||||
s->transfer_delay += TICKS_PER_SECOND * s->syt_interval / rate;
|
||||
}
|
||||
EXPORT_SYMBOL(amdtp_out_stream_set_rate);
|
||||
EXPORT_SYMBOL(amdtp_out_stream_set_parameters);
|
||||
|
||||
/**
|
||||
* amdtp_out_stream_get_max_payload - get the stream's packet size
|
||||
* @s: the AMDTP output stream
|
||||
*
|
||||
* This function must not be called before the stream has been configured
|
||||
* with amdtp_out_stream_set_hw_params(), amdtp_out_stream_set_pcm(), and
|
||||
* amdtp_out_stream_set_midi().
|
||||
* with amdtp_out_stream_set_parameters().
|
||||
*/
|
||||
unsigned int amdtp_out_stream_get_max_payload(struct amdtp_out_stream *s)
|
||||
{
|
||||
static const unsigned int max_data_blocks[] = {
|
||||
[CIP_SFC_32000] = 4,
|
||||
[CIP_SFC_44100] = 6,
|
||||
[CIP_SFC_48000] = 6,
|
||||
[CIP_SFC_88200] = 12,
|
||||
[CIP_SFC_96000] = 12,
|
||||
[CIP_SFC_176400] = 23,
|
||||
[CIP_SFC_192000] = 24,
|
||||
};
|
||||
|
||||
s->data_block_quadlets = s->pcm_channels;
|
||||
s->data_block_quadlets += DIV_ROUND_UP(s->midi_ports, 8);
|
||||
|
||||
return 8 + max_data_blocks[s->sfc] * 4 * s->data_block_quadlets;
|
||||
return 8 + s->syt_interval * s->data_block_quadlets * 4;
|
||||
}
|
||||
EXPORT_SYMBOL(amdtp_out_stream_get_max_payload);
|
||||
|
||||
|
|
@ -138,19 +153,26 @@ static void amdtp_write_s16(struct amdtp_out_stream *s,
|
|||
static void amdtp_write_s32(struct amdtp_out_stream *s,
|
||||
struct snd_pcm_substream *pcm,
|
||||
__be32 *buffer, unsigned int frames);
|
||||
static void amdtp_write_s16_dualwire(struct amdtp_out_stream *s,
|
||||
struct snd_pcm_substream *pcm,
|
||||
__be32 *buffer, unsigned int frames);
|
||||
static void amdtp_write_s32_dualwire(struct amdtp_out_stream *s,
|
||||
struct snd_pcm_substream *pcm,
|
||||
__be32 *buffer, unsigned int frames);
|
||||
|
||||
/**
|
||||
* amdtp_out_stream_set_pcm_format - set the PCM format
|
||||
* @s: the AMDTP output stream to configure
|
||||
* @format: the format of the ALSA PCM device
|
||||
*
|
||||
* The sample format must be set before the stream is started, and must not be
|
||||
* changed while the stream is running.
|
||||
* The sample format must be set after the other paramters (rate/PCM channels/
|
||||
* MIDI) and before the stream is started, and must not be changed while the
|
||||
* stream is running.
|
||||
*/
|
||||
void amdtp_out_stream_set_pcm_format(struct amdtp_out_stream *s,
|
||||
snd_pcm_format_t format)
|
||||
{
|
||||
if (WARN_ON(!IS_ERR(s->context)))
|
||||
if (WARN_ON(amdtp_out_stream_running(s)))
|
||||
return;
|
||||
|
||||
switch (format) {
|
||||
|
|
@ -158,10 +180,16 @@ void amdtp_out_stream_set_pcm_format(struct amdtp_out_stream *s,
|
|||
WARN_ON(1);
|
||||
/* fall through */
|
||||
case SNDRV_PCM_FORMAT_S16:
|
||||
s->transfer_samples = amdtp_write_s16;
|
||||
if (s->dual_wire)
|
||||
s->transfer_samples = amdtp_write_s16_dualwire;
|
||||
else
|
||||
s->transfer_samples = amdtp_write_s16;
|
||||
break;
|
||||
case SNDRV_PCM_FORMAT_S32:
|
||||
s->transfer_samples = amdtp_write_s32;
|
||||
if (s->dual_wire)
|
||||
s->transfer_samples = amdtp_write_s32_dualwire;
|
||||
else
|
||||
s->transfer_samples = amdtp_write_s32;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
|
@ -248,7 +276,7 @@ static unsigned int calculate_syt(struct amdtp_out_stream *s,
|
|||
s->last_syt_offset = syt_offset;
|
||||
|
||||
if (syt_offset < TICKS_PER_CYCLE) {
|
||||
syt_offset += TRANSFER_DELAY_TICKS - TICKS_PER_CYCLE;
|
||||
syt_offset += s->transfer_delay;
|
||||
syt = (cycle + syt_offset / TICKS_PER_CYCLE) << 12;
|
||||
syt += syt_offset % TICKS_PER_CYCLE;
|
||||
|
||||
|
|
@ -310,6 +338,68 @@ static void amdtp_write_s16(struct amdtp_out_stream *s,
|
|||
}
|
||||
}
|
||||
|
||||
static void amdtp_write_s32_dualwire(struct amdtp_out_stream *s,
|
||||
struct snd_pcm_substream *pcm,
|
||||
__be32 *buffer, unsigned int frames)
|
||||
{
|
||||
struct snd_pcm_runtime *runtime = pcm->runtime;
|
||||
unsigned int channels, frame_adjust_1, frame_adjust_2, i, c;
|
||||
const u32 *src;
|
||||
|
||||
channels = s->pcm_channels;
|
||||
src = (void *)runtime->dma_area +
|
||||
s->pcm_buffer_pointer * (runtime->frame_bits / 8);
|
||||
frame_adjust_1 = channels - 1;
|
||||
frame_adjust_2 = 1 - (s->data_block_quadlets - channels);
|
||||
|
||||
channels /= 2;
|
||||
for (i = 0; i < frames; ++i) {
|
||||
for (c = 0; c < channels; ++c) {
|
||||
*buffer = cpu_to_be32((*src >> 8) | 0x40000000);
|
||||
src++;
|
||||
buffer += 2;
|
||||
}
|
||||
buffer -= frame_adjust_1;
|
||||
for (c = 0; c < channels; ++c) {
|
||||
*buffer = cpu_to_be32((*src >> 8) | 0x40000000);
|
||||
src++;
|
||||
buffer += 2;
|
||||
}
|
||||
buffer -= frame_adjust_2;
|
||||
}
|
||||
}
|
||||
|
||||
static void amdtp_write_s16_dualwire(struct amdtp_out_stream *s,
|
||||
struct snd_pcm_substream *pcm,
|
||||
__be32 *buffer, unsigned int frames)
|
||||
{
|
||||
struct snd_pcm_runtime *runtime = pcm->runtime;
|
||||
unsigned int channels, frame_adjust_1, frame_adjust_2, i, c;
|
||||
const u16 *src;
|
||||
|
||||
channels = s->pcm_channels;
|
||||
src = (void *)runtime->dma_area +
|
||||
s->pcm_buffer_pointer * (runtime->frame_bits / 8);
|
||||
frame_adjust_1 = channels - 1;
|
||||
frame_adjust_2 = 1 - (s->data_block_quadlets - channels);
|
||||
|
||||
channels /= 2;
|
||||
for (i = 0; i < frames; ++i) {
|
||||
for (c = 0; c < channels; ++c) {
|
||||
*buffer = cpu_to_be32((*src << 8) | 0x40000000);
|
||||
src++;
|
||||
buffer += 2;
|
||||
}
|
||||
buffer -= frame_adjust_1;
|
||||
for (c = 0; c < channels; ++c) {
|
||||
*buffer = cpu_to_be32((*src << 8) | 0x40000000);
|
||||
src++;
|
||||
buffer += 2;
|
||||
}
|
||||
buffer -= frame_adjust_2;
|
||||
}
|
||||
}
|
||||
|
||||
static void amdtp_fill_pcm_silence(struct amdtp_out_stream *s,
|
||||
__be32 *buffer, unsigned int frames)
|
||||
{
|
||||
|
|
@ -344,8 +434,17 @@ static void queue_out_packet(struct amdtp_out_stream *s, unsigned int cycle)
|
|||
return;
|
||||
index = s->packet_index;
|
||||
|
||||
data_blocks = calculate_data_blocks(s);
|
||||
syt = calculate_syt(s, cycle);
|
||||
if (!(s->flags & CIP_BLOCKING)) {
|
||||
data_blocks = calculate_data_blocks(s);
|
||||
} else {
|
||||
if (syt != 0xffff) {
|
||||
data_blocks = s->syt_interval;
|
||||
} else {
|
||||
data_blocks = 0;
|
||||
syt = 0xffffff;
|
||||
}
|
||||
}
|
||||
|
||||
buffer = s->buffer.packets[index].buffer;
|
||||
buffer[0] = cpu_to_be32(ACCESS_ONCE(s->source_node_id_field) |
|
||||
|
|
@ -386,6 +485,9 @@ static void queue_out_packet(struct amdtp_out_stream *s, unsigned int cycle)
|
|||
s->packet_index = index;
|
||||
|
||||
if (pcm) {
|
||||
if (s->dual_wire)
|
||||
data_blocks *= 2;
|
||||
|
||||
ptr = s->pcm_buffer_pointer + data_blocks;
|
||||
if (ptr >= pcm->runtime->buffer_size)
|
||||
ptr -= pcm->runtime->buffer_size;
|
||||
|
|
@ -455,9 +557,8 @@ static int queue_initial_skip_packets(struct amdtp_out_stream *s)
|
|||
* @speed: firewire speed code
|
||||
*
|
||||
* The stream cannot be started until it has been configured with
|
||||
* amdtp_out_stream_set_hw_params(), amdtp_out_stream_set_pcm(), and
|
||||
* amdtp_out_stream_set_midi(); and it must be started before any
|
||||
* PCM or MIDI device can be started.
|
||||
* amdtp_out_stream_set_parameters() and amdtp_out_stream_set_pcm_format(),
|
||||
* and it must be started before any PCM or MIDI device can be started.
|
||||
*/
|
||||
int amdtp_out_stream_start(struct amdtp_out_stream *s, int channel, int speed)
|
||||
{
|
||||
|
|
@ -477,7 +578,7 @@ int amdtp_out_stream_start(struct amdtp_out_stream *s, int channel, int speed)
|
|||
|
||||
mutex_lock(&s->mutex);
|
||||
|
||||
if (WARN_ON(!IS_ERR(s->context) ||
|
||||
if (WARN_ON(amdtp_out_stream_running(s) ||
|
||||
(!s->pcm_channels && !s->midi_ports))) {
|
||||
err = -EBADFD;
|
||||
goto err_unlock;
|
||||
|
|
@ -573,7 +674,7 @@ void amdtp_out_stream_stop(struct amdtp_out_stream *s)
|
|||
{
|
||||
mutex_lock(&s->mutex);
|
||||
|
||||
if (IS_ERR(s->context)) {
|
||||
if (!amdtp_out_stream_running(s)) {
|
||||
mutex_unlock(&s->mutex);
|
||||
return;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,6 +1,7 @@
|
|||
#ifndef SOUND_FIREWIRE_AMDTP_H_INCLUDED
|
||||
#define SOUND_FIREWIRE_AMDTP_H_INCLUDED
|
||||
|
||||
#include <linux/err.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/mutex.h>
|
||||
#include "packets-buffer.h"
|
||||
|
|
@ -11,9 +12,18 @@
|
|||
* sample_rate/8000 samples, with rounding up or down to adjust
|
||||
* for clock skew and left-over fractional samples. This should
|
||||
* be used if supported by the device.
|
||||
* @CIP_BLOCKING: In blocking mode, each packet contains either zero or
|
||||
* SYT_INTERVAL samples, with these two types alternating so that
|
||||
* the overall sample rate comes out right.
|
||||
* @CIP_HI_DUALWIRE: At rates above 96 kHz, pretend that the stream runs
|
||||
* at half the actual sample rate with twice the number of channels;
|
||||
* two samples of a channel are stored consecutively in the packet.
|
||||
* Requires blocking mode and SYT_INTERVAL-aligned PCM buffer size.
|
||||
*/
|
||||
enum cip_out_flags {
|
||||
CIP_NONBLOCKING = 0,
|
||||
CIP_NONBLOCKING = 0x00,
|
||||
CIP_BLOCKING = 0x01,
|
||||
CIP_HI_DUALWIRE = 0x02,
|
||||
};
|
||||
|
||||
/**
|
||||
|
|
@ -27,6 +37,7 @@ enum cip_sfc {
|
|||
CIP_SFC_96000 = 4,
|
||||
CIP_SFC_176400 = 5,
|
||||
CIP_SFC_192000 = 6,
|
||||
CIP_SFC_COUNT
|
||||
};
|
||||
|
||||
#define AMDTP_OUT_PCM_FORMAT_BITS (SNDRV_PCM_FMTBIT_S16 | \
|
||||
|
|
@ -43,6 +54,7 @@ struct amdtp_out_stream {
|
|||
struct mutex mutex;
|
||||
|
||||
enum cip_sfc sfc;
|
||||
bool dual_wire;
|
||||
unsigned int data_block_quadlets;
|
||||
unsigned int pcm_channels;
|
||||
unsigned int midi_ports;
|
||||
|
|
@ -51,6 +63,7 @@ struct amdtp_out_stream {
|
|||
__be32 *buffer, unsigned int frames);
|
||||
|
||||
unsigned int syt_interval;
|
||||
unsigned int transfer_delay;
|
||||
unsigned int source_node_id_field;
|
||||
struct iso_packets_buffer buffer;
|
||||
|
||||
|
|
@ -74,7 +87,10 @@ int amdtp_out_stream_init(struct amdtp_out_stream *s, struct fw_unit *unit,
|
|||
enum cip_out_flags flags);
|
||||
void amdtp_out_stream_destroy(struct amdtp_out_stream *s);
|
||||
|
||||
void amdtp_out_stream_set_rate(struct amdtp_out_stream *s, unsigned int rate);
|
||||
void amdtp_out_stream_set_parameters(struct amdtp_out_stream *s,
|
||||
unsigned int rate,
|
||||
unsigned int pcm_channels,
|
||||
unsigned int midi_ports);
|
||||
unsigned int amdtp_out_stream_get_max_payload(struct amdtp_out_stream *s);
|
||||
|
||||
int amdtp_out_stream_start(struct amdtp_out_stream *s, int channel, int speed);
|
||||
|
|
@ -87,31 +103,11 @@ void amdtp_out_stream_pcm_prepare(struct amdtp_out_stream *s);
|
|||
unsigned long amdtp_out_stream_pcm_pointer(struct amdtp_out_stream *s);
|
||||
void amdtp_out_stream_pcm_abort(struct amdtp_out_stream *s);
|
||||
|
||||
/**
|
||||
* amdtp_out_stream_set_pcm - configure format of PCM samples
|
||||
* @s: the AMDTP output stream to be configured
|
||||
* @pcm_channels: the number of PCM samples in each data block, to be encoded
|
||||
* as AM824 multi-bit linear audio
|
||||
*
|
||||
* This function must not be called while the stream is running.
|
||||
*/
|
||||
static inline void amdtp_out_stream_set_pcm(struct amdtp_out_stream *s,
|
||||
unsigned int pcm_channels)
|
||||
{
|
||||
s->pcm_channels = pcm_channels;
|
||||
}
|
||||
extern const unsigned int amdtp_syt_intervals[CIP_SFC_COUNT];
|
||||
|
||||
/**
|
||||
* amdtp_out_stream_set_midi - configure format of MIDI data
|
||||
* @s: the AMDTP output stream to be configured
|
||||
* @midi_ports: the number of MIDI ports (i.e., MPX-MIDI Data Channels)
|
||||
*
|
||||
* This function must not be called while the stream is running.
|
||||
*/
|
||||
static inline void amdtp_out_stream_set_midi(struct amdtp_out_stream *s,
|
||||
unsigned int midi_ports)
|
||||
static inline bool amdtp_out_stream_running(struct amdtp_out_stream *s)
|
||||
{
|
||||
s->midi_ports = midi_ports;
|
||||
return !IS_ERR(s->context);
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
|
|||
|
|
@ -48,9 +48,6 @@ static int pcr_modify(struct cmp_connection *c,
|
|||
int (*check)(struct cmp_connection *c, __be32 pcr),
|
||||
enum bus_reset_handling bus_reset_handling)
|
||||
{
|
||||
struct fw_device *device = fw_parent_device(c->resources.unit);
|
||||
int generation = c->resources.generation;
|
||||
int rcode, errors = 0;
|
||||
__be32 old_arg, buffer[2];
|
||||
int err;
|
||||
|
||||
|
|
@ -59,36 +56,31 @@ static int pcr_modify(struct cmp_connection *c,
|
|||
old_arg = buffer[0];
|
||||
buffer[1] = modify(c, buffer[0]);
|
||||
|
||||
rcode = fw_run_transaction(
|
||||
device->card, TCODE_LOCK_COMPARE_SWAP,
|
||||
device->node_id, generation, device->max_speed,
|
||||
err = snd_fw_transaction(
|
||||
c->resources.unit, TCODE_LOCK_COMPARE_SWAP,
|
||||
CSR_REGISTER_BASE + CSR_IPCR(c->pcr_index),
|
||||
buffer, 8);
|
||||
buffer, 8,
|
||||
FW_FIXED_GENERATION | c->resources.generation);
|
||||
|
||||
if (rcode == RCODE_COMPLETE) {
|
||||
if (buffer[0] == old_arg) /* success? */
|
||||
break;
|
||||
if (err < 0) {
|
||||
if (err == -EAGAIN &&
|
||||
bus_reset_handling == SUCCEED_ON_BUS_RESET)
|
||||
err = 0;
|
||||
return err;
|
||||
}
|
||||
|
||||
if (check) {
|
||||
err = check(c, buffer[0]);
|
||||
if (err < 0)
|
||||
return err;
|
||||
}
|
||||
} else if (rcode == RCODE_GENERATION)
|
||||
goto bus_reset;
|
||||
else if (rcode_is_permanent_error(rcode) || ++errors >= 3)
|
||||
goto io_error;
|
||||
if (buffer[0] == old_arg) /* success? */
|
||||
break;
|
||||
|
||||
if (check) {
|
||||
err = check(c, buffer[0]);
|
||||
if (err < 0)
|
||||
return err;
|
||||
}
|
||||
}
|
||||
c->last_pcr_value = buffer[1];
|
||||
|
||||
return 0;
|
||||
|
||||
io_error:
|
||||
cmp_error(c, "transaction failed: %s\n", fw_rcode_string(rcode));
|
||||
return -EIO;
|
||||
|
||||
bus_reset:
|
||||
return bus_reset_handling == ABORT_ON_BUS_RESET ? -EAGAIN : 0;
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -108,7 +100,7 @@ int cmp_connection_init(struct cmp_connection *c,
|
|||
|
||||
err = snd_fw_transaction(unit, TCODE_READ_QUADLET_REQUEST,
|
||||
CSR_REGISTER_BASE + CSR_IMPR,
|
||||
&impr_be, 4);
|
||||
&impr_be, 4, 0);
|
||||
if (err < 0)
|
||||
return err;
|
||||
impr = be32_to_cpu(impr_be);
|
||||
|
|
|
|||
|
|
@ -0,0 +1,371 @@
|
|||
#ifndef SOUND_FIREWIRE_DICE_INTERFACE_H_INCLUDED
|
||||
#define SOUND_FIREWIRE_DICE_INTERFACE_H_INCLUDED
|
||||
|
||||
/*
|
||||
* DICE device interface definitions
|
||||
*/
|
||||
|
||||
/*
|
||||
* Generally, all registers can be read like memory, i.e., with quadlet read or
|
||||
* block read transactions with at least quadlet-aligned offset and length.
|
||||
* Writes are not allowed except where noted; quadlet-sized registers must be
|
||||
* written with a quadlet write transaction.
|
||||
*
|
||||
* All values are in big endian. The DICE firmware runs on a little-endian CPU
|
||||
* and just byte-swaps _all_ quadlets on the bus, so values without endianness
|
||||
* (e.g. strings) get scrambled and must be byte-swapped again by the driver.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Streaming is handled by the "DICE driver" interface. Its registers are
|
||||
* located in this private address space.
|
||||
*/
|
||||
#define DICE_PRIVATE_SPACE 0xffffe0000000uLL
|
||||
|
||||
/*
|
||||
* The registers are organized in several sections, which are organized
|
||||
* separately to allow them to be extended individually. Whether a register is
|
||||
* supported can be detected by checking its offset against its section's size.
|
||||
*
|
||||
* The section offset values are relative to DICE_PRIVATE_SPACE; the offset/
|
||||
* size values are measured in quadlets. Read-only.
|
||||
*/
|
||||
#define DICE_GLOBAL_OFFSET 0x00
|
||||
#define DICE_GLOBAL_SIZE 0x04
|
||||
#define DICE_TX_OFFSET 0x08
|
||||
#define DICE_TX_SIZE 0x0c
|
||||
#define DICE_RX_OFFSET 0x10
|
||||
#define DICE_RX_SIZE 0x14
|
||||
#define DICE_EXT_SYNC_OFFSET 0x18
|
||||
#define DICE_EXT_SYNC_SIZE 0x1c
|
||||
#define DICE_UNUSED2_OFFSET 0x20
|
||||
#define DICE_UNUSED2_SIZE 0x24
|
||||
|
||||
/*
|
||||
* Global settings.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Stores the full 64-bit address (node ID and offset in the node's address
|
||||
* space) where the device will send notifications. Must be changed with
|
||||
* a compare/swap transaction by the owner. This register is automatically
|
||||
* cleared on a bus reset.
|
||||
*/
|
||||
#define GLOBAL_OWNER 0x000
|
||||
#define OWNER_NO_OWNER 0xffff000000000000uLL
|
||||
#define OWNER_NODE_SHIFT 48
|
||||
|
||||
/*
|
||||
* A bitmask with asynchronous events; read-only. When any event(s) happen,
|
||||
* the bits of previous events are cleared, and the value of this register is
|
||||
* also written to the address stored in the owner register.
|
||||
*/
|
||||
#define GLOBAL_NOTIFICATION 0x008
|
||||
/* Some registers in the Rx/Tx sections may have changed. */
|
||||
#define NOTIFY_RX_CFG_CHG 0x00000001
|
||||
#define NOTIFY_TX_CFG_CHG 0x00000002
|
||||
/* Lock status of the current clock source may have changed. */
|
||||
#define NOTIFY_LOCK_CHG 0x00000010
|
||||
/* Write to the clock select register has been finished. */
|
||||
#define NOTIFY_CLOCK_ACCEPTED 0x00000020
|
||||
/* Lock status of some clock source has changed. */
|
||||
#define NOTIFY_EXT_STATUS 0x00000040
|
||||
/* Other bits may be used for device-specific events. */
|
||||
|
||||
/*
|
||||
* A name that can be customized for each device; read/write. Padded with zero
|
||||
* bytes. Quadlets are byte-swapped. The encoding is whatever the host driver
|
||||
* happens to be using.
|
||||
*/
|
||||
#define GLOBAL_NICK_NAME 0x00c
|
||||
#define NICK_NAME_SIZE 64
|
||||
|
||||
/*
|
||||
* The current sample rate and clock source; read/write. Whether a clock
|
||||
* source or sample rate is supported is device-specific; the internal clock
|
||||
* source is always available. Low/mid/high = up to 48/96/192 kHz. This
|
||||
* register can be changed even while streams are running.
|
||||
*/
|
||||
#define GLOBAL_CLOCK_SELECT 0x04c
|
||||
#define CLOCK_SOURCE_MASK 0x000000ff
|
||||
#define CLOCK_SOURCE_AES1 0x00000000
|
||||
#define CLOCK_SOURCE_AES2 0x00000001
|
||||
#define CLOCK_SOURCE_AES3 0x00000002
|
||||
#define CLOCK_SOURCE_AES4 0x00000003
|
||||
#define CLOCK_SOURCE_AES_ANY 0x00000004
|
||||
#define CLOCK_SOURCE_ADAT 0x00000005
|
||||
#define CLOCK_SOURCE_TDIF 0x00000006
|
||||
#define CLOCK_SOURCE_WC 0x00000007
|
||||
#define CLOCK_SOURCE_ARX1 0x00000008
|
||||
#define CLOCK_SOURCE_ARX2 0x00000009
|
||||
#define CLOCK_SOURCE_ARX3 0x0000000a
|
||||
#define CLOCK_SOURCE_ARX4 0x0000000b
|
||||
#define CLOCK_SOURCE_INTERNAL 0x0000000c
|
||||
#define CLOCK_RATE_MASK 0x0000ff00
|
||||
#define CLOCK_RATE_32000 0x00000000
|
||||
#define CLOCK_RATE_44100 0x00000100
|
||||
#define CLOCK_RATE_48000 0x00000200
|
||||
#define CLOCK_RATE_88200 0x00000300
|
||||
#define CLOCK_RATE_96000 0x00000400
|
||||
#define CLOCK_RATE_176400 0x00000500
|
||||
#define CLOCK_RATE_192000 0x00000600
|
||||
#define CLOCK_RATE_ANY_LOW 0x00000700
|
||||
#define CLOCK_RATE_ANY_MID 0x00000800
|
||||
#define CLOCK_RATE_ANY_HIGH 0x00000900
|
||||
#define CLOCK_RATE_NONE 0x00000a00
|
||||
#define CLOCK_RATE_SHIFT 8
|
||||
|
||||
/*
|
||||
* Enable streaming; read/write. Writing a non-zero value (re)starts all
|
||||
* streams that have a valid iso channel set; zero stops all streams. The
|
||||
* streams' parameters must be configured before starting. This register is
|
||||
* automatically cleared on a bus reset.
|
||||
*/
|
||||
#define GLOBAL_ENABLE 0x050
|
||||
|
||||
/*
|
||||
* Status of the sample clock; read-only.
|
||||
*/
|
||||
#define GLOBAL_STATUS 0x054
|
||||
/* The current clock source is locked. */
|
||||
#define STATUS_SOURCE_LOCKED 0x00000001
|
||||
/* The actual sample rate; CLOCK_RATE_32000-_192000 or _NONE. */
|
||||
#define STATUS_NOMINAL_RATE_MASK 0x0000ff00
|
||||
|
||||
/*
|
||||
* Status of all clock sources; read-only.
|
||||
*/
|
||||
#define GLOBAL_EXTENDED_STATUS 0x058
|
||||
/*
|
||||
* The _LOCKED bits always show the current status; any change generates
|
||||
* a notification.
|
||||
*/
|
||||
#define EXT_STATUS_AES1_LOCKED 0x00000001
|
||||
#define EXT_STATUS_AES2_LOCKED 0x00000002
|
||||
#define EXT_STATUS_AES3_LOCKED 0x00000004
|
||||
#define EXT_STATUS_AES4_LOCKED 0x00000008
|
||||
#define EXT_STATUS_ADAT_LOCKED 0x00000010
|
||||
#define EXT_STATUS_TDIF_LOCKED 0x00000020
|
||||
#define EXT_STATUS_ARX1_LOCKED 0x00000040
|
||||
#define EXT_STATUS_ARX2_LOCKED 0x00000080
|
||||
#define EXT_STATUS_ARX3_LOCKED 0x00000100
|
||||
#define EXT_STATUS_ARX4_LOCKED 0x00000200
|
||||
#define EXT_STATUS_WC_LOCKED 0x00000400
|
||||
/*
|
||||
* The _SLIP bits do not generate notifications; a set bit indicates that an
|
||||
* error occurred since the last time when this register was read with
|
||||
* a quadlet read transaction.
|
||||
*/
|
||||
#define EXT_STATUS_AES1_SLIP 0x00010000
|
||||
#define EXT_STATUS_AES2_SLIP 0x00020000
|
||||
#define EXT_STATUS_AES3_SLIP 0x00040000
|
||||
#define EXT_STATUS_AES4_SLIP 0x00080000
|
||||
#define EXT_STATUS_ADAT_SLIP 0x00100000
|
||||
#define EXT_STATUS_TDIF_SLIP 0x00200000
|
||||
#define EXT_STATUS_ARX1_SLIP 0x00400000
|
||||
#define EXT_STATUS_ARX2_SLIP 0x00800000
|
||||
#define EXT_STATUS_ARX3_SLIP 0x01000000
|
||||
#define EXT_STATUS_ARX4_SLIP 0x02000000
|
||||
#define EXT_STATUS_WC_SLIP 0x04000000
|
||||
|
||||
/*
|
||||
* The measured rate of the current clock source, in Hz; read-only.
|
||||
*/
|
||||
#define GLOBAL_SAMPLE_RATE 0x05c
|
||||
|
||||
/*
|
||||
* The version of the DICE driver specification that this device conforms to;
|
||||
* read-only.
|
||||
*/
|
||||
#define GLOBAL_VERSION 0x060
|
||||
|
||||
/* Some old firmware versions do not have the following global registers: */
|
||||
|
||||
/*
|
||||
* Supported sample rates and clock sources; read-only.
|
||||
*/
|
||||
#define GLOBAL_CLOCK_CAPABILITIES 0x064
|
||||
#define CLOCK_CAP_RATE_32000 0x00000001
|
||||
#define CLOCK_CAP_RATE_44100 0x00000002
|
||||
#define CLOCK_CAP_RATE_48000 0x00000004
|
||||
#define CLOCK_CAP_RATE_88200 0x00000008
|
||||
#define CLOCK_CAP_RATE_96000 0x00000010
|
||||
#define CLOCK_CAP_RATE_176400 0x00000020
|
||||
#define CLOCK_CAP_RATE_192000 0x00000040
|
||||
#define CLOCK_CAP_SOURCE_AES1 0x00010000
|
||||
#define CLOCK_CAP_SOURCE_AES2 0x00020000
|
||||
#define CLOCK_CAP_SOURCE_AES3 0x00040000
|
||||
#define CLOCK_CAP_SOURCE_AES4 0x00080000
|
||||
#define CLOCK_CAP_SOURCE_AES_ANY 0x00100000
|
||||
#define CLOCK_CAP_SOURCE_ADAT 0x00200000
|
||||
#define CLOCK_CAP_SOURCE_TDIF 0x00400000
|
||||
#define CLOCK_CAP_SOURCE_WC 0x00800000
|
||||
#define CLOCK_CAP_SOURCE_ARX1 0x01000000
|
||||
#define CLOCK_CAP_SOURCE_ARX2 0x02000000
|
||||
#define CLOCK_CAP_SOURCE_ARX3 0x04000000
|
||||
#define CLOCK_CAP_SOURCE_ARX4 0x08000000
|
||||
#define CLOCK_CAP_SOURCE_INTERNAL 0x10000000
|
||||
|
||||
/*
|
||||
* Names of all clock sources; read-only. Quadlets are byte-swapped. Names
|
||||
* are separated with one backslash, the list is terminated with two
|
||||
* backslashes. Unused clock sources are included.
|
||||
*/
|
||||
#define GLOBAL_CLOCK_SOURCE_NAMES 0x068
|
||||
#define CLOCK_SOURCE_NAMES_SIZE 256
|
||||
|
||||
/*
|
||||
* Capture stream settings. This section includes the number/size registers
|
||||
* and the registers of all streams.
|
||||
*/
|
||||
|
||||
/*
|
||||
* The number of supported capture streams; read-only.
|
||||
*/
|
||||
#define TX_NUMBER 0x000
|
||||
|
||||
/*
|
||||
* The size of one stream's register block, in quadlets; read-only. The
|
||||
* registers of the first stream follow immediately afterwards; the registers
|
||||
* of the following streams are offset by this register's value.
|
||||
*/
|
||||
#define TX_SIZE 0x004
|
||||
|
||||
/*
|
||||
* The isochronous channel number on which packets are sent, or -1 if the
|
||||
* stream is not to be used; read/write.
|
||||
*/
|
||||
#define TX_ISOCHRONOUS 0x008
|
||||
|
||||
/*
|
||||
* The number of audio channels; read-only. There will be one quadlet per
|
||||
* channel; the first channel is the first quadlet in a data block.
|
||||
*/
|
||||
#define TX_NUMBER_AUDIO 0x00c
|
||||
|
||||
/*
|
||||
* The number of MIDI ports, 0-8; read-only. If > 0, there will be one
|
||||
* additional quadlet in each data block, following the audio quadlets.
|
||||
*/
|
||||
#define TX_NUMBER_MIDI 0x010
|
||||
|
||||
/*
|
||||
* The speed at which the packets are sent, SCODE_100-_400; read/write.
|
||||
*/
|
||||
#define TX_SPEED 0x014
|
||||
|
||||
/*
|
||||
* Names of all audio channels; read-only. Quadlets are byte-swapped. Names
|
||||
* are separated with one backslash, the list is terminated with two
|
||||
* backslashes.
|
||||
*/
|
||||
#define TX_NAMES 0x018
|
||||
#define TX_NAMES_SIZE 256
|
||||
|
||||
/*
|
||||
* Audio IEC60958 capabilities; read-only. Bitmask with one bit per audio
|
||||
* channel.
|
||||
*/
|
||||
#define TX_AC3_CAPABILITIES 0x118
|
||||
|
||||
/*
|
||||
* Send audio data with IEC60958 label; read/write. Bitmask with one bit per
|
||||
* audio channel. This register can be changed even while the stream is
|
||||
* running.
|
||||
*/
|
||||
#define TX_AC3_ENABLE 0x11c
|
||||
|
||||
/*
|
||||
* Playback stream settings. This section includes the number/size registers
|
||||
* and the registers of all streams.
|
||||
*/
|
||||
|
||||
/*
|
||||
* The number of supported playback streams; read-only.
|
||||
*/
|
||||
#define RX_NUMBER 0x000
|
||||
|
||||
/*
|
||||
* The size of one stream's register block, in quadlets; read-only. The
|
||||
* registers of the first stream follow immediately afterwards; the registers
|
||||
* of the following streams are offset by this register's value.
|
||||
*/
|
||||
#define RX_SIZE 0x004
|
||||
|
||||
/*
|
||||
* The isochronous channel number on which packets are received, or -1 if the
|
||||
* stream is not to be used; read/write.
|
||||
*/
|
||||
#define RX_ISOCHRONOUS 0x008
|
||||
|
||||
/*
|
||||
* Index of first quadlet to be interpreted; read/write. If > 0, that many
|
||||
* quadlets at the beginning of each data block will be ignored, and all the
|
||||
* audio and MIDI quadlets will follow.
|
||||
*/
|
||||
#define RX_SEQ_START 0x00c
|
||||
|
||||
/*
|
||||
* The number of audio channels; read-only. There will be one quadlet per
|
||||
* channel.
|
||||
*/
|
||||
#define RX_NUMBER_AUDIO 0x010
|
||||
|
||||
/*
|
||||
* The number of MIDI ports, 0-8; read-only. If > 0, there will be one
|
||||
* additional quadlet in each data block, following the audio quadlets.
|
||||
*/
|
||||
#define RX_NUMBER_MIDI 0x014
|
||||
|
||||
/*
|
||||
* Names of all audio channels; read-only. Quadlets are byte-swapped. Names
|
||||
* are separated with one backslash, the list is terminated with two
|
||||
* backslashes.
|
||||
*/
|
||||
#define RX_NAMES 0x018
|
||||
#define RX_NAMES_SIZE 256
|
||||
|
||||
/*
|
||||
* Audio IEC60958 capabilities; read-only. Bitmask with one bit per audio
|
||||
* channel.
|
||||
*/
|
||||
#define RX_AC3_CAPABILITIES 0x118
|
||||
|
||||
/*
|
||||
* Receive audio data with IEC60958 label; read/write. Bitmask with one bit
|
||||
* per audio channel. This register can be changed even while the stream is
|
||||
* running.
|
||||
*/
|
||||
#define RX_AC3_ENABLE 0x11c
|
||||
|
||||
/*
|
||||
* Extended synchronization information.
|
||||
* This section can be read completely with a block read request.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Current clock source; read-only.
|
||||
*/
|
||||
#define EXT_SYNC_CLOCK_SOURCE 0x000
|
||||
|
||||
/*
|
||||
* Clock source is locked (boolean); read-only.
|
||||
*/
|
||||
#define EXT_SYNC_LOCKED 0x004
|
||||
|
||||
/*
|
||||
* Current sample rate (CLOCK_RATE_* >> CLOCK_RATE_SHIFT), _32000-_192000 or
|
||||
* _NONE; read-only.
|
||||
*/
|
||||
#define EXT_SYNC_RATE 0x008
|
||||
|
||||
/*
|
||||
* ADAT user data bits; read-only.
|
||||
*/
|
||||
#define EXT_SYNC_ADAT_USER_DATA 0x00c
|
||||
/* The data bits, if available. */
|
||||
#define ADAT_USER_DATA_MASK 0x0f
|
||||
/* The data bits are not available. */
|
||||
#define ADAT_USER_DATA_NO_DATA 0x10
|
||||
|
||||
#endif
|
||||
Разница между файлами не показана из-за своего большого размера
Загрузить разницу
|
|
@ -90,7 +90,7 @@ int fcp_avc_transaction(struct fw_unit *unit,
|
|||
: TCODE_WRITE_BLOCK_REQUEST;
|
||||
ret = snd_fw_transaction(t.unit, tcode,
|
||||
CSR_REGISTER_BASE + CSR_FCP_COMMAND,
|
||||
(void *)command, command_size);
|
||||
(void *)command, command_size, 0);
|
||||
if (ret < 0)
|
||||
break;
|
||||
|
||||
|
|
|
|||
|
|
@ -217,7 +217,7 @@ static void isight_packet(struct fw_iso_context *context, u32 cycle,
|
|||
|
||||
static int isight_connect(struct isight *isight)
|
||||
{
|
||||
int ch, err, rcode, errors = 0;
|
||||
int ch, err;
|
||||
__be32 value;
|
||||
|
||||
retry_after_bus_reset:
|
||||
|
|
@ -230,27 +230,19 @@ retry_after_bus_reset:
|
|||
}
|
||||
|
||||
value = cpu_to_be32(ch | (isight->device->max_speed << SPEED_SHIFT));
|
||||
for (;;) {
|
||||
rcode = fw_run_transaction(
|
||||
isight->device->card,
|
||||
TCODE_WRITE_QUADLET_REQUEST,
|
||||
isight->device->node_id,
|
||||
isight->resources.generation,
|
||||
isight->device->max_speed,
|
||||
isight->audio_base + REG_ISO_TX_CONFIG,
|
||||
&value, 4);
|
||||
if (rcode == RCODE_COMPLETE) {
|
||||
return 0;
|
||||
} else if (rcode == RCODE_GENERATION) {
|
||||
fw_iso_resources_free(&isight->resources);
|
||||
goto retry_after_bus_reset;
|
||||
} else if (rcode_is_permanent_error(rcode) || ++errors >= 3) {
|
||||
err = -EIO;
|
||||
goto err_resources;
|
||||
}
|
||||
msleep(5);
|
||||
err = snd_fw_transaction(isight->unit, TCODE_WRITE_QUADLET_REQUEST,
|
||||
isight->audio_base + REG_ISO_TX_CONFIG,
|
||||
&value, 4, FW_FIXED_GENERATION |
|
||||
isight->resources.generation);
|
||||
if (err == -EAGAIN) {
|
||||
fw_iso_resources_free(&isight->resources);
|
||||
goto retry_after_bus_reset;
|
||||
} else if (err < 0) {
|
||||
goto err_resources;
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
||||
err_resources:
|
||||
fw_iso_resources_free(&isight->resources);
|
||||
error:
|
||||
|
|
@ -315,17 +307,19 @@ static int isight_hw_params(struct snd_pcm_substream *substream,
|
|||
static int reg_read(struct isight *isight, int offset, __be32 *value)
|
||||
{
|
||||
return snd_fw_transaction(isight->unit, TCODE_READ_QUADLET_REQUEST,
|
||||
isight->audio_base + offset, value, 4);
|
||||
isight->audio_base + offset, value, 4, 0);
|
||||
}
|
||||
|
||||
static int reg_write(struct isight *isight, int offset, __be32 value)
|
||||
{
|
||||
return snd_fw_transaction(isight->unit, TCODE_WRITE_QUADLET_REQUEST,
|
||||
isight->audio_base + offset, &value, 4);
|
||||
isight->audio_base + offset, &value, 4, 0);
|
||||
}
|
||||
|
||||
static void isight_stop_streaming(struct isight *isight)
|
||||
{
|
||||
__be32 value;
|
||||
|
||||
if (!isight->context)
|
||||
return;
|
||||
|
||||
|
|
@ -333,7 +327,10 @@ static void isight_stop_streaming(struct isight *isight)
|
|||
fw_iso_context_destroy(isight->context);
|
||||
isight->context = NULL;
|
||||
fw_iso_resources_free(&isight->resources);
|
||||
reg_write(isight, REG_AUDIO_ENABLE, 0);
|
||||
value = 0;
|
||||
snd_fw_transaction(isight->unit, TCODE_WRITE_QUADLET_REQUEST,
|
||||
isight->audio_base + REG_AUDIO_ENABLE,
|
||||
&value, 4, FW_QUIET);
|
||||
}
|
||||
|
||||
static int isight_hw_free(struct snd_pcm_substream *substream)
|
||||
|
|
|
|||
|
|
@ -11,7 +11,7 @@
|
|||
#include <linux/module.h>
|
||||
#include "lib.h"
|
||||
|
||||
#define ERROR_RETRY_DELAY_MS 5
|
||||
#define ERROR_RETRY_DELAY_MS 20
|
||||
|
||||
/**
|
||||
* snd_fw_transaction - send a request and wait for its completion
|
||||
|
|
@ -20,6 +20,9 @@
|
|||
* @offset: the address in the target's address space
|
||||
* @buffer: input/output data
|
||||
* @length: length of @buffer
|
||||
* @flags: use %FW_FIXED_GENERATION and add the generation value to attempt the
|
||||
* request only in that generation; use %FW_QUIET to suppress error
|
||||
* messages
|
||||
*
|
||||
* Submits an asynchronous request to the target device, and waits for the
|
||||
* response. The node ID and the current generation are derived from @unit.
|
||||
|
|
@ -27,14 +30,18 @@
|
|||
* Returns zero on success, or a negative error code.
|
||||
*/
|
||||
int snd_fw_transaction(struct fw_unit *unit, int tcode,
|
||||
u64 offset, void *buffer, size_t length)
|
||||
u64 offset, void *buffer, size_t length,
|
||||
unsigned int flags)
|
||||
{
|
||||
struct fw_device *device = fw_parent_device(unit);
|
||||
int generation, rcode, tries = 0;
|
||||
|
||||
generation = flags & FW_GENERATION_MASK;
|
||||
for (;;) {
|
||||
generation = device->generation;
|
||||
smp_rmb(); /* node_id vs. generation */
|
||||
if (!(flags & FW_FIXED_GENERATION)) {
|
||||
generation = device->generation;
|
||||
smp_rmb(); /* node_id vs. generation */
|
||||
}
|
||||
rcode = fw_run_transaction(device->card, tcode,
|
||||
device->node_id, generation,
|
||||
device->max_speed, offset,
|
||||
|
|
@ -43,9 +50,14 @@ int snd_fw_transaction(struct fw_unit *unit, int tcode,
|
|||
if (rcode == RCODE_COMPLETE)
|
||||
return 0;
|
||||
|
||||
if (rcode == RCODE_GENERATION && (flags & FW_FIXED_GENERATION))
|
||||
return -EAGAIN;
|
||||
|
||||
if (rcode_is_permanent_error(rcode) || ++tries >= 3) {
|
||||
dev_err(&unit->device, "transaction failed: %s\n",
|
||||
fw_rcode_string(rcode));
|
||||
if (!(flags & FW_QUIET))
|
||||
dev_err(&unit->device,
|
||||
"transaction failed: %s\n",
|
||||
fw_rcode_string(rcode));
|
||||
return -EIO;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -6,8 +6,13 @@
|
|||
|
||||
struct fw_unit;
|
||||
|
||||
#define FW_GENERATION_MASK 0x00ff
|
||||
#define FW_FIXED_GENERATION 0x0100
|
||||
#define FW_QUIET 0x0200
|
||||
|
||||
int snd_fw_transaction(struct fw_unit *unit, int tcode,
|
||||
u64 offset, void *buffer, size_t length);
|
||||
u64 offset, void *buffer, size_t length,
|
||||
unsigned int flags);
|
||||
|
||||
/* returns true if retrying the transaction would not make sense */
|
||||
static inline bool rcode_is_permanent_error(int rcode)
|
||||
|
|
|
|||
|
|
@ -369,7 +369,7 @@ static int scs_init_hss_address(struct scs *scs)
|
|||
data = cpu_to_be64(((u64)HSS1394_TAG_CHANGE_ADDRESS << 56) |
|
||||
scs->hss_handler.offset);
|
||||
err = snd_fw_transaction(scs->unit, TCODE_WRITE_BLOCK_REQUEST,
|
||||
HSS1394_ADDRESS, &data, 8);
|
||||
HSS1394_ADDRESS, &data, 8, 0);
|
||||
if (err < 0)
|
||||
dev_err(&scs->unit->device, "HSS1394 communication failed\n");
|
||||
|
||||
|
|
@ -455,12 +455,16 @@ err_card:
|
|||
static void scs_update(struct fw_unit *unit)
|
||||
{
|
||||
struct scs *scs = dev_get_drvdata(&unit->device);
|
||||
int generation;
|
||||
__be64 data;
|
||||
|
||||
data = cpu_to_be64(((u64)HSS1394_TAG_CHANGE_ADDRESS << 56) |
|
||||
scs->hss_handler.offset);
|
||||
generation = fw_parent_device(unit)->generation;
|
||||
smp_rmb(); /* node_id vs. generation */
|
||||
snd_fw_transaction(scs->unit, TCODE_WRITE_BLOCK_REQUEST,
|
||||
HSS1394_ADDRESS, &data, 8);
|
||||
HSS1394_ADDRESS, &data, 8,
|
||||
FW_FIXED_GENERATION | generation);
|
||||
}
|
||||
|
||||
static void scs_remove(struct fw_unit *unit)
|
||||
|
|
|
|||
|
|
@ -52,7 +52,6 @@ struct fwspk {
|
|||
struct mutex mutex;
|
||||
struct cmp_connection connection;
|
||||
struct amdtp_out_stream stream;
|
||||
bool stream_running;
|
||||
bool mute;
|
||||
s16 volume[6];
|
||||
s16 volume_min;
|
||||
|
|
@ -188,10 +187,9 @@ static int fwspk_close(struct snd_pcm_substream *substream)
|
|||
|
||||
static void fwspk_stop_stream(struct fwspk *fwspk)
|
||||
{
|
||||
if (fwspk->stream_running) {
|
||||
if (amdtp_out_stream_running(&fwspk->stream)) {
|
||||
amdtp_out_stream_stop(&fwspk->stream);
|
||||
cmp_connection_break(&fwspk->connection);
|
||||
fwspk->stream_running = false;
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -246,8 +244,10 @@ static int fwspk_hw_params(struct snd_pcm_substream *substream,
|
|||
if (err < 0)
|
||||
goto error;
|
||||
|
||||
amdtp_out_stream_set_rate(&fwspk->stream, params_rate(hw_params));
|
||||
amdtp_out_stream_set_pcm(&fwspk->stream, params_channels(hw_params));
|
||||
amdtp_out_stream_set_parameters(&fwspk->stream,
|
||||
params_rate(hw_params),
|
||||
params_channels(hw_params),
|
||||
0);
|
||||
|
||||
amdtp_out_stream_set_pcm_format(&fwspk->stream,
|
||||
params_format(hw_params));
|
||||
|
|
@ -285,7 +285,7 @@ static int fwspk_prepare(struct snd_pcm_substream *substream)
|
|||
if (amdtp_out_streaming_error(&fwspk->stream))
|
||||
fwspk_stop_stream(fwspk);
|
||||
|
||||
if (!fwspk->stream_running) {
|
||||
if (!amdtp_out_stream_running(&fwspk->stream)) {
|
||||
err = cmp_connection_establish(&fwspk->connection,
|
||||
amdtp_out_stream_get_max_payload(&fwspk->stream));
|
||||
if (err < 0)
|
||||
|
|
@ -296,8 +296,6 @@ static int fwspk_prepare(struct snd_pcm_substream *substream)
|
|||
fwspk->connection.speed);
|
||||
if (err < 0)
|
||||
goto err_connection;
|
||||
|
||||
fwspk->stream_running = true;
|
||||
}
|
||||
|
||||
mutex_unlock(&fwspk->mutex);
|
||||
|
|
@ -647,7 +645,7 @@ static u32 fwspk_read_firmware_version(struct fw_unit *unit)
|
|||
int err;
|
||||
|
||||
err = snd_fw_transaction(unit, TCODE_READ_QUADLET_REQUEST,
|
||||
OXFORD_FIRMWARE_ID_ADDRESS, &data, 4);
|
||||
OXFORD_FIRMWARE_ID_ADDRESS, &data, 4, 0);
|
||||
return err >= 0 ? be32_to_cpu(data) : 0;
|
||||
}
|
||||
|
||||
|
|
|
|||
Загрузка…
Ссылка в новой задаче