drm/exynos: Add plane support with fimd
The exynos fimd supports 5 window overlays. Only one window overlay of fimd is used by the crtc, so we need plane feature to use the rest window overlays. This creates one ioctl exynos specific - DRM_EXYNOS_PLANE_SET_ZPOS, it is the ioctl to decide for user to assign which window overlay. Signed-off-by: Joonyoung Shim <jy0922.shim@samsung.com> Signed-off-by: Inki Dae <inki.dae@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
This commit is contained in:
Joonyoung Shim
Inki Dae
Родитель
cb91f6a078
Коммит
864ee9e6f6
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@ -5,7 +5,8 @@
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ccflags-y := -Iinclude/drm -Idrivers/gpu/drm/exynos
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exynosdrm-y := exynos_drm_drv.o exynos_drm_encoder.o exynos_drm_connector.o \
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exynos_drm_crtc.o exynos_drm_fbdev.o exynos_drm_fb.o \
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exynos_drm_buf.o exynos_drm_gem.o exynos_drm_core.o
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exynos_drm_buf.o exynos_drm_gem.o exynos_drm_core.o \
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exynos_drm_plane.o
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obj-$(CONFIG_DRM_EXYNOS) += exynosdrm.o
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obj-$(CONFIG_DRM_EXYNOS_FIMD) += exynos_drm_fimd.o
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@ -380,6 +380,7 @@ int exynos_drm_crtc_create(struct drm_device *dev, unsigned int nr)
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exynos_crtc->pipe = nr;
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exynos_crtc->dpms = DRM_MODE_DPMS_OFF;
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exynos_crtc->overlay.zpos = DEFAULT_ZPOS;
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crtc = &exynos_crtc->drm_crtc;
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private->crtc[nr] = crtc;
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@ -36,6 +36,7 @@
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#include "exynos_drm_fbdev.h"
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#include "exynos_drm_fb.h"
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#include "exynos_drm_gem.h"
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#include "exynos_drm_plane.h"
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#define DRIVER_NAME "exynos-drm"
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#define DRIVER_DESC "Samsung SoC DRM"
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@ -77,6 +78,12 @@ static int exynos_drm_load(struct drm_device *dev, unsigned long flags)
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goto err_crtc;
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}
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for (nr = 0; nr < MAX_PLANE; nr++) {
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ret = exynos_plane_init(dev, nr);
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if (ret)
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goto err_crtc;
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}
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ret = drm_vblank_init(dev, MAX_CRTC);
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if (ret)
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goto err_crtc;
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@ -163,6 +170,8 @@ static struct drm_ioctl_desc exynos_ioctls[] = {
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DRM_AUTH),
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DRM_IOCTL_DEF_DRV(EXYNOS_GEM_MMAP,
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exynos_drm_gem_mmap_ioctl, DRM_UNLOCKED | DRM_AUTH),
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DRM_IOCTL_DEF_DRV(EXYNOS_PLANE_SET_ZPOS, exynos_plane_set_zpos_ioctl,
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DRM_UNLOCKED | DRM_AUTH),
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};
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static const struct file_operations exynos_drm_driver_fops = {
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@ -33,6 +33,8 @@
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#include "drm.h"
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#define MAX_CRTC 2
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#define MAX_PLANE 5
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#define DEFAULT_ZPOS -1
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struct drm_device;
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struct exynos_drm_overlay;
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@ -57,8 +59,8 @@ enum exynos_drm_output_type {
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struct exynos_drm_overlay_ops {
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void (*mode_set)(struct device *subdrv_dev,
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struct exynos_drm_overlay *overlay);
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void (*commit)(struct device *subdrv_dev);
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void (*disable)(struct device *subdrv_dev);
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void (*commit)(struct device *subdrv_dev, int zpos);
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void (*disable)(struct device *subdrv_dev, int zpos);
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};
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/*
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@ -83,6 +85,7 @@ struct exynos_drm_overlay_ops {
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* @dma_addr: bus(accessed by dma) address to the memory region allocated
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* for a overlay.
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* @vaddr: virtual memory addresss to this overlay.
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* @zpos: order of overlay layer(z position).
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* @default_win: a window to be enabled.
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* @color_key: color key on or off.
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* @index_color: if using color key feature then this value would be used
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@ -111,6 +114,7 @@ struct exynos_drm_overlay {
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unsigned int pitch;
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dma_addr_t dma_addr;
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void __iomem *vaddr;
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int zpos;
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bool default_win;
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bool color_key;
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@ -294,12 +294,27 @@ void exynos_drm_disable_vblank(struct drm_encoder *encoder, void *data)
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manager_ops->disable_vblank(manager->dev);
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}
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void exynos_drm_encoder_crtc_commit(struct drm_encoder *encoder, void *data)
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void exynos_drm_encoder_crtc_plane_commit(struct drm_encoder *encoder,
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void *data)
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{
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struct exynos_drm_manager *manager =
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to_exynos_encoder(encoder)->manager;
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struct exynos_drm_overlay_ops *overlay_ops = manager->overlay_ops;
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int zpos = DEFAULT_ZPOS;
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if (data)
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zpos = *(int *)data;
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if (overlay_ops && overlay_ops->commit)
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overlay_ops->commit(manager->dev, zpos);
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}
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void exynos_drm_encoder_crtc_commit(struct drm_encoder *encoder, void *data)
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{
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struct exynos_drm_manager *manager =
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to_exynos_encoder(encoder)->manager;
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int crtc = *(int *)data;
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int zpos = DEFAULT_ZPOS;
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DRM_DEBUG_KMS("%s\n", __FILE__);
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@ -309,8 +324,7 @@ void exynos_drm_encoder_crtc_commit(struct drm_encoder *encoder, void *data)
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*/
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manager->pipe = crtc;
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if (overlay_ops && overlay_ops->commit)
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overlay_ops->commit(manager->dev);
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exynos_drm_encoder_crtc_plane_commit(encoder, &zpos);
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}
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void exynos_drm_encoder_dpms_from_crtc(struct drm_encoder *encoder, void *data)
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@ -375,11 +389,15 @@ void exynos_drm_encoder_crtc_disable(struct drm_encoder *encoder, void *data)
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struct exynos_drm_manager *manager =
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to_exynos_encoder(encoder)->manager;
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struct exynos_drm_overlay_ops *overlay_ops = manager->overlay_ops;
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int zpos = DEFAULT_ZPOS;
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DRM_DEBUG_KMS("\n");
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if (data)
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zpos = *(int *)data;
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if (overlay_ops && overlay_ops->disable)
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overlay_ops->disable(manager->dev);
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overlay_ops->disable(manager->dev, zpos);
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}
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MODULE_AUTHOR("Inki Dae <inki.dae@samsung.com>");
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@ -39,6 +39,8 @@ void exynos_drm_fn_encoder(struct drm_crtc *crtc, void *data,
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void (*fn)(struct drm_encoder *, void *));
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void exynos_drm_enable_vblank(struct drm_encoder *encoder, void *data);
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void exynos_drm_disable_vblank(struct drm_encoder *encoder, void *data);
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void exynos_drm_encoder_crtc_plane_commit(struct drm_encoder *encoder,
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void *data);
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void exynos_drm_encoder_crtc_commit(struct drm_encoder *encoder, void *data);
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void exynos_drm_encoder_dpms_from_crtc(struct drm_encoder *encoder,
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void *data);
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@ -161,12 +161,15 @@ static void fimd_apply(struct device *subdrv_dev)
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struct exynos_drm_manager_ops *mgr_ops = mgr->ops;
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struct exynos_drm_overlay_ops *ovl_ops = mgr->overlay_ops;
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struct fimd_win_data *win_data;
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int i;
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DRM_DEBUG_KMS("%s\n", __FILE__);
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win_data = &ctx->win_data[ctx->default_win];
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if (win_data->enabled && (ovl_ops && ovl_ops->commit))
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ovl_ops->commit(subdrv_dev);
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for (i = 0; i < WINDOWS_NR; i++) {
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win_data = &ctx->win_data[i];
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if (win_data->enabled && (ovl_ops && ovl_ops->commit))
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ovl_ops->commit(subdrv_dev, i);
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}
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if (mgr_ops && mgr_ops->commit)
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mgr_ops->commit(subdrv_dev);
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@ -277,6 +280,7 @@ static void fimd_win_mode_set(struct device *dev,
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{
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struct fimd_context *ctx = get_fimd_context(dev);
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struct fimd_win_data *win_data;
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int win;
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unsigned long offset;
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DRM_DEBUG_KMS("%s\n", __FILE__);
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@ -286,12 +290,19 @@ static void fimd_win_mode_set(struct device *dev,
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return;
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}
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win = overlay->zpos;
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if (win == DEFAULT_ZPOS)
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win = ctx->default_win;
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if (win < 0 || win > WINDOWS_NR)
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return;
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offset = overlay->fb_x * (overlay->bpp >> 3);
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offset += overlay->fb_y * overlay->pitch;
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DRM_DEBUG_KMS("offset = 0x%lx, pitch = %x\n", offset, overlay->pitch);
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win_data = &ctx->win_data[ctx->default_win];
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win_data = &ctx->win_data[win];
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win_data->offset_x = overlay->crtc_x;
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win_data->offset_y = overlay->crtc_y;
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@ -394,15 +405,18 @@ static void fimd_win_set_colkey(struct device *dev, unsigned int win)
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writel(keycon1, ctx->regs + WKEYCON1_BASE(win));
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}
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static void fimd_win_commit(struct device *dev)
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static void fimd_win_commit(struct device *dev, int zpos)
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{
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struct fimd_context *ctx = get_fimd_context(dev);
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struct fimd_win_data *win_data;
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int win = ctx->default_win;
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int win = zpos;
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unsigned long val, alpha, size;
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DRM_DEBUG_KMS("%s\n", __FILE__);
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if (win == DEFAULT_ZPOS)
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win = ctx->default_win;
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if (win < 0 || win > WINDOWS_NR)
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return;
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@ -499,15 +513,18 @@ static void fimd_win_commit(struct device *dev)
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win_data->enabled = true;
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}
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static void fimd_win_disable(struct device *dev)
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static void fimd_win_disable(struct device *dev, int zpos)
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{
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struct fimd_context *ctx = get_fimd_context(dev);
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struct fimd_win_data *win_data;
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int win = ctx->default_win;
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int win = zpos;
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u32 val;
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DRM_DEBUG_KMS("%s\n", __FILE__);
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if (win == DEFAULT_ZPOS)
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win = ctx->default_win;
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if (win < 0 || win > WINDOWS_NR)
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return;
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@ -0,0 +1,163 @@
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/*
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* Copyright (C) 2011 Samsung Electronics Co.Ltd
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* Authors: Joonyoung Shim <jy0922.shim@samsung.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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*/
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#include "drmP.h"
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#include "exynos_drm.h"
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#include "exynos_drm_crtc.h"
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#include "exynos_drm_drv.h"
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#include "exynos_drm_encoder.h"
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struct exynos_plane {
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struct drm_plane base;
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struct exynos_drm_overlay overlay;
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bool enabled;
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};
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static int
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exynos_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
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struct drm_framebuffer *fb, int crtc_x, int crtc_y,
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unsigned int crtc_w, unsigned int crtc_h,
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uint32_t src_x, uint32_t src_y,
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uint32_t src_w, uint32_t src_h)
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{
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struct exynos_plane *exynos_plane =
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container_of(plane, struct exynos_plane, base);
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struct exynos_drm_overlay *overlay = &exynos_plane->overlay;
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struct exynos_drm_crtc_pos pos;
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unsigned int x = src_x >> 16;
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unsigned int y = src_y >> 16;
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int ret;
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DRM_DEBUG_KMS("[%d] %s\n", __LINE__, __func__);
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memset(&pos, 0, sizeof(struct exynos_drm_crtc_pos));
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pos.crtc_x = crtc_x;
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pos.crtc_y = crtc_y;
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pos.crtc_w = crtc_w;
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pos.crtc_h = crtc_h;
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pos.fb_x = x;
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pos.fb_y = y;
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/* TODO: scale feature */
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ret = exynos_drm_overlay_update(overlay, fb, &crtc->mode, &pos);
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if (ret < 0)
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return ret;
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exynos_drm_fn_encoder(crtc, overlay,
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exynos_drm_encoder_crtc_mode_set);
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exynos_drm_fn_encoder(crtc, &overlay->zpos,
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exynos_drm_encoder_crtc_plane_commit);
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exynos_plane->enabled = true;
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return 0;
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}
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static int exynos_disable_plane(struct drm_plane *plane)
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{
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struct exynos_plane *exynos_plane =
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container_of(plane, struct exynos_plane, base);
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struct exynos_drm_overlay *overlay = &exynos_plane->overlay;
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DRM_DEBUG_KMS("[%d] %s\n", __LINE__, __func__);
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if (!exynos_plane->enabled)
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return 0;
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exynos_drm_fn_encoder(plane->crtc, &overlay->zpos,
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exynos_drm_encoder_crtc_disable);
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exynos_plane->enabled = false;
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exynos_plane->overlay.zpos = DEFAULT_ZPOS;
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return 0;
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}
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static void exynos_plane_destroy(struct drm_plane *plane)
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{
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struct exynos_plane *exynos_plane =
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container_of(plane, struct exynos_plane, base);
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DRM_DEBUG_KMS("[%d] %s\n", __LINE__, __func__);
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exynos_disable_plane(plane);
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drm_plane_cleanup(plane);
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kfree(exynos_plane);
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}
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static struct drm_plane_funcs exynos_plane_funcs = {
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.update_plane = exynos_update_plane,
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.disable_plane = exynos_disable_plane,
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.destroy = exynos_plane_destroy,
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};
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int exynos_plane_init(struct drm_device *dev, unsigned int nr)
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{
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struct exynos_plane *exynos_plane;
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uint32_t possible_crtcs;
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exynos_plane = kzalloc(sizeof(struct exynos_plane), GFP_KERNEL);
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if (!exynos_plane)
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return -ENOMEM;
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/* all CRTCs are available */
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possible_crtcs = (1 << MAX_CRTC) - 1;
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exynos_plane->overlay.zpos = DEFAULT_ZPOS;
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/* TODO: format */
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return drm_plane_init(dev, &exynos_plane->base, possible_crtcs,
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&exynos_plane_funcs, NULL, 0);
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}
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int exynos_plane_set_zpos_ioctl(struct drm_device *dev, void *data,
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struct drm_file *file_priv)
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{
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struct drm_exynos_plane_set_zpos *zpos_req = data;
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struct drm_mode_object *obj;
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struct drm_plane *plane;
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struct exynos_plane *exynos_plane;
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int ret = 0;
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DRM_DEBUG_KMS("[%d] %s\n", __LINE__, __func__);
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if (!drm_core_check_feature(dev, DRIVER_MODESET))
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return -EINVAL;
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if (zpos_req->zpos < 0 || zpos_req->zpos >= MAX_PLANE) {
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if (zpos_req->zpos != DEFAULT_ZPOS) {
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DRM_ERROR("zpos not within limits\n");
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return -EINVAL;
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}
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}
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mutex_lock(&dev->mode_config.mutex);
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obj = drm_mode_object_find(dev, zpos_req->plane_id,
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DRM_MODE_OBJECT_PLANE);
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if (!obj) {
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DRM_DEBUG_KMS("Unknown plane ID %d\n",
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zpos_req->plane_id);
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ret = -EINVAL;
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goto out;
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}
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plane = obj_to_plane(obj);
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exynos_plane = container_of(plane, struct exynos_plane, base);
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exynos_plane->overlay.zpos = zpos_req->zpos;
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out:
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mutex_unlock(&dev->mode_config.mutex);
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return ret;
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}
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@ -0,0 +1,14 @@
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/*
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* Copyright (C) 2011 Samsung Electronics Co.Ltd
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* Authors: Joonyoung Shim <jy0922.shim@samsung.com>
|
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*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
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*
|
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*/
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int exynos_plane_init(struct drm_device *dev, unsigned int nr);
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int exynos_plane_set_zpos_ioctl(struct drm_device *dev, void *data,
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||||
struct drm_file *file_priv);
|
||||
|
|
@ -74,9 +74,16 @@ struct drm_exynos_gem_mmap {
|
|||
uint64_t mapped;
|
||||
};
|
||||
|
||||
struct drm_exynos_plane_set_zpos {
|
||||
__u32 plane_id;
|
||||
__s32 zpos;
|
||||
};
|
||||
|
||||
#define DRM_EXYNOS_GEM_CREATE 0x00
|
||||
#define DRM_EXYNOS_GEM_MAP_OFFSET 0x01
|
||||
#define DRM_EXYNOS_GEM_MMAP 0x02
|
||||
/* Reserved 0x03 ~ 0x05 for exynos specific gem ioctl */
|
||||
#define DRM_EXYNOS_PLANE_SET_ZPOS 0x06
|
||||
|
||||
#define DRM_IOCTL_EXYNOS_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + \
|
||||
DRM_EXYNOS_GEM_CREATE, struct drm_exynos_gem_create)
|
||||
|
|
@ -87,6 +94,9 @@ struct drm_exynos_gem_mmap {
|
|||
#define DRM_IOCTL_EXYNOS_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + \
|
||||
DRM_EXYNOS_GEM_MMAP, struct drm_exynos_gem_mmap)
|
||||
|
||||
#define DRM_IOCTL_EXYNOS_PLANE_SET_ZPOS DRM_IOWR(DRM_COMMAND_BASE + \
|
||||
DRM_EXYNOS_PLANE_SET_ZPOS, struct drm_exynos_plane_set_zpos)
|
||||
|
||||
/**
|
||||
* Platform Specific Structure for DRM based FIMD.
|
||||
*
|
||||
|
|
|
|||
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