MIPS: Octeon: Do proper acknowledgment of CIU timer interrupts.
Signed-off-by: David Daney <ddaney@caviumnetworks.com> To: linux-mips@linux-mips.org To: netdev@vger.kernel.org To: gregkh@suse.de Patchwork: http://patchwork.linux-mips.org/patch/967/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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@ -51,9 +51,6 @@ static void octeon_irq_core_eoi(unsigned int irq)
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*/
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if (desc->status & IRQ_DISABLED)
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return;
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/* There is a race here. We should fix it. */
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/*
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* We don't need to disable IRQs to make these atomic since
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* they are already disabled earlier in the low level
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@ -201,6 +198,29 @@ static void octeon_irq_ciu0_ack_v2(unsigned int irq)
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cvmx_write_csr(CVMX_CIU_INTX_EN0_W1C(index), mask);
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}
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/*
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* CIU timer type interrupts must be acknoleged by writing a '1' bit
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* to their sum0 bit.
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*/
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static void octeon_irq_ciu0_timer_ack(unsigned int irq)
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{
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int index = cvmx_get_core_num() * 2;
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uint64_t mask = 1ull << (irq - OCTEON_IRQ_WORKQ0);
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cvmx_write_csr(CVMX_CIU_INTX_SUM0(index), mask);
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}
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static void octeon_irq_ciu0_timer_ack_v1(unsigned int irq)
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{
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octeon_irq_ciu0_timer_ack(irq);
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octeon_irq_ciu0_ack(irq);
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}
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static void octeon_irq_ciu0_timer_ack_v2(unsigned int irq)
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{
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octeon_irq_ciu0_timer_ack(irq);
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octeon_irq_ciu0_ack_v2(irq);
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}
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/*
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* Enable the irq on the current core for chips that have the EN*_W1{S,C}
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* registers.
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@ -304,6 +324,28 @@ static struct irq_chip octeon_irq_chip_ciu0 = {
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#endif
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};
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static struct irq_chip octeon_irq_chip_ciu0_timer_v2 = {
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.name = "CIU0-T",
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.enable = octeon_irq_ciu0_enable_v2,
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.disable = octeon_irq_ciu0_disable_all_v2,
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.ack = octeon_irq_ciu0_timer_ack_v2,
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.eoi = octeon_irq_ciu0_eoi_v2,
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#ifdef CONFIG_SMP
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.set_affinity = octeon_irq_ciu0_set_affinity_v2,
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#endif
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};
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static struct irq_chip octeon_irq_chip_ciu0_timer = {
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.name = "CIU0-T",
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.enable = octeon_irq_ciu0_enable,
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.disable = octeon_irq_ciu0_disable,
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.ack = octeon_irq_ciu0_timer_ack_v1,
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.eoi = octeon_irq_ciu0_eoi,
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#ifdef CONFIG_SMP
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.set_affinity = octeon_irq_ciu0_set_affinity,
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#endif
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};
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static void octeon_irq_ciu1_ack(unsigned int irq)
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{
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@ -587,6 +629,7 @@ void __init arch_init_irq(void)
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{
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int irq;
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struct irq_chip *chip0;
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struct irq_chip *chip0_timer;
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struct irq_chip *chip1;
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#ifdef CONFIG_SMP
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@ -602,9 +645,11 @@ void __init arch_init_irq(void)
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OCTEON_IS_MODEL(OCTEON_CN56XX_PASS2_X) ||
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OCTEON_IS_MODEL(OCTEON_CN52XX_PASS2_X)) {
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chip0 = &octeon_irq_chip_ciu0_v2;
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chip0_timer = &octeon_irq_chip_ciu0_timer_v2;
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chip1 = &octeon_irq_chip_ciu1_v2;
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} else {
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chip0 = &octeon_irq_chip_ciu0;
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chip0_timer = &octeon_irq_chip_ciu0_timer;
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chip1 = &octeon_irq_chip_ciu1;
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}
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@ -618,7 +663,21 @@ void __init arch_init_irq(void)
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/* 24 - 87 CIU_INT_SUM0 */
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for (irq = OCTEON_IRQ_WORKQ0; irq <= OCTEON_IRQ_BOOTDMA; irq++) {
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set_irq_chip_and_handler(irq, chip0, handle_percpu_irq);
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switch (irq) {
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case OCTEON_IRQ_GMX_DRP0:
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case OCTEON_IRQ_GMX_DRP1:
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case OCTEON_IRQ_IPD_DRP:
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case OCTEON_IRQ_KEY_ZERO:
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case OCTEON_IRQ_TIMER0:
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case OCTEON_IRQ_TIMER1:
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case OCTEON_IRQ_TIMER2:
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case OCTEON_IRQ_TIMER3:
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set_irq_chip_and_handler(irq, chip0_timer, handle_percpu_irq);
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break;
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default:
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set_irq_chip_and_handler(irq, chip0, handle_percpu_irq);
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break;
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}
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}
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/* 88 - 151 CIU_INT_SUM1 */
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