Merge branch 'pci/resource'
- Use ioremap(), not phys_to_virt() for platform ROM, to fix video ROM
mapping with CONFIG_HIGHMEM (Mikel Rychliski)
- Add support for root bus sizing so we don't have to assume host bridge
windows are known a priori (Ivan Kokshaysky)
- Fix alpha Nautilus PCI setup, which has been broken since we started
enforcing window limits in resource allocation (Ivan Kokshaysky)
* pci/resource:
alpha: Fix nautilus PCI setup
PCI: Add support for root bus sizing
PCI: Use ioremap(), not phys_to_virt() for platform ROM
This commit is contained in:
Bjorn Helgaas
Коммит
86845e37ac
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@ -187,10 +187,6 @@ nautilus_machine_check(unsigned long vector, unsigned long la_ptr)
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extern void pcibios_claim_one_bus(struct pci_bus *);
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static struct resource irongate_io = {
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.name = "Irongate PCI IO",
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.flags = IORESOURCE_IO,
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};
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static struct resource irongate_mem = {
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.name = "Irongate PCI MEM",
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.flags = IORESOURCE_MEM,
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@ -208,17 +204,19 @@ nautilus_init_pci(void)
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struct pci_controller *hose = hose_head;
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struct pci_host_bridge *bridge;
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struct pci_bus *bus;
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struct pci_dev *irongate;
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unsigned long bus_align, bus_size, pci_mem;
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unsigned long memtop = max_low_pfn << PAGE_SHIFT;
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int ret;
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bridge = pci_alloc_host_bridge(0);
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if (!bridge)
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return;
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/* Use default IO. */
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pci_add_resource(&bridge->windows, &ioport_resource);
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pci_add_resource(&bridge->windows, &iomem_resource);
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/* Irongate PCI memory aperture, calculate requred size before
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setting it up. */
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pci_add_resource(&bridge->windows, &irongate_mem);
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pci_add_resource(&bridge->windows, &busn_resource);
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bridge->dev.parent = NULL;
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bridge->sysdata = hose;
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@ -226,59 +224,49 @@ nautilus_init_pci(void)
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bridge->ops = alpha_mv.pci_ops;
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bridge->swizzle_irq = alpha_mv.pci_swizzle;
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bridge->map_irq = alpha_mv.pci_map_irq;
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bridge->size_windows = 1;
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/* Scan our single hose. */
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ret = pci_scan_root_bus_bridge(bridge);
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if (ret) {
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if (pci_scan_root_bus_bridge(bridge)) {
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pci_free_host_bridge(bridge);
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return;
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}
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bus = hose->bus = bridge->bus;
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pcibios_claim_one_bus(bus);
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irongate = pci_get_domain_bus_and_slot(pci_domain_nr(bus), 0, 0);
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bus->self = irongate;
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bus->resource[0] = &irongate_io;
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bus->resource[1] = &irongate_mem;
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pci_bus_size_bridges(bus);
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/* IO port range. */
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bus->resource[0]->start = 0;
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bus->resource[0]->end = 0xffff;
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/* Set up PCI memory range - limit is hardwired to 0xffffffff,
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base must be at aligned to 16Mb. */
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bus_align = bus->resource[1]->start;
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bus_size = bus->resource[1]->end + 1 - bus_align;
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/* Now we've got the size and alignment of PCI memory resources
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stored in irongate_mem. Set up the PCI memory range: limit is
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hardwired to 0xffffffff, base must be aligned to 16Mb. */
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bus_align = irongate_mem.start;
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bus_size = irongate_mem.end + 1 - bus_align;
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if (bus_align < 0x1000000UL)
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bus_align = 0x1000000UL;
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pci_mem = (0x100000000UL - bus_size) & -bus_align;
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irongate_mem.start = pci_mem;
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irongate_mem.end = 0xffffffffUL;
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bus->resource[1]->start = pci_mem;
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bus->resource[1]->end = 0xffffffffUL;
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if (request_resource(&iomem_resource, bus->resource[1]) < 0)
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/* Register our newly calculated PCI memory window in the resource
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tree. */
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if (request_resource(&iomem_resource, &irongate_mem) < 0)
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printk(KERN_ERR "Failed to request MEM on hose 0\n");
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printk(KERN_INFO "Irongate pci_mem %pR\n", &irongate_mem);
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if (pci_mem < memtop)
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memtop = pci_mem;
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if (memtop > alpha_mv.min_mem_address) {
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free_reserved_area(__va(alpha_mv.min_mem_address),
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__va(memtop), -1, NULL);
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printk("nautilus_init_pci: %ldk freed\n",
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printk(KERN_INFO "nautilus_init_pci: %ldk freed\n",
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(memtop - alpha_mv.min_mem_address) >> 10);
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}
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if ((IRONGATE0->dev_vendor >> 16) > 0x7006) /* Albacore? */
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IRONGATE0->pci_mem = pci_mem;
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pci_bus_assign_resources(bus);
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/* pci_common_swizzle() relies on bus->self being NULL
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for the root bus, so just clear it. */
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bus->self = NULL;
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pci_bus_add_devices(bus);
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}
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@ -192,30 +192,35 @@ static bool amdgpu_read_bios_from_rom(struct amdgpu_device *adev)
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static bool amdgpu_read_platform_bios(struct amdgpu_device *adev)
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{
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uint8_t __iomem *bios;
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size_t size;
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phys_addr_t rom = adev->pdev->rom;
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size_t romlen = adev->pdev->romlen;
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void __iomem *bios;
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adev->bios = NULL;
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bios = pci_platform_rom(adev->pdev, &size);
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if (!bios) {
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return false;
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}
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adev->bios = kzalloc(size, GFP_KERNEL);
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if (adev->bios == NULL)
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if (!rom || romlen == 0)
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return false;
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memcpy_fromio(adev->bios, bios, size);
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if (!check_atom_bios(adev->bios, size)) {
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kfree(adev->bios);
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adev->bios = kzalloc(romlen, GFP_KERNEL);
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if (!adev->bios)
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return false;
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}
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adev->bios_size = size;
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bios = ioremap(rom, romlen);
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if (!bios)
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goto free_bios;
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memcpy_fromio(adev->bios, bios, romlen);
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iounmap(bios);
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if (!check_atom_bios(adev->bios, romlen))
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goto free_bios;
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adev->bios_size = romlen;
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return true;
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free_bios:
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kfree(adev->bios);
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return false;
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}
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#ifdef CONFIG_ACPI
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@ -101,9 +101,13 @@ platform_init(struct nvkm_bios *bios, const char *name)
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else
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return ERR_PTR(-ENODEV);
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if (!pdev->rom || pdev->romlen == 0)
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return ERR_PTR(-ENODEV);
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if ((priv = kmalloc(sizeof(*priv), GFP_KERNEL))) {
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priv->size = pdev->romlen;
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if (ret = -ENODEV,
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(priv->rom = pci_platform_rom(pdev, &priv->size)))
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(priv->rom = ioremap(pdev->rom, pdev->romlen)))
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return priv;
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kfree(priv);
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}
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@ -111,11 +115,20 @@ platform_init(struct nvkm_bios *bios, const char *name)
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return ERR_PTR(ret);
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}
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static void
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platform_fini(void *data)
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{
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struct priv *priv = data;
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iounmap(priv->rom);
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kfree(priv);
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}
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const struct nvbios_source
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nvbios_platform = {
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.name = "PLATFORM",
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.init = platform_init,
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.fini = (void(*)(void *))kfree,
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.fini = platform_fini,
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.read = pcirom_read,
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.rw = true,
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};
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@ -108,25 +108,33 @@ static bool radeon_read_bios(struct radeon_device *rdev)
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static bool radeon_read_platform_bios(struct radeon_device *rdev)
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{
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uint8_t __iomem *bios;
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size_t size;
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phys_addr_t rom = rdev->pdev->rom;
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size_t romlen = rdev->pdev->romlen;
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void __iomem *bios;
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rdev->bios = NULL;
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bios = pci_platform_rom(rdev->pdev, &size);
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if (!bios) {
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if (!rom || romlen == 0)
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return false;
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}
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if (size == 0 || bios[0] != 0x55 || bios[1] != 0xaa) {
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rdev->bios = kzalloc(romlen, GFP_KERNEL);
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if (!rdev->bios)
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return false;
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}
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rdev->bios = kmemdup(bios, size, GFP_KERNEL);
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if (rdev->bios == NULL) {
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return false;
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}
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bios = ioremap(rom, romlen);
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if (!bios)
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goto free_bios;
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memcpy_fromio(rdev->bios, bios, romlen);
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iounmap(bios);
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if (rdev->bios[0] != 0x55 || rdev->bios[1] != 0xaa)
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goto free_bios;
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return true;
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free_bios:
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kfree(rdev->bios);
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return false;
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}
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#ifdef CONFIG_ACPI
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@ -195,20 +195,3 @@ void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom)
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pci_disable_rom(pdev);
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}
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EXPORT_SYMBOL(pci_unmap_rom);
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/**
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* pci_platform_rom - provides a pointer to any ROM image provided by the
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* platform
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* @pdev: pointer to pci device struct
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* @size: pointer to receive size of pci window over ROM
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*/
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void __iomem *pci_platform_rom(struct pci_dev *pdev, size_t *size)
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{
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if (pdev->rom && pdev->romlen) {
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*size = pdev->romlen;
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return phys_to_virt((phys_addr_t)pdev->rom);
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}
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return NULL;
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}
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EXPORT_SYMBOL(pci_platform_rom);
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@ -846,7 +846,7 @@ static resource_size_t window_alignment(struct pci_bus *bus, unsigned long type)
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* Per spec, I/O windows are 4K-aligned, but some bridges have
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* an extension to support 1K alignment.
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*/
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if (bus->self->io_window_1k)
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if (bus->self && bus->self->io_window_1k)
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align = PCI_P2P_DEFAULT_IO_ALIGN_1K;
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else
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align = PCI_P2P_DEFAULT_IO_ALIGN;
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@ -920,7 +920,7 @@ static void pbus_size_io(struct pci_bus *bus, resource_size_t min_size,
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calculate_iosize(size, min_size, size1, add_size, children_add_size,
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resource_size(b_res), min_align);
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if (!size0 && !size1) {
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if (b_res->start || b_res->end)
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if (bus->self && (b_res->start || b_res->end))
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pci_info(bus->self, "disabling bridge window %pR to %pR (unused)\n",
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b_res, &bus->busn_res);
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b_res->flags = 0;
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@ -930,7 +930,7 @@ static void pbus_size_io(struct pci_bus *bus, resource_size_t min_size,
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b_res->start = min_align;
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b_res->end = b_res->start + size0 - 1;
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b_res->flags |= IORESOURCE_STARTALIGN;
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if (size1 > size0 && realloc_head) {
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if (bus->self && size1 > size0 && realloc_head) {
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add_to_list(realloc_head, bus->self, b_res, size1-size0,
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min_align);
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pci_info(bus->self, "bridge window %pR to %pR add_size %llx\n",
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@ -1073,7 +1073,7 @@ static int pbus_size_mem(struct pci_bus *bus, unsigned long mask,
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calculate_memsize(size, min_size, add_size, children_add_size,
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resource_size(b_res), add_align);
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if (!size0 && !size1) {
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if (b_res->start || b_res->end)
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if (bus->self && (b_res->start || b_res->end))
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pci_info(bus->self, "disabling bridge window %pR to %pR (unused)\n",
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b_res, &bus->busn_res);
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b_res->flags = 0;
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|
@ -1082,7 +1082,7 @@ static int pbus_size_mem(struct pci_bus *bus, unsigned long mask,
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b_res->start = min_align;
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b_res->end = size0 + min_align - 1;
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b_res->flags |= IORESOURCE_STARTALIGN;
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if (size1 > size0 && realloc_head) {
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if (bus->self && size1 > size0 && realloc_head) {
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add_to_list(realloc_head, bus->self, b_res, size1-size0, add_align);
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pci_info(bus->self, "bridge window %pR to %pR add_size %llx add_align %llx\n",
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b_res, &bus->busn_res,
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@ -1196,8 +1196,9 @@ void __pci_bus_size_bridges(struct pci_bus *bus, struct list_head *realloc_head)
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unsigned long mask, prefmask, type2 = 0, type3 = 0;
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resource_size_t additional_io_size = 0, additional_mmio_size = 0,
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additional_mmio_pref_size = 0;
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struct resource *b_res;
|
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int ret;
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struct resource *pref;
|
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struct pci_host_bridge *host;
|
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int hdr_type, i, ret;
|
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|
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list_for_each_entry(dev, &bus->devices, bus_list) {
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struct pci_bus *b = dev->subordinate;
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|
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@ -1217,10 +1218,20 @@ void __pci_bus_size_bridges(struct pci_bus *bus, struct list_head *realloc_head)
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}
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/* The root bus? */
|
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if (pci_is_root_bus(bus))
|
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return;
|
||||
if (pci_is_root_bus(bus)) {
|
||||
host = to_pci_host_bridge(bus->bridge);
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||||
if (!host->size_windows)
|
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return;
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pci_bus_for_each_resource(bus, pref, i)
|
||||
if (pref && (pref->flags & IORESOURCE_PREFETCH))
|
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break;
|
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hdr_type = -1; /* Intentionally invalid - not a PCI device. */
|
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} else {
|
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pref = &bus->self->resource[PCI_BRIDGE_RESOURCES + 2];
|
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hdr_type = bus->self->hdr_type;
|
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}
|
||||
|
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switch (bus->self->hdr_type) {
|
||||
switch (hdr_type) {
|
||||
case PCI_HEADER_TYPE_CARDBUS:
|
||||
/* Don't size CardBuses yet */
|
||||
break;
|
||||
|
|
@ -1242,10 +1253,9 @@ void __pci_bus_size_bridges(struct pci_bus *bus, struct list_head *realloc_head)
|
|||
* the size required to put all 64-bit prefetchable
|
||||
* resources in it.
|
||||
*/
|
||||
b_res = &bus->self->resource[PCI_BRIDGE_RESOURCES];
|
||||
mask = IORESOURCE_MEM;
|
||||
prefmask = IORESOURCE_MEM | IORESOURCE_PREFETCH;
|
||||
if (b_res[2].flags & IORESOURCE_MEM_64) {
|
||||
if (pref && (pref->flags & IORESOURCE_MEM_64)) {
|
||||
prefmask |= IORESOURCE_MEM_64;
|
||||
ret = pbus_size_mem(bus, prefmask, prefmask,
|
||||
prefmask, prefmask,
|
||||
|
|
|
|||
|
|
@ -517,6 +517,7 @@ struct pci_host_bridge {
|
|||
unsigned int native_ltr:1; /* OS may use PCIe LTR */
|
||||
unsigned int native_dpc:1; /* OS may use PCIe DPC */
|
||||
unsigned int preserve_config:1; /* Preserve FW resource setup */
|
||||
unsigned int size_windows:1; /* Enable root bus sizing */
|
||||
|
||||
/* Resource alignment requirements */
|
||||
resource_size_t (*align_resource)(struct pci_dev *dev,
|
||||
|
|
@ -1220,7 +1221,6 @@ int pci_enable_rom(struct pci_dev *pdev);
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|||
void pci_disable_rom(struct pci_dev *pdev);
|
||||
void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size);
|
||||
void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom);
|
||||
void __iomem __must_check *pci_platform_rom(struct pci_dev *pdev, size_t *size);
|
||||
|
||||
/* Power management related routines */
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||||
int pci_save_state(struct pci_dev *dev);
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|
|
|
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