clk: qcom: ipq4019: Add all the frequencies for apss cpu
The APSS CPU clock does not contain all the frequencies in its frequency table so this patch adds the same. Signed-off-by: Abhishek Sahu <absahu@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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Родитель
b52a0c2c11
Коммит
86c654d41a
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@ -568,10 +568,20 @@ static struct clk_rcg2 sdcc1_apps_clk_src = {
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};
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};
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static const struct freq_tbl ftbl_gcc_apps_clk[] = {
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static const struct freq_tbl ftbl_gcc_apps_clk[] = {
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F(48000000, P_XO, 1, 0, 0),
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F(48000000, P_XO, 1, 0, 0),
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F(200000000, P_FEPLL200, 1, 0, 0),
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F(200000000, P_FEPLL200, 1, 0, 0),
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F(384000000, P_DDRPLLAPSS, 1, 0, 0),
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F(413000000, P_DDRPLLAPSS, 1, 0, 0),
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F(448000000, P_DDRPLLAPSS, 1, 0, 0),
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F(488000000, P_DDRPLLAPSS, 1, 0, 0),
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F(500000000, P_FEPLL500, 1, 0, 0),
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F(500000000, P_FEPLL500, 1, 0, 0),
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F(626000000, P_DDRPLLAPSS, 1, 0, 0),
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F(512000000, P_DDRPLLAPSS, 1, 0, 0),
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F(537000000, P_DDRPLLAPSS, 1, 0, 0),
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F(565000000, P_DDRPLLAPSS, 1, 0, 0),
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F(597000000, P_DDRPLLAPSS, 1, 0, 0),
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F(632000000, P_DDRPLLAPSS, 1, 0, 0),
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F(672000000, P_DDRPLLAPSS, 1, 0, 0),
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F(716000000, P_DDRPLLAPSS, 1, 0, 0),
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{ }
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{ }
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};
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};
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