drm/i915: Implement pipe CSC based limited range RGB output
HSW no longer has the PIPECONF bit for limited range RGB output. Instead the pipe CSC unit must be used to perform that task. The CSC pre offset are set to 0, since the incoming data is full [0:255] range RGB, the coefficients are programmed to compress the data into [0:219] range, and then we use either the CSC_MODE black screen offset bit, or the CSC post offsets to shift the data to the correct [16:235] range. Also have to change the confiuration of all planes so that the data is sent through the pipe CSC unit. For simplicity send the plane data through the pipe CSC unit always, and in case full range output is requested, the pipe CSC unit is set up with an identity transform to pass the plane data through unchanged. I've been told by some hardware people that the use of the pipe CSC unit shouldn't result in any measurable increase in power consumption numbers. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
This commit is contained in:
Ville Syrjälä
Daniel Vetter
Родитель
ac4199e0f0
Коммит
86d3efce2c
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@ -2949,6 +2949,7 @@
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#define CURSOR_ENABLE 0x80000000
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#define CURSOR_GAMMA_ENABLE 0x40000000
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#define CURSOR_STRIDE_MASK 0x30000000
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#define CURSOR_PIPE_CSC_ENABLE (1<<24)
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#define CURSOR_FORMAT_SHIFT 24
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#define CURSOR_FORMAT_MASK (0x07 << CURSOR_FORMAT_SHIFT)
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#define CURSOR_FORMAT_2C (0x00 << CURSOR_FORMAT_SHIFT)
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@ -3010,6 +3011,7 @@
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#define DISPPLANE_RGBA888 (0xf<<26)
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#define DISPPLANE_STEREO_ENABLE (1<<25)
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#define DISPPLANE_STEREO_DISABLE 0
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#define DISPPLANE_PIPE_CSC_ENABLE (1<<24)
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#define DISPPLANE_SEL_PIPE_SHIFT 24
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#define DISPPLANE_SEL_PIPE_MASK (3<<DISPPLANE_SEL_PIPE_SHIFT)
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#define DISPPLANE_SEL_PIPE_A 0
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@ -3098,6 +3100,7 @@
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#define DVS_FORMAT_RGBX101010 (1<<25)
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#define DVS_FORMAT_RGBX888 (2<<25)
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#define DVS_FORMAT_RGBX161616 (3<<25)
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#define DVS_PIPE_CSC_ENABLE (1<<24)
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#define DVS_SOURCE_KEY (1<<22)
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#define DVS_RGB_ORDER_XBGR (1<<20)
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#define DVS_YUV_BYTE_ORDER_MASK (3<<16)
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@ -3165,7 +3168,7 @@
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#define SPRITE_FORMAT_RGBX161616 (3<<25)
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#define SPRITE_FORMAT_YUV444 (4<<25)
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#define SPRITE_FORMAT_XR_BGR101010 (5<<25) /* Extended range */
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#define SPRITE_CSC_ENABLE (1<<24)
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#define SPRITE_PIPE_CSC_ENABLE (1<<24)
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#define SPRITE_SOURCE_KEY (1<<22)
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#define SPRITE_RGB_ORDER_RGBX (1<<20) /* only for 888 and 161616 */
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#define SPRITE_YUV_TO_RGB_CSC_DISABLE (1<<19)
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@ -4645,4 +4648,51 @@
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#define WM_DBG_DISALLOW_MAXFIFO (1<<1)
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#define WM_DBG_DISALLOW_SPRITE (1<<2)
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/* pipe CSC */
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#define _PIPE_A_CSC_COEFF_RY_GY 0x49010
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#define _PIPE_A_CSC_COEFF_BY 0x49014
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#define _PIPE_A_CSC_COEFF_RU_GU 0x49018
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#define _PIPE_A_CSC_COEFF_BU 0x4901c
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#define _PIPE_A_CSC_COEFF_RV_GV 0x49020
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#define _PIPE_A_CSC_COEFF_BV 0x49024
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#define _PIPE_A_CSC_MODE 0x49028
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#define _PIPE_A_CSC_PREOFF_HI 0x49030
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#define _PIPE_A_CSC_PREOFF_ME 0x49034
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#define _PIPE_A_CSC_PREOFF_LO 0x49038
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#define _PIPE_A_CSC_POSTOFF_HI 0x49040
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#define _PIPE_A_CSC_POSTOFF_ME 0x49044
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#define _PIPE_A_CSC_POSTOFF_LO 0x49048
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#define _PIPE_B_CSC_COEFF_RY_GY 0x49110
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#define _PIPE_B_CSC_COEFF_BY 0x49114
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#define _PIPE_B_CSC_COEFF_RU_GU 0x49118
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#define _PIPE_B_CSC_COEFF_BU 0x4911c
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#define _PIPE_B_CSC_COEFF_RV_GV 0x49120
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#define _PIPE_B_CSC_COEFF_BV 0x49124
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#define _PIPE_B_CSC_MODE 0x49128
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#define _PIPE_B_CSC_PREOFF_HI 0x49130
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#define _PIPE_B_CSC_PREOFF_ME 0x49134
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#define _PIPE_B_CSC_PREOFF_LO 0x49138
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#define _PIPE_B_CSC_POSTOFF_HI 0x49140
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#define _PIPE_B_CSC_POSTOFF_ME 0x49144
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#define _PIPE_B_CSC_POSTOFF_LO 0x49148
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#define CSC_BLACK_SCREEN_OFFSET (1 << 2)
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#define CSC_POSITION_BEFORE_GAMMA (1 << 1)
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#define CSC_MODE_YUV_TO_RGB (1 << 0)
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#define PIPE_CSC_COEFF_RY_GY(pipe) _PIPE(pipe, _PIPE_A_CSC_COEFF_RY_GY, _PIPE_B_CSC_COEFF_RY_GY)
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#define PIPE_CSC_COEFF_BY(pipe) _PIPE(pipe, _PIPE_A_CSC_COEFF_BY, _PIPE_B_CSC_COEFF_BY)
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#define PIPE_CSC_COEFF_RU_GU(pipe) _PIPE(pipe, _PIPE_A_CSC_COEFF_RU_GU, _PIPE_B_CSC_COEFF_RU_GU)
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#define PIPE_CSC_COEFF_BU(pipe) _PIPE(pipe, _PIPE_A_CSC_COEFF_BU, _PIPE_B_CSC_COEFF_BU)
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#define PIPE_CSC_COEFF_RV_GV(pipe) _PIPE(pipe, _PIPE_A_CSC_COEFF_RV_GV, _PIPE_B_CSC_COEFF_RV_GV)
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#define PIPE_CSC_COEFF_BV(pipe) _PIPE(pipe, _PIPE_A_CSC_COEFF_BV, _PIPE_B_CSC_COEFF_BV)
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#define PIPE_CSC_MODE(pipe) _PIPE(pipe, _PIPE_A_CSC_MODE, _PIPE_B_CSC_MODE)
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#define PIPE_CSC_PREOFF_HI(pipe) _PIPE(pipe, _PIPE_A_CSC_PREOFF_HI, _PIPE_B_CSC_PREOFF_HI)
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#define PIPE_CSC_PREOFF_ME(pipe) _PIPE(pipe, _PIPE_A_CSC_PREOFF_ME, _PIPE_B_CSC_PREOFF_ME)
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#define PIPE_CSC_PREOFF_LO(pipe) _PIPE(pipe, _PIPE_A_CSC_PREOFF_LO, _PIPE_B_CSC_PREOFF_LO)
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#define PIPE_CSC_POSTOFF_HI(pipe) _PIPE(pipe, _PIPE_A_CSC_POSTOFF_HI, _PIPE_B_CSC_POSTOFF_HI)
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#define PIPE_CSC_POSTOFF_ME(pipe) _PIPE(pipe, _PIPE_A_CSC_POSTOFF_ME, _PIPE_B_CSC_POSTOFF_ME)
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#define PIPE_CSC_POSTOFF_LO(pipe) _PIPE(pipe, _PIPE_A_CSC_POSTOFF_LO, _PIPE_B_CSC_POSTOFF_LO)
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#endif /* _I915_REG_H_ */
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@ -5126,6 +5126,71 @@ static void ironlake_set_pipeconf(struct drm_crtc *crtc,
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POSTING_READ(PIPECONF(pipe));
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}
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/*
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* Set up the pipe CSC unit.
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*
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* Currently only full range RGB to limited range RGB conversion
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* is supported, but eventually this should handle various
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* RGB<->YCbCr scenarios as well.
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*/
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static void intel_set_pipe_csc(struct drm_crtc *crtc,
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const struct drm_display_mode *adjusted_mode)
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{
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struct drm_device *dev = crtc->dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
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int pipe = intel_crtc->pipe;
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uint16_t coeff = 0x7800; /* 1.0 */
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/*
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* TODO: Check what kind of values actually come out of the pipe
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* with these coeff/postoff values and adjust to get the best
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* accuracy. Perhaps we even need to take the bpc value into
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* consideration.
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*/
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if (adjusted_mode->private_flags & INTEL_MODE_LIMITED_COLOR_RANGE)
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coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
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/*
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* GY/GU and RY/RU should be the other way around according
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* to BSpec, but reality doesn't agree. Just set them up in
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* a way that results in the correct picture.
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*/
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I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
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I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
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I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
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I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
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I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
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I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
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I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
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I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
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I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
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if (INTEL_INFO(dev)->gen > 6) {
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uint16_t postoff = 0;
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if (adjusted_mode->private_flags & INTEL_MODE_LIMITED_COLOR_RANGE)
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postoff = (16 * (1 << 13) / 255) & 0x1fff;
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I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
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I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
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I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
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I915_WRITE(PIPE_CSC_MODE(pipe), 0);
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} else {
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uint32_t mode = CSC_MODE_YUV_TO_RGB;
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if (adjusted_mode->private_flags & INTEL_MODE_LIMITED_COLOR_RANGE)
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mode |= CSC_BLACK_SCREEN_OFFSET;
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I915_WRITE(PIPE_CSC_MODE(pipe), mode);
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}
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}
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static void haswell_set_pipeconf(struct drm_crtc *crtc,
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struct drm_display_mode *adjusted_mode,
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bool dither)
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@ -5714,8 +5779,10 @@ static int haswell_crtc_mode_set(struct drm_crtc *crtc,
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haswell_set_pipeconf(crtc, adjusted_mode, dither);
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intel_set_pipe_csc(crtc, adjusted_mode);
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/* Set up the display plane register */
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I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
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I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
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POSTING_READ(DSPCNTR(plane));
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ret = intel_pipe_set_base(crtc, x, y, fb);
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@ -6120,6 +6187,8 @@ static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
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cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
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cntl |= CURSOR_MODE_DISABLE;
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}
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if (IS_HASWELL(dev))
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cntl |= CURSOR_PIPE_CSC_ENABLE;
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I915_WRITE(CURCNTR_IVB(pipe), cntl);
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intel_crtc->cursor_visible = visible;
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@ -90,6 +90,9 @@ ivb_update_plane(struct drm_plane *plane, struct drm_framebuffer *fb,
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sprctl |= SPRITE_TRICKLE_FEED_DISABLE;
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sprctl |= SPRITE_ENABLE;
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if (IS_HASWELL(dev))
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sprctl |= SPRITE_PIPE_CSC_ENABLE;
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/* Sizes are 0 based */
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src_w--;
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src_h--;
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