arm64: dts: qcom: msm8996: Pad addresses
Pad all addresses in msm8996.dtsi to 8 digits, in order to make it easier to ensure ordering when adding new nodes. Acked-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
This commit is contained in:
Bjorn Andersson
Родитель
88264f1f6b
Коммит
86f6d6225e
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@ -520,7 +520,7 @@
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rpm_msg_ram: memory@68000 {
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compatible = "qcom,rpm-msg-ram";
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reg = <0x68000 0x6000>;
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reg = <0x00068000 0x6000>;
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};
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rng: rng@83000 {
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@ -532,13 +532,13 @@
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tcsr_mutex_regs: syscon@740000 {
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compatible = "syscon";
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reg = <0x740000 0x20000>;
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reg = <0x00740000 0x20000>;
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};
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tsens0: thermal-sensor@4a9000 {
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compatible = "qcom,msm8996-tsens";
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reg = <0x4a9000 0x1000>, /* TM */
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<0x4a8000 0x1000>; /* SROT */
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reg = <0x004a9000 0x1000>, /* TM */
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<0x004a8000 0x1000>; /* SROT */
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#qcom,sensors = <13>;
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interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "uplow";
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@ -547,8 +547,8 @@
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tsens1: thermal-sensor@4ad000 {
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compatible = "qcom,msm8996-tsens";
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reg = <0x4ad000 0x1000>, /* TM */
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<0x4ac000 0x1000>; /* SROT */
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reg = <0x004ad000 0x1000>, /* TM */
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<0x004ac000 0x1000>; /* SROT */
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#qcom,sensors = <8>;
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interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "uplow";
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@ -557,7 +557,7 @@
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tcsr: syscon@7a0000 {
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compatible = "qcom,tcsr-msm8996", "syscon";
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reg = <0x7a0000 0x18000>;
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reg = <0x007a0000 0x18000>;
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};
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intc: interrupt-controller@9bc0000 {
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@ -573,7 +573,7 @@
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apcs_glb: mailbox@9820000 {
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compatible = "qcom,msm8996-apcs-hmss-global";
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reg = <0x9820000 0x1000>;
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reg = <0x09820000 0x1000>;
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#mbox-cells = <1>;
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};
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@ -583,7 +583,7 @@
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#clock-cells = <1>;
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#reset-cells = <1>;
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#power-domain-cells = <1>;
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reg = <0x300000 0x90000>;
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reg = <0x00300000 0x90000>;
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};
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stm@3002000 {
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@ -1056,7 +1056,7 @@
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kryocc: clock-controller@6400000 {
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compatible = "qcom,apcc-msm8996";
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reg = <0x6400000 0x90000>;
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reg = <0x06400000 0x90000>;
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#clock-cells = <1>;
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};
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@ -1102,7 +1102,7 @@
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blsp2_uart1: serial@75b0000 {
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compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
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reg = <0x75b0000 0x1000>;
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reg = <0x075b0000 0x1000>;
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interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>,
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<&gcc GCC_BLSP2_AHB_CLK>;
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@ -1168,7 +1168,7 @@
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sdhc2: sdhci@74a4900 {
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status = "disabled";
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compatible = "qcom,sdhci-msm-v4";
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reg = <0x74a4900 0x314>, <0x74a4000 0x800>;
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reg = <0x074a4900 0x314>, <0x074a4000 0x800>;
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reg-names = "hc_mem", "core_mem";
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interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>,
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@ -1253,11 +1253,11 @@
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spmi_bus: qcom,spmi@400f000 {
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compatible = "qcom,spmi-pmic-arb";
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reg = <0x400f000 0x1000>,
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<0x4400000 0x800000>,
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<0x4c00000 0x800000>,
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<0x5800000 0x200000>,
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<0x400a000 0x002100>;
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reg = <0x0400f000 0x1000>,
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<0x04400000 0x800000>,
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<0x04c00000 0x800000>,
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<0x05800000 0x200000>,
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<0x0400a000 0x002100>;
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reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
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interrupt-names = "periph_irq";
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interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>;
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@ -1271,7 +1271,7 @@
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ufsphy: phy@627000 {
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compatible = "qcom,msm8996-ufs-phy-qmp-14nm";
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reg = <0x627000 0xda8>;
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reg = <0x00627000 0xda8>;
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reg-names = "phy_mem";
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#phy-cells = <0>;
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@ -1284,7 +1284,7 @@
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ufshc: ufshc@624000 {
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compatible = "qcom,ufshc";
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reg = <0x624000 0x2500>;
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reg = <0x00624000 0x2500>;
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interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
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phys = <&ufsphy>;
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@ -1343,7 +1343,7 @@
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#clock-cells = <1>;
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#reset-cells = <1>;
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#power-domain-cells = <1>;
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reg = <0x8c0000 0x40000>;
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reg = <0x008c0000 0x40000>;
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assigned-clocks = <&mmcc MMPLL9_PLL>,
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<&mmcc MMPLL1_PLL>,
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<&mmcc MMPLL3_PLL>,
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@ -1358,7 +1358,7 @@
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qfprom@74000 {
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compatible = "qcom,qfprom";
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reg = <0x74000 0x8ff>;
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reg = <0x00074000 0x8ff>;
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#address-cells = <1>;
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#size-cells = <1>;
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@ -1380,7 +1380,7 @@
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pcie_phy: phy@34000 {
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compatible = "qcom,msm8996-qmp-pcie-phy";
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reg = <0x34000 0x488>;
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reg = <0x00034000 0x488>;
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#clock-cells = <1>;
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#address-cells = <1>;
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#size-cells = <1>;
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@ -1398,9 +1398,9 @@
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status = "disabled";
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pciephy_0: lane@35000 {
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reg = <0x035000 0x130>,
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<0x035200 0x200>,
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<0x035400 0x1dc>;
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reg = <0x00035000 0x130>,
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<0x00035200 0x200>,
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<0x00035400 0x1dc>;
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#phy-cells = <0>;
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clock-output-names = "pcie_0_pipe_clk_src";
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@ -1411,9 +1411,9 @@
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};
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pciephy_1: lane@36000 {
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reg = <0x036000 0x130>,
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<0x036200 0x200>,
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<0x036400 0x1dc>;
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reg = <0x00036000 0x130>,
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<0x00036200 0x200>,
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<0x00036400 0x1dc>;
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#phy-cells = <0>;
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clock-output-names = "pcie_1_pipe_clk_src";
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@ -1424,9 +1424,9 @@
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};
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pciephy_2: lane@37000 {
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reg = <0x037000 0x130>,
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<0x037200 0x200>,
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<0x037400 0x1dc>;
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reg = <0x00037000 0x130>,
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<0x00037200 0x200>,
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<0x00037400 0x1dc>;
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#phy-cells = <0>;
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clock-output-names = "pcie_2_pipe_clk_src";
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@ -1439,7 +1439,7 @@
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usb3phy: phy@7410000 {
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compatible = "qcom,msm8996-qmp-usb3-phy";
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reg = <0x7410000 0x1c4>;
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reg = <0x07410000 0x1c4>;
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#clock-cells = <1>;
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#address-cells = <1>;
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#size-cells = <1>;
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@ -1456,9 +1456,9 @@
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status = "disabled";
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ssusb_phy_0: lane@7410200 {
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reg = <0x7410200 0x200>,
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<0x7410400 0x130>,
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<0x7410600 0x1a8>;
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reg = <0x07410200 0x200>,
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<0x07410400 0x130>,
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<0x07410600 0x1a8>;
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#phy-cells = <0>;
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clock-output-names = "usb3_phy_pipe_clk_src";
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@ -1469,7 +1469,7 @@
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hsusb_phy1: phy@7411000 {
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compatible = "qcom,msm8996-qusb2-phy";
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reg = <0x7411000 0x180>;
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reg = <0x07411000 0x180>;
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#phy-cells = <0>;
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clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
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@ -1483,7 +1483,7 @@
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hsusb_phy2: phy@7412000 {
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compatible = "qcom,msm8996-qusb2-phy";
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reg = <0x7412000 0x180>;
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reg = <0x07412000 0x180>;
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#phy-cells = <0>;
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clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
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@ -1497,7 +1497,7 @@
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usb2: usb@76f8800 {
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compatible = "qcom,msm8996-dwc3", "qcom,dwc3";
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reg = <0x76f8800 0x400>;
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reg = <0x076f8800 0x400>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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@ -1517,7 +1517,7 @@
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dwc3@7600000 {
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compatible = "snps,dwc3";
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reg = <0x7600000 0xcc00>;
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reg = <0x07600000 0xcc00>;
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interrupts = <0 138 IRQ_TYPE_LEVEL_HIGH>;
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phys = <&hsusb_phy2>;
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phy-names = "usb2-phy";
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@ -1528,7 +1528,7 @@
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usb3: usb@6af8800 {
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compatible = "qcom,msm8996-dwc3", "qcom,dwc3";
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reg = <0x6af8800 0x400>;
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reg = <0x06af8800 0x400>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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@ -1549,7 +1549,7 @@
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dwc3@6a00000 {
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compatible = "snps,dwc3";
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reg = <0x6a00000 0xcc00>;
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reg = <0x06a00000 0xcc00>;
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interrupts = <0 131 IRQ_TYPE_LEVEL_HIGH>;
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phys = <&hsusb_phy1>, <&ssusb_phy_0>;
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phy-names = "usb2-phy", "usb3-phy";
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@ -1560,7 +1560,7 @@
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vfe_smmu: iommu@da0000 {
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compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
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reg = <0xda0000 0x10000>;
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reg = <0x00da0000 0x10000>;
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#global-interrupts = <1>;
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interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
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@ -1576,20 +1576,20 @@
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camss: camss@a00000 {
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compatible = "qcom,msm8996-camss";
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reg = <0xa34000 0x1000>,
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<0xa00030 0x4>,
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<0xa35000 0x1000>,
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<0xa00038 0x4>,
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<0xa36000 0x1000>,
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<0xa00040 0x4>,
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<0xa30000 0x100>,
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<0xa30400 0x100>,
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<0xa30800 0x100>,
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<0xa30c00 0x100>,
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<0xa31000 0x500>,
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<0xa00020 0x10>,
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<0xa10000 0x1000>,
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<0xa14000 0x1000>;
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reg = <0x00a34000 0x1000>,
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<0x00a00030 0x4>,
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<0x00a35000 0x1000>,
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<0x00a00038 0x4>,
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<0x00a36000 0x1000>,
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<0x00a00040 0x4>,
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<0x00a30000 0x100>,
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<0x00a30400 0x100>,
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<0x00a30800 0x100>,
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<0x00a30c00 0x100>,
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<0x00a31000 0x500>,
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<0x00a00020 0x10>,
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<0x00a10000 0x1000>,
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<0x00a14000 0x1000>;
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reg-names = "csiphy0",
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"csiphy0_clk_mux",
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"csiphy1",
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@ -1710,7 +1710,7 @@
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adreno_smmu: iommu@b40000 {
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compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
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reg = <0xb40000 0x10000>;
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reg = <0x00b40000 0x10000>;
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#global-interrupts = <1>;
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interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
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@ -1727,7 +1727,7 @@
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mdp_smmu: iommu@d00000 {
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compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
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reg = <0xd00000 0x10000>;
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reg = <0x00d00000 0x10000>;
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#global-interrupts = <1>;
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interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
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@ -1743,7 +1743,7 @@
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lpass_q6_smmu: iommu@1600000 {
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compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
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reg = <0x1600000 0x20000>;
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reg = <0x01600000 0x20000>;
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#iommu-cells = <1>;
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power-domains = <&gcc HLOS1_VOTE_LPASS_CORE_GDSC>;
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@ -1930,7 +1930,7 @@
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{
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compatible = "qcom,bam-v1.7.0";
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qcom,controlled-remotely;
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reg = <0x9184000 0x32000>;
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reg = <0x09184000 0x32000>;
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num-channels = <31>;
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interrupts = <0 164 IRQ_TYPE_LEVEL_HIGH>;
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#dma-cells = <1>;
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@ -1940,7 +1940,7 @@
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slim_msm: slim@91c0000 {
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compatible = "qcom,slim-ngd-v1.5.0";
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reg = <0x91c0000 0x2C000>;
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reg = <0x091c0000 0x2C000>;
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reg-names = "ctrl";
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interrupts = <0 163 IRQ_TYPE_LEVEL_HIGH>;
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dmas = <&slimbam 3>, <&slimbam 4>,
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@ -1984,7 +1984,7 @@
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compatible = "qcom,adreno-530.2", "qcom,adreno";
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#stream-id-cells = <16>;
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reg = <0xb00000 0x3f000>;
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reg = <0x00b00000 0x3f000>;
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reg-names = "kgsl_3d0_reg_memory";
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interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>;
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@ -2058,9 +2058,9 @@
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mdss: mdss@900000 {
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compatible = "qcom,mdss";
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reg = <0x900000 0x1000>,
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<0x9b0000 0x1040>,
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<0x9b8000 0x1040>;
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reg = <0x00900000 0x1000>,
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<0x009b0000 0x1040>,
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<0x009b8000 0x1040>;
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reg-names = "mdss_phys",
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"vbif_phys",
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"vbif_nrt_phys";
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@ -2080,7 +2080,7 @@
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mdp: mdp@901000 {
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compatible = "qcom,mdp5";
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reg = <0x901000 0x90000>;
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reg = <0x00901000 0x90000>;
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reg-names = "mdp_phys";
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interrupt-parent = <&mdss>;
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@ -2156,12 +2156,12 @@
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hdmi_phy: hdmi-phy@9a0600 {
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#phy-cells = <0>;
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compatible = "qcom,hdmi-phy-8996";
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reg = <0x9a0600 0x1c4>,
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<0x9a0a00 0x124>,
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<0x9a0c00 0x124>,
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<0x9a0e00 0x124>,
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<0x9a1000 0x124>,
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<0x9a1200 0x0c8>;
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reg = <0x009a0600 0x1c4>,
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<0x009a0a00 0x124>,
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<0x009a0c00 0x124>,
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||||
<0x009a0e00 0x124>,
|
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<0x009a1000 0x124>,
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<0x009a1200 0x0c8>;
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reg-names = "hdmi_pll",
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"hdmi_tx_l0",
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"hdmi_tx_l1",
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