ASoC: zx-tdm: add zte's tdm controller driver
This patch adds tdm controller driver for zte's SoC family. Signed-off-by: Baoyou Xie <baoyou.xie@linaro.org> Reviewed-by: Shawn Guo <shawnguo@kernel.org> Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Baoyou Xie
Mark Brown
Родитель
5949dae3a4
Коммит
870e0ddc43
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@ -15,3 +15,11 @@ config ZX_I2S
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help
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Say Y or M if you want to add support for codecs attached to the
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ZTE ZX I2S interface
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config ZX_TDM
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tristate "ZTE ZX TDM Driver Support"
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depends on COMMON_CLK
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select SND_SOC_GENERIC_DMAENGINE_PCM
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help
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Say Y or M if you want to add support for codecs attached to the
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ZTE ZX TDM interface
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@ -1,2 +1,3 @@
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obj-$(CONFIG_ZX_SPDIF) += zx-spdif.o
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obj-$(CONFIG_ZX_I2S) += zx-i2s.o
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obj-$(CONFIG_ZX_TDM) += zx-tdm.o
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@ -0,0 +1,461 @@
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/*
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* ZTE's TDM driver
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*
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* Copyright (C) 2017 ZTE Ltd
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*
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* Author: Baoyou Xie <baoyou.xie@linaro.org>
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*
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* License terms: GNU General Public License (GPL) version 2
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*/
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#include <linux/clk.h>
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#include <linux/io.h>
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#include <linux/mfd/syscon.h>
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#include <linux/module.h>
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#include <sound/dmaengine_pcm.h>
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#include <sound/pcm_params.h>
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#include <sound/soc.h>
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#include <sound/soc-dai.h>
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#define REG_TIMING_CTRL 0x04
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#define REG_TX_FIFO_CTRL 0x0C
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#define REG_RX_FIFO_CTRL 0x10
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#define REG_INT_EN 0x1C
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#define REG_INT_STATUS 0x20
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#define REG_DATABUF 0x24
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#define REG_TS_MASK0 0x44
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#define REG_PROCESS_CTRL 0x54
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#define FIFO_CTRL_TX_RST BIT(0)
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#define FIFO_CTRL_RX_RST BIT(0)
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#define DEAGULT_FIFO_THRES GENMASK(4, 2)
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#define FIFO_CTRL_TX_DMA_EN BIT(1)
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#define FIFO_CTRL_RX_DMA_EN BIT(1)
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#define TX_FIFO_RST_MASK BIT(0)
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#define RX_FIFO_RST_MASK BIT(0)
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#define FIFOCTRL_TX_FIFO_RST BIT(0)
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#define FIFOCTRL_RX_FIFO_RST BIT(0)
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#define TXTH_MASK GENMASK(5, 2)
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#define RXTH_MASK GENMASK(5, 2)
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#define FIFOCTRL_THRESHOLD(x) ((x) << 2)
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#define TIMING_MS_MASK BIT(1)
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/*
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* 00: 8 clk cycles every timeslot
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* 01: 16 clk cycles every timeslot
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* 10: 32 clk cycles every timeslot
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*/
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#define TIMING_SYNC_WIDTH_MASK GENMASK(6, 5)
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#define TIMING_WIDTH_SHIFT 5
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#define TIMING_DEFAULT_WIDTH 0
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#define TIMING_TS_WIDTH(x) ((x) << TIMING_WIDTH_SHIFT)
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#define TIMING_WIDTH_FACTOR 8
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#define TIMING_MASTER_MODE BIT(21)
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#define TIMING_LSB_FIRST BIT(20)
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#define TIMING_TS_NUM(x) (((x) - 1) << 7)
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#define TIMING_CLK_SEL_MASK GENMASK(2, 0)
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#define TIMING_CLK_SEL_DEF BIT(2)
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#define PROCESS_TX_EN BIT(0)
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#define PROCESS_RX_EN BIT(1)
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#define PROCESS_TDM_EN BIT(2)
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#define PROCESS_DISABLE_ALL 0
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#define INT_DISABLE_ALL 0
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#define INT_STATUS_MASK GENMASK(6, 0)
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struct zx_tdm_info {
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struct snd_dmaengine_dai_dma_data dma_playback;
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struct snd_dmaengine_dai_dma_data dma_capture;
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resource_size_t phy_addr;
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void __iomem *regbase;
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struct clk *dai_wclk;
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struct clk *dai_pclk;
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int master;
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struct device *dev;
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};
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static inline u32 zx_tdm_readl(struct zx_tdm_info *tdm, u16 reg)
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{
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return readl_relaxed(tdm->regbase + reg);
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}
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static inline void zx_tdm_writel(struct zx_tdm_info *tdm, u16 reg, u32 val)
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{
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writel_relaxed(val, tdm->regbase + reg);
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}
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static void zx_tdm_tx_en(struct zx_tdm_info *tdm, bool on)
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{
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unsigned long val;
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val = zx_tdm_readl(tdm, REG_PROCESS_CTRL);
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if (on)
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val |= PROCESS_TX_EN | PROCESS_TDM_EN;
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else
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val &= ~(PROCESS_TX_EN | PROCESS_TDM_EN);
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zx_tdm_writel(tdm, REG_PROCESS_CTRL, val);
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}
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static void zx_tdm_rx_en(struct zx_tdm_info *tdm, bool on)
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{
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unsigned long val;
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val = zx_tdm_readl(tdm, REG_PROCESS_CTRL);
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if (on)
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val |= PROCESS_RX_EN | PROCESS_TDM_EN;
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else
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val &= ~(PROCESS_RX_EN | PROCESS_TDM_EN);
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zx_tdm_writel(tdm, REG_PROCESS_CTRL, val);
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}
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static void zx_tdm_tx_dma_en(struct zx_tdm_info *tdm, bool on)
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{
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unsigned long val;
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val = zx_tdm_readl(tdm, REG_TX_FIFO_CTRL);
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val |= FIFO_CTRL_TX_RST | DEAGULT_FIFO_THRES;
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if (on)
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val |= FIFO_CTRL_TX_DMA_EN;
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else
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val &= ~FIFO_CTRL_TX_DMA_EN;
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zx_tdm_writel(tdm, REG_TX_FIFO_CTRL, val);
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}
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static void zx_tdm_rx_dma_en(struct zx_tdm_info *tdm, bool on)
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{
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unsigned long val;
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val = zx_tdm_readl(tdm, REG_RX_FIFO_CTRL);
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val |= FIFO_CTRL_RX_RST | DEAGULT_FIFO_THRES;
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if (on)
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val |= FIFO_CTRL_RX_DMA_EN;
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else
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val &= ~FIFO_CTRL_RX_DMA_EN;
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zx_tdm_writel(tdm, REG_RX_FIFO_CTRL, val);
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}
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#define ZX_TDM_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000)
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#define ZX_TDM_FMTBIT \
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(SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FORMAT_MU_LAW | \
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SNDRV_PCM_FORMAT_A_LAW)
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static int zx_tdm_dai_probe(struct snd_soc_dai *dai)
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{
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struct zx_tdm_info *zx_tdm = dev_get_drvdata(dai->dev);
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snd_soc_dai_set_drvdata(dai, zx_tdm);
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zx_tdm->dma_playback.addr = zx_tdm->phy_addr + REG_DATABUF;
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zx_tdm->dma_playback.maxburst = 16;
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zx_tdm->dma_capture.addr = zx_tdm->phy_addr + REG_DATABUF;
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zx_tdm->dma_capture.maxburst = 16;
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snd_soc_dai_init_dma_data(dai, &zx_tdm->dma_playback,
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&zx_tdm->dma_capture);
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return 0;
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}
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static int zx_tdm_set_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt)
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{
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struct zx_tdm_info *tdm = snd_soc_dai_get_drvdata(cpu_dai);
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unsigned long val;
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val = zx_tdm_readl(tdm, REG_TIMING_CTRL);
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val &= ~(TIMING_SYNC_WIDTH_MASK | TIMING_MS_MASK);
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val |= TIMING_DEFAULT_WIDTH << TIMING_WIDTH_SHIFT;
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switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
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case SND_SOC_DAIFMT_CBM_CFM:
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tdm->master = 1;
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val |= TIMING_MASTER_MODE;
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break;
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case SND_SOC_DAIFMT_CBS_CFS:
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tdm->master = 0;
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val &= ~TIMING_MASTER_MODE;
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break;
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default:
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dev_err(cpu_dai->dev, "Unknown master/slave format\n");
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return -EINVAL;
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}
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zx_tdm_writel(tdm, REG_TIMING_CTRL, val);
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return 0;
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}
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static int zx_tdm_hw_params(struct snd_pcm_substream *substream,
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struct snd_pcm_hw_params *params,
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struct snd_soc_dai *socdai)
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{
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struct zx_tdm_info *tdm = snd_soc_dai_get_drvdata(socdai);
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struct snd_dmaengine_dai_dma_data *dma_data;
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unsigned int ts_width = TIMING_DEFAULT_WIDTH;
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unsigned int ch_num = 32;
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unsigned int mask = 0;
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unsigned int ret = 0;
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unsigned long val;
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dma_data = snd_soc_dai_get_dma_data(socdai, substream);
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dma_data->addr_width = ch_num >> 3;
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switch (params_format(params)) {
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case SNDRV_PCM_FORMAT_MU_LAW:
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case SNDRV_PCM_FORMAT_A_LAW:
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case SNDRV_PCM_FORMAT_S16_LE:
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ts_width = 1;
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break;
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default:
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ts_width = 0;
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dev_err(socdai->dev, "Unknown data format\n");
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return -EINVAL;
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}
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val = zx_tdm_readl(tdm, REG_TIMING_CTRL);
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val |= TIMING_TS_WIDTH(ts_width) | TIMING_TS_NUM(1);
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zx_tdm_writel(tdm, REG_TIMING_CTRL, val);
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zx_tdm_writel(tdm, REG_TS_MASK0, mask);
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if (tdm->master)
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ret = clk_set_rate(tdm->dai_wclk,
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params_rate(params) * TIMING_WIDTH_FACTOR * ch_num);
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return ret;
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}
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static int zx_tdm_trigger(struct snd_pcm_substream *substream, int cmd,
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struct snd_soc_dai *dai)
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{
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int capture = (substream->stream == SNDRV_PCM_STREAM_CAPTURE);
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struct zx_tdm_info *zx_tdm = dev_get_drvdata(dai->dev);
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unsigned int val;
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int ret = 0;
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switch (cmd) {
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case SNDRV_PCM_TRIGGER_START:
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if (capture) {
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val = zx_tdm_readl(zx_tdm, REG_RX_FIFO_CTRL);
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val |= FIFOCTRL_RX_FIFO_RST;
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zx_tdm_writel(zx_tdm, REG_RX_FIFO_CTRL, val);
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zx_tdm_rx_dma_en(zx_tdm, true);
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} else {
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val = zx_tdm_readl(zx_tdm, REG_TX_FIFO_CTRL);
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val |= FIFOCTRL_TX_FIFO_RST;
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zx_tdm_writel(zx_tdm, REG_TX_FIFO_CTRL, val);
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zx_tdm_tx_dma_en(zx_tdm, true);
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}
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break;
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case SNDRV_PCM_TRIGGER_RESUME:
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case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
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if (capture)
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zx_tdm_rx_en(zx_tdm, true);
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else
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zx_tdm_tx_en(zx_tdm, true);
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break;
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case SNDRV_PCM_TRIGGER_STOP:
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if (capture)
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zx_tdm_rx_dma_en(zx_tdm, false);
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else
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zx_tdm_tx_dma_en(zx_tdm, false);
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break;
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case SNDRV_PCM_TRIGGER_SUSPEND:
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case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
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if (capture)
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zx_tdm_rx_en(zx_tdm, false);
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else
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zx_tdm_tx_en(zx_tdm, false);
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break;
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default:
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ret = -EINVAL;
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break;
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}
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return ret;
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}
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static int zx_tdm_startup(struct snd_pcm_substream *substream,
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struct snd_soc_dai *dai)
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{
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struct zx_tdm_info *zx_tdm = dev_get_drvdata(dai->dev);
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int ret;
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ret = clk_prepare_enable(zx_tdm->dai_wclk);
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if (ret)
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return ret;
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ret = clk_prepare_enable(zx_tdm->dai_pclk);
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if (ret) {
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clk_disable_unprepare(zx_tdm->dai_wclk);
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return ret;
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}
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return 0;
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}
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static void zx_tdm_shutdown(struct snd_pcm_substream *substream,
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struct snd_soc_dai *dai)
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{
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struct zx_tdm_info *zx_tdm = dev_get_drvdata(dai->dev);
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clk_disable_unprepare(zx_tdm->dai_pclk);
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clk_disable_unprepare(zx_tdm->dai_wclk);
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}
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static struct snd_soc_dai_ops zx_tdm_dai_ops = {
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.trigger = zx_tdm_trigger,
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.hw_params = zx_tdm_hw_params,
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.set_fmt = zx_tdm_set_fmt,
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.startup = zx_tdm_startup,
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.shutdown = zx_tdm_shutdown,
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};
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static const struct snd_soc_component_driver zx_tdm_component = {
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.name = "zx-tdm",
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};
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static void zx_tdm_init_state(struct zx_tdm_info *tdm)
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{
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unsigned int val;
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zx_tdm_writel(tdm, REG_PROCESS_CTRL, PROCESS_DISABLE_ALL);
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val = zx_tdm_readl(tdm, REG_TIMING_CTRL);
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val |= TIMING_LSB_FIRST;
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val &= ~TIMING_CLK_SEL_MASK;
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val |= TIMING_CLK_SEL_DEF;
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zx_tdm_writel(tdm, REG_TIMING_CTRL, val);
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zx_tdm_writel(tdm, REG_INT_EN, INT_DISABLE_ALL);
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/*
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* write INT_STATUS register to clear it.
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*/
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zx_tdm_writel(tdm, REG_INT_STATUS, INT_STATUS_MASK);
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zx_tdm_writel(tdm, REG_RX_FIFO_CTRL, FIFOCTRL_RX_FIFO_RST);
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zx_tdm_writel(tdm, REG_TX_FIFO_CTRL, FIFOCTRL_TX_FIFO_RST);
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val = zx_tdm_readl(tdm, REG_RX_FIFO_CTRL);
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val &= ~(RXTH_MASK | RX_FIFO_RST_MASK);
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val |= FIFOCTRL_THRESHOLD(8);
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zx_tdm_writel(tdm, REG_RX_FIFO_CTRL, val);
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val = zx_tdm_readl(tdm, REG_TX_FIFO_CTRL);
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val &= ~(TXTH_MASK | TX_FIFO_RST_MASK);
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val |= FIFOCTRL_THRESHOLD(8);
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zx_tdm_writel(tdm, REG_TX_FIFO_CTRL, val);
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}
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static struct snd_soc_dai_driver zx_tdm_dai = {
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.name = "zx-tdm-dai",
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.id = 0,
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.probe = zx_tdm_dai_probe,
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.playback = {
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.channels_min = 1,
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.channels_max = 4,
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.rates = ZX_TDM_RATES,
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.formats = ZX_TDM_FMTBIT,
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},
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.capture = {
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.channels_min = 1,
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.channels_max = 4,
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.rates = ZX_TDM_RATES,
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.formats = ZX_TDM_FMTBIT,
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},
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.ops = &zx_tdm_dai_ops,
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};
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static int zx_tdm_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct of_phandle_args out_args;
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unsigned int dma_reg_offset;
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struct zx_tdm_info *zx_tdm;
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unsigned int dma_mask;
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struct resource *res;
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struct regmap *regmap_sysctrl;
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int ret;
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zx_tdm = devm_kzalloc(&pdev->dev, sizeof(*zx_tdm), GFP_KERNEL);
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if (!zx_tdm)
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return -ENOMEM;
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zx_tdm->dev = dev;
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zx_tdm->dai_wclk = devm_clk_get(&pdev->dev, "wclk");
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if (IS_ERR(zx_tdm->dai_wclk)) {
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dev_err(&pdev->dev, "Fail to get wclk\n");
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return PTR_ERR(zx_tdm->dai_wclk);
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}
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zx_tdm->dai_pclk = devm_clk_get(&pdev->dev, "pclk");
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if (IS_ERR(zx_tdm->dai_pclk)) {
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dev_err(&pdev->dev, "Fail to get pclk\n");
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return PTR_ERR(zx_tdm->dai_pclk);
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}
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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zx_tdm->phy_addr = res->start;
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zx_tdm->regbase = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(zx_tdm->regbase))
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return PTR_ERR(zx_tdm->regbase);
|
||||
|
||||
ret = of_parse_phandle_with_fixed_args(pdev->dev.of_node,
|
||||
"zte,tdm-dma-sysctrl", 2, 0, &out_args);
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev, "Fail to get zte,tdm-dma-sysctrl\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
dma_reg_offset = out_args.args[0];
|
||||
dma_mask = out_args.args[1];
|
||||
regmap_sysctrl = syscon_node_to_regmap(out_args.np);
|
||||
if (IS_ERR(regmap_sysctrl)) {
|
||||
of_node_put(out_args.np);
|
||||
return PTR_ERR(regmap_sysctrl);
|
||||
}
|
||||
|
||||
regmap_update_bits(regmap_sysctrl, dma_reg_offset, dma_mask, dma_mask);
|
||||
of_node_put(out_args.np);
|
||||
|
||||
zx_tdm_init_state(zx_tdm);
|
||||
platform_set_drvdata(pdev, zx_tdm);
|
||||
|
||||
ret = devm_snd_soc_register_component(&pdev->dev, &zx_tdm_component,
|
||||
&zx_tdm_dai, 1);
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev, "Register DAI failed: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
|
||||
if (ret)
|
||||
dev_err(&pdev->dev, "Register platform PCM failed: %d\n", ret);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static const struct of_device_id zx_tdm_dt_ids[] = {
|
||||
{ .compatible = "zte,zx296718-tdm", },
|
||||
{}
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, zx_tdm_dt_ids);
|
||||
|
||||
static struct platform_driver tdm_driver = {
|
||||
.probe = zx_tdm_probe,
|
||||
.driver = {
|
||||
.name = "zx-tdm",
|
||||
.of_match_table = zx_tdm_dt_ids,
|
||||
},
|
||||
};
|
||||
module_platform_driver(tdm_driver);
|
||||
|
||||
MODULE_AUTHOR("Baoyou Xie <baoyou.xie@linaro.org>");
|
||||
MODULE_DESCRIPTION("ZTE TDM DAI driver");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
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