drm/tegra: Add falcon helper library
Add a set of falcon helper routines for use by the tegradrm client drivers of the various falcon-based engines. The falcon is a microcontroller that acts as a frontend for the rest of a particular Tegra engine. In order to properly utilize these engines, the frontend must be booted before pushing any commands. Based on work by Andrew Chew <achew@nvidia.com> Signed-off-by: Andrew Chew <achew@nvidia.com> Signed-off-by: Arto Merilainen <amerilainen@nvidia.com> Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
This commit is contained in:
Arto Merilainen
Thierry Reding
Родитель
ad92601521
Коммит
8746f6593d
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@ -13,6 +13,7 @@ tegra-drm-y := \
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sor.o \
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dpaux.o \
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gr2d.o \
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gr3d.o
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gr3d.o \
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falcon.o
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obj-$(CONFIG_DRM_TEGRA) += tegra-drm.o
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@ -0,0 +1,259 @@
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/*
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* Copyright (c) 2015, NVIDIA Corporation.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/platform_device.h>
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#include <linux/dma-mapping.h>
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#include <linux/firmware.h>
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#include <linux/pci_ids.h>
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#include <linux/iopoll.h>
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#include "falcon.h"
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#include "drm.h"
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enum falcon_memory {
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FALCON_MEMORY_IMEM,
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FALCON_MEMORY_DATA,
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};
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static void falcon_writel(struct falcon *falcon, u32 value, u32 offset)
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{
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writel(value, falcon->regs + offset);
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}
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int falcon_wait_idle(struct falcon *falcon)
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{
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u32 value;
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return readl_poll_timeout(falcon->regs + FALCON_IDLESTATE, value,
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(value == 0), 10, 100000);
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}
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static int falcon_dma_wait_idle(struct falcon *falcon)
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{
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u32 value;
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return readl_poll_timeout(falcon->regs + FALCON_DMATRFCMD, value,
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(value & FALCON_DMATRFCMD_IDLE), 10, 100000);
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}
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static int falcon_copy_chunk(struct falcon *falcon,
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phys_addr_t base,
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unsigned long offset,
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enum falcon_memory target)
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{
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u32 cmd = FALCON_DMATRFCMD_SIZE_256B;
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if (target == FALCON_MEMORY_IMEM)
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cmd |= FALCON_DMATRFCMD_IMEM;
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falcon_writel(falcon, offset, FALCON_DMATRFMOFFS);
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falcon_writel(falcon, base, FALCON_DMATRFFBOFFS);
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falcon_writel(falcon, cmd, FALCON_DMATRFCMD);
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return falcon_dma_wait_idle(falcon);
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}
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static void falcon_copy_firmware_image(struct falcon *falcon,
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const struct firmware *firmware)
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{
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u32 *firmware_vaddr = falcon->firmware.vaddr;
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dma_addr_t daddr;
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size_t i;
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int err;
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/* copy the whole thing taking into account endianness */
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for (i = 0; i < firmware->size / sizeof(u32); i++)
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firmware_vaddr[i] = le32_to_cpu(((u32 *)firmware->data)[i]);
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/* ensure that caches are flushed and falcon can see the firmware */
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daddr = dma_map_single(falcon->dev, firmware_vaddr,
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falcon->firmware.size, DMA_TO_DEVICE);
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err = dma_mapping_error(falcon->dev, daddr);
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if (err) {
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dev_err(falcon->dev, "failed to map firmware: %d\n", err);
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return;
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}
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dma_sync_single_for_device(falcon->dev, daddr,
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falcon->firmware.size, DMA_TO_DEVICE);
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dma_unmap_single(falcon->dev, daddr, falcon->firmware.size,
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DMA_TO_DEVICE);
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}
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static int falcon_parse_firmware_image(struct falcon *falcon)
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{
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struct falcon_fw_bin_header_v1 *bin = (void *)falcon->firmware.vaddr;
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struct falcon_fw_os_header_v1 *os;
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/* endian problems would show up right here */
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if (bin->magic != PCI_VENDOR_ID_NVIDIA) {
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dev_err(falcon->dev, "incorrect firmware magic\n");
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return -EINVAL;
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}
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/* currently only version 1 is supported */
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if (bin->version != 1) {
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dev_err(falcon->dev, "unsupported firmware version\n");
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return -EINVAL;
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}
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/* check that the firmware size is consistent */
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if (bin->size > falcon->firmware.size) {
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dev_err(falcon->dev, "firmware image size inconsistency\n");
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return -EINVAL;
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}
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os = falcon->firmware.vaddr + bin->os_header_offset;
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falcon->firmware.bin_data.size = bin->os_size;
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falcon->firmware.bin_data.offset = bin->os_data_offset;
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falcon->firmware.code.offset = os->code_offset;
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falcon->firmware.code.size = os->code_size;
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falcon->firmware.data.offset = os->data_offset;
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falcon->firmware.data.size = os->data_size;
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return 0;
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}
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int falcon_read_firmware(struct falcon *falcon, const char *name)
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{
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int err;
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/* request_firmware prints error if it fails */
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err = request_firmware(&falcon->firmware.firmware, name, falcon->dev);
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if (err < 0)
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return err;
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return 0;
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}
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int falcon_load_firmware(struct falcon *falcon)
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{
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const struct firmware *firmware = falcon->firmware.firmware;
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int err;
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falcon->firmware.size = firmware->size;
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/* allocate iova space for the firmware */
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falcon->firmware.vaddr = falcon->ops->alloc(falcon, firmware->size,
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&falcon->firmware.paddr);
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if (!falcon->firmware.vaddr) {
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dev_err(falcon->dev, "dma memory mapping failed\n");
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return -ENOMEM;
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}
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/* copy firmware image into local area. this also ensures endianness */
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falcon_copy_firmware_image(falcon, firmware);
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/* parse the image data */
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err = falcon_parse_firmware_image(falcon);
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if (err < 0) {
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dev_err(falcon->dev, "failed to parse firmware image\n");
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goto err_setup_firmware_image;
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}
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release_firmware(firmware);
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falcon->firmware.firmware = NULL;
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return 0;
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err_setup_firmware_image:
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falcon->ops->free(falcon, falcon->firmware.size,
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falcon->firmware.paddr, falcon->firmware.vaddr);
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return err;
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}
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int falcon_init(struct falcon *falcon)
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{
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/* check mandatory ops */
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if (!falcon->ops || !falcon->ops->alloc || !falcon->ops->free)
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return -EINVAL;
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falcon->firmware.vaddr = NULL;
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return 0;
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}
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void falcon_exit(struct falcon *falcon)
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{
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if (falcon->firmware.firmware) {
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release_firmware(falcon->firmware.firmware);
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falcon->firmware.firmware = NULL;
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}
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if (falcon->firmware.vaddr) {
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falcon->ops->free(falcon, falcon->firmware.size,
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falcon->firmware.paddr,
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falcon->firmware.vaddr);
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falcon->firmware.vaddr = NULL;
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}
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}
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int falcon_boot(struct falcon *falcon)
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{
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unsigned long offset;
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int err;
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if (!falcon->firmware.vaddr)
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return -EINVAL;
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falcon_writel(falcon, 0, FALCON_DMACTL);
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/* setup the address of the binary data so Falcon can access it later */
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falcon_writel(falcon, (falcon->firmware.paddr +
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falcon->firmware.bin_data.offset) >> 8,
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FALCON_DMATRFBASE);
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/* copy the data segment into Falcon internal memory */
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for (offset = 0; offset < falcon->firmware.data.size; offset += 256)
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falcon_copy_chunk(falcon,
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falcon->firmware.data.offset + offset,
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offset, FALCON_MEMORY_DATA);
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/* copy the first code segment into Falcon internal memory */
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falcon_copy_chunk(falcon, falcon->firmware.code.offset,
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0, FALCON_MEMORY_IMEM);
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/* setup falcon interrupts */
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falcon_writel(falcon, FALCON_IRQMSET_EXT(0xff) |
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FALCON_IRQMSET_SWGEN1 |
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FALCON_IRQMSET_SWGEN0 |
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FALCON_IRQMSET_EXTERR |
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FALCON_IRQMSET_HALT |
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FALCON_IRQMSET_WDTMR,
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FALCON_IRQMSET);
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falcon_writel(falcon, FALCON_IRQDEST_EXT(0xff) |
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FALCON_IRQDEST_SWGEN1 |
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FALCON_IRQDEST_SWGEN0 |
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FALCON_IRQDEST_EXTERR |
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FALCON_IRQDEST_HALT,
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FALCON_IRQDEST);
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/* enable interface */
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falcon_writel(falcon, FALCON_ITFEN_MTHDEN |
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FALCON_ITFEN_CTXEN,
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FALCON_ITFEN);
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/* boot falcon */
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falcon_writel(falcon, 0x00000000, FALCON_BOOTVEC);
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falcon_writel(falcon, FALCON_CPUCTL_STARTCPU, FALCON_CPUCTL);
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err = falcon_wait_idle(falcon);
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if (err < 0) {
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dev_err(falcon->dev, "Falcon boot failed due to timeout\n");
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return err;
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}
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return 0;
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}
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void falcon_execute_method(struct falcon *falcon, u32 method, u32 data)
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{
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falcon_writel(falcon, method >> 2, FALCON_UCLASS_METHOD_OFFSET);
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falcon_writel(falcon, data, FALCON_UCLASS_METHOD_DATA);
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}
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@ -0,0 +1,127 @@
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/*
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* Copyright (c) 2015, NVIDIA Corporation.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef _FALCON_H_
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#define _FALCON_H_
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#include <linux/types.h>
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#define FALCON_UCLASS_METHOD_OFFSET 0x00000040
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#define FALCON_UCLASS_METHOD_DATA 0x00000044
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#define FALCON_IRQMSET 0x00001010
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#define FALCON_IRQMSET_WDTMR (1 << 1)
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#define FALCON_IRQMSET_HALT (1 << 4)
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#define FALCON_IRQMSET_EXTERR (1 << 5)
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#define FALCON_IRQMSET_SWGEN0 (1 << 6)
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#define FALCON_IRQMSET_SWGEN1 (1 << 7)
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#define FALCON_IRQMSET_EXT(v) (((v) & 0xff) << 8)
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#define FALCON_IRQDEST 0x0000101c
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#define FALCON_IRQDEST_HALT (1 << 4)
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#define FALCON_IRQDEST_EXTERR (1 << 5)
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#define FALCON_IRQDEST_SWGEN0 (1 << 6)
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#define FALCON_IRQDEST_SWGEN1 (1 << 7)
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#define FALCON_IRQDEST_EXT(v) (((v) & 0xff) << 8)
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#define FALCON_ITFEN 0x00001048
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#define FALCON_ITFEN_CTXEN (1 << 0)
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#define FALCON_ITFEN_MTHDEN (1 << 1)
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#define FALCON_IDLESTATE 0x0000104c
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#define FALCON_CPUCTL 0x00001100
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#define FALCON_CPUCTL_STARTCPU (1 << 1)
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#define FALCON_BOOTVEC 0x00001104
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#define FALCON_DMACTL 0x0000110c
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#define FALCON_DMACTL_DMEM_SCRUBBING (1 << 1)
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#define FALCON_DMACTL_IMEM_SCRUBBING (1 << 2)
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#define FALCON_DMATRFBASE 0x00001110
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#define FALCON_DMATRFMOFFS 0x00001114
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#define FALCON_DMATRFCMD 0x00001118
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#define FALCON_DMATRFCMD_IDLE (1 << 1)
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#define FALCON_DMATRFCMD_IMEM (1 << 4)
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#define FALCON_DMATRFCMD_SIZE_256B (6 << 8)
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#define FALCON_DMATRFFBOFFS 0x0000111c
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struct falcon_fw_bin_header_v1 {
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u32 magic; /* 0x10de */
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u32 version; /* version of bin format (1) */
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u32 size; /* entire image size including this header */
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u32 os_header_offset;
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u32 os_data_offset;
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u32 os_size;
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};
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struct falcon_fw_os_app_v1 {
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u32 offset;
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u32 size;
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};
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struct falcon_fw_os_header_v1 {
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u32 code_offset;
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u32 code_size;
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u32 data_offset;
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u32 data_size;
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};
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struct falcon;
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struct falcon_ops {
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void *(*alloc)(struct falcon *falcon, size_t size,
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dma_addr_t *paddr);
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void (*free)(struct falcon *falcon, size_t size,
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dma_addr_t paddr, void *vaddr);
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};
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struct falcon_firmware_section {
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unsigned long offset;
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size_t size;
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};
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struct falcon_firmware {
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/* Firmware after it is read but not loaded */
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const struct firmware *firmware;
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/* Raw firmware data */
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dma_addr_t paddr;
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void *vaddr;
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size_t size;
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/* Parsed firmware information */
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struct falcon_firmware_section bin_data;
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struct falcon_firmware_section data;
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struct falcon_firmware_section code;
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};
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struct falcon {
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/* Set by falcon client */
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struct device *dev;
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void __iomem *regs;
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const struct falcon_ops *ops;
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void *data;
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struct falcon_firmware firmware;
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};
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int falcon_init(struct falcon *falcon);
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void falcon_exit(struct falcon *falcon);
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int falcon_read_firmware(struct falcon *falcon, const char *firmware_name);
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int falcon_load_firmware(struct falcon *falcon);
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int falcon_boot(struct falcon *falcon);
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void falcon_execute_method(struct falcon *falcon, u32 method, u32 data);
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int falcon_wait_idle(struct falcon *falcon);
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#endif /* _FALCON_H_ */
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