ASoC: amd: dma config parameters changes
Added dma configuration parameters to rtd structure. Moved dma configuration parameters initialization to hw_params callback. Removed hard coding in prepare and trigger callbacks. Signed-off-by: Vijendar Mukunda <Vijendar.Mukunda@amd.com> Reviewed-by: Daniel Kurtz <djkurtz@chromium.org> Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Vijendar Mukunda
Mark Brown
Родитель
98e1241c35
Коммит
8769bb55fe
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@ -321,19 +321,12 @@ static void config_acp_dma(void __iomem *acp_mmio,
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u32 asic_type)
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{
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u32 pte_offset, sram_bank;
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u16 ch1, ch2, destination, dma_dscr_idx;
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if (rtd->direction == SNDRV_PCM_STREAM_PLAYBACK) {
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pte_offset = ACP_PLAYBACK_PTE_OFFSET;
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ch1 = SYSRAM_TO_ACP_CH_NUM;
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ch2 = ACP_TO_I2S_DMA_CH_NUM;
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sram_bank = ACP_SHARED_RAM_BANK_1_ADDRESS;
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destination = TO_ACP_I2S_1;
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} else {
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pte_offset = ACP_CAPTURE_PTE_OFFSET;
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ch1 = SYSRAM_TO_ACP_CH_NUM;
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ch2 = ACP_TO_I2S_DMA_CH_NUM;
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switch (asic_type) {
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case CHIP_STONEY:
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sram_bank = ACP_SHARED_RAM_BANK_3_ADDRESS;
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@ -341,30 +334,19 @@ static void config_acp_dma(void __iomem *acp_mmio,
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default:
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sram_bank = ACP_SHARED_RAM_BANK_5_ADDRESS;
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}
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destination = FROM_ACP_I2S_1;
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}
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acp_pte_config(acp_mmio, rtd->pg, rtd->num_of_pages,
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pte_offset);
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if (rtd->direction == SNDRV_PCM_STREAM_PLAYBACK)
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dma_dscr_idx = PLAYBACK_START_DMA_DESCR_CH12;
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else
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dma_dscr_idx = CAPTURE_START_DMA_DESCR_CH14;
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/* Configure System memory <-> ACP SRAM DMA descriptors */
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set_acp_sysmem_dma_descriptors(acp_mmio, rtd->size,
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rtd->direction, pte_offset, ch1,
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sram_bank, dma_dscr_idx, asic_type);
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if (rtd->direction == SNDRV_PCM_STREAM_PLAYBACK)
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dma_dscr_idx = PLAYBACK_START_DMA_DESCR_CH13;
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else
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dma_dscr_idx = CAPTURE_START_DMA_DESCR_CH15;
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rtd->direction, pte_offset,
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rtd->ch1, sram_bank,
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rtd->dma_dscr_idx_1, asic_type);
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/* Configure ACP SRAM <-> I2S DMA descriptors */
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set_acp_to_i2s_dma_descriptors(acp_mmio, rtd->size,
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rtd->direction, sram_bank,
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destination, ch2, dma_dscr_idx,
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asic_type);
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rtd->destination, rtd->ch2,
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rtd->dma_dscr_idx_2, asic_type);
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}
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/* Start a given DMA channel transfer */
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@ -804,6 +786,21 @@ static int acp_dma_hw_params(struct snd_pcm_substream *substream,
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acp_reg_write(val, adata->acp_mmio,
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mmACP_I2S_16BIT_RESOLUTION_EN);
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}
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if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
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rtd->ch1 = SYSRAM_TO_ACP_CH_NUM;
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rtd->ch2 = ACP_TO_I2S_DMA_CH_NUM;
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rtd->destination = TO_ACP_I2S_1;
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rtd->dma_dscr_idx_1 = PLAYBACK_START_DMA_DESCR_CH12;
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rtd->dma_dscr_idx_2 = PLAYBACK_START_DMA_DESCR_CH13;
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} else {
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rtd->ch1 = ACP_TO_SYSRAM_CH_NUM;
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rtd->ch2 = I2S_TO_ACP_DMA_CH_NUM;
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rtd->destination = FROM_ACP_I2S_1;
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rtd->dma_dscr_idx_1 = CAPTURE_START_DMA_DESCR_CH14;
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rtd->dma_dscr_idx_2 = CAPTURE_START_DMA_DESCR_CH15;
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}
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size = params_buffer_bytes(params);
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status = snd_pcm_lib_malloc_pages(substream, size);
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if (status < 0)
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@ -898,21 +895,15 @@ static int acp_dma_prepare(struct snd_pcm_substream *substream)
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if (!rtd)
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return -EINVAL;
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if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
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config_acp_dma_channel(rtd->acp_mmio, SYSRAM_TO_ACP_CH_NUM,
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PLAYBACK_START_DMA_DESCR_CH12,
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NUM_DSCRS_PER_CHANNEL, 0);
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config_acp_dma_channel(rtd->acp_mmio, ACP_TO_I2S_DMA_CH_NUM,
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PLAYBACK_START_DMA_DESCR_CH13,
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NUM_DSCRS_PER_CHANNEL, 0);
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} else {
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config_acp_dma_channel(rtd->acp_mmio, ACP_TO_SYSRAM_CH_NUM,
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CAPTURE_START_DMA_DESCR_CH14,
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NUM_DSCRS_PER_CHANNEL, 0);
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config_acp_dma_channel(rtd->acp_mmio, I2S_TO_ACP_DMA_CH_NUM,
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CAPTURE_START_DMA_DESCR_CH15,
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NUM_DSCRS_PER_CHANNEL, 0);
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}
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config_acp_dma_channel(rtd->acp_mmio,
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rtd->ch1,
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rtd->dma_dscr_idx_1,
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NUM_DSCRS_PER_CHANNEL, 0);
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config_acp_dma_channel(rtd->acp_mmio,
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rtd->ch2,
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rtd->dma_dscr_idx_2,
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NUM_DSCRS_PER_CHANNEL, 0);
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return 0;
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}
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@ -939,10 +930,9 @@ static int acp_dma_trigger(struct snd_pcm_substream *substream, int cmd)
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if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
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if (rtd->i2ssp_renderbytescount == 0)
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rtd->i2ssp_renderbytescount = bytescount;
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acp_dma_start(rtd->acp_mmio,
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SYSRAM_TO_ACP_CH_NUM, false);
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acp_dma_start(rtd->acp_mmio, rtd->ch1, false);
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while (acp_reg_read(rtd->acp_mmio, mmACP_DMA_CH_STS) &
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BIT(SYSRAM_TO_ACP_CH_NUM)) {
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BIT(rtd->ch1)) {
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if (!loops--) {
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dev_err(component->dev,
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"acp dma start timeout\n");
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@ -950,38 +940,31 @@ static int acp_dma_trigger(struct snd_pcm_substream *substream, int cmd)
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}
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cpu_relax();
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}
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acp_dma_start(rtd->acp_mmio,
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ACP_TO_I2S_DMA_CH_NUM, true);
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} else {
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if (rtd->i2ssp_capturebytescount == 0)
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rtd->i2ssp_capturebytescount = bytescount;
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acp_dma_start(rtd->acp_mmio,
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I2S_TO_ACP_DMA_CH_NUM, true);
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}
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acp_dma_start(rtd->acp_mmio, rtd->ch2, true);
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ret = 0;
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break;
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case SNDRV_PCM_TRIGGER_STOP:
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case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
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case SNDRV_PCM_TRIGGER_SUSPEND:
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/*
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* Need to stop only circular DMA channels :
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* ACP_TO_I2S_DMA_CH_NUM / I2S_TO_ACP_DMA_CH_NUM. Non-circular
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* channels will stopped automatically after its transfer
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* completes : SYSRAM_TO_ACP_CH_NUM / ACP_TO_SYSRAM_CH_NUM
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/* For playback, non circular dma should be stopped first
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* i.e Sysram to acp dma transfer channel(rtd->ch1) should be
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* stopped before stopping cirular dma which is acp sram to i2s
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* fifo dma transfer channel(rtd->ch2). Where as in Capture
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* scenario, i2s fifo to acp sram dma channel(rtd->ch2) stopped
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* first before stopping acp sram to sysram which is circular
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* dma(rtd->ch1).
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*/
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if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
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ret = acp_dma_stop(rtd->acp_mmio,
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SYSRAM_TO_ACP_CH_NUM);
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ret = acp_dma_stop(rtd->acp_mmio,
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ACP_TO_I2S_DMA_CH_NUM);
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acp_dma_stop(rtd->acp_mmio, rtd->ch1);
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ret = acp_dma_stop(rtd->acp_mmio, rtd->ch2);
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rtd->i2ssp_renderbytescount = 0;
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} else {
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ret = acp_dma_stop(rtd->acp_mmio,
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I2S_TO_ACP_DMA_CH_NUM);
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ret = acp_dma_stop(rtd->acp_mmio,
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ACP_TO_SYSRAM_CH_NUM);
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acp_dma_stop(rtd->acp_mmio, rtd->ch2);
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ret = acp_dma_stop(rtd->acp_mmio, rtd->ch1);
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rtd->i2ssp_capturebytescount = 0;
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}
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break;
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@ -85,6 +85,11 @@ struct audio_substream_data {
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unsigned int order;
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u16 num_of_pages;
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u16 direction;
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u16 ch1;
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u16 ch2;
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u16 destination;
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u16 dma_dscr_idx_1;
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u16 dma_dscr_idx_2;
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uint64_t size;
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u64 i2ssp_renderbytescount;
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u64 i2ssp_capturebytescount;
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