This pull request contains Broadcom ARM-based Device Tree changes for 4.15,
please pull the following: - Eric adds support for the CLCD and PWM controller on Cygnus chis - Loic fixes the console path on the Raspberry Pi 3 (already submitted as fixes) and then proceeds with enabling the BCM43438 bluetooth chip on the Raspberry Pi 3 - Rafal specifies the USB ports on the Luxul XWR-1200 - Dan adds support for the Luxul ABR-4500 based on BCM47094, the Luxul XAP-810 and XAP-1440 both based on BCM53573 - Florian adds support for the Broadcom Hurricane 2 SoC by adding general machine binding, clock binding, SoC DTS include file and a DTS for the Ubiquiti Networks UniFi Switch 8 -----BEGIN PGP SIGNATURE----- iQIcBAABCAAGBQJZ6oyXAAoJEIfQlpxEBwcEZ9sQAIHxupdwbECNH1DJo0jWxqrC bMAfx2yHyr/snPXq46E91QjRIGJLk/E2lMUS0xYWpxC2MRp0pZPFAVTc3qYKgI/9 dGOuJNsk1ZUhbys1BhgVuryYbc6ZSfxz8h5uUxdZ5CLxs9beAsaKDXablsN8Th3O j5OEundSosZ1SPd+F9KNDURjRmfeUzhYlBuRZ2AfWvSJFYjn2cIDM9aCBnDSNYHh Pxs03CF4uGM6DBReIcuG99NKtlaTFoD4v7Empb5i4F0sUNCefcGvhXeMDUBGPeRo z0BDJ4LEBySDzTRd9NhekPC4DM7QsyTjGJz1JbW8FmsK+GnJx5uLMrEgXUtWbSou bup1RHRaxAcpoTv0BTiPK0chfU63RgAqrvDw7wo8O17d06BHtyt0Z5tlv3Oc7OBP 4XhkSj6TmkD6WtQCQWY81jMZ6ezzxeZ/5kOIASAvKc1bh3ocbxpdQkNoxd0pASsI o/CW14a0q0STEdYnF+Y6YGQziuAhRQH/8W6mBUeRfPxQQrG8NXPJoGArP9be1ikR 7mqUivV3pD1mA+3PiiD2fZ57hQRjTowr4bA+RarYxxg7TDu3kUFqkXm93aYXuBbm UzyAZZ4LLbhlcIXIuwfoigoSmQaqUbEIMOqSW8v74PKJDOcSqBS+iZDD+hDSpbPA XShAuXKwt3p6uSei3nib =DmZ2 -----END PGP SIGNATURE----- Merge tag 'arm-soc/for-4.15/devicetree' of http://github.com/Broadcom/stblinux into next/dt Pull "Broadcom devicetree changes for 4.15" from Florian Fainelli: This pull request contains Broadcom ARM-based Device Tree changes for 4.15, please pull the following: - Eric adds support for the CLCD and PWM controller on Cygnus chis - Loic fixes the console path on the Raspberry Pi 3 (already submitted as fixes) and then proceeds with enabling the BCM43438 bluetooth chip on the Raspberry Pi 3 - Rafal specifies the USB ports on the Luxul XWR-1200 - Dan adds support for the Luxul ABR-4500 based on BCM47094, the Luxul XAP-810 and XAP-1440 both based on BCM53573 - Florian adds support for the Broadcom Hurricane 2 SoC by adding general machine binding, clock binding, SoC DTS include file and a DTS for the Ubiquiti Networks UniFi Switch 8 * tag 'arm-soc/for-4.15/devicetree' of http://github.com/Broadcom/stblinux: ARM: dts: Hurricane 2: Add basic support for Ubiquiti UniFi Switch 8 dt-bindings: Add Ubiquiti Networks vendor prefix ARM: dts: Add Broadcom Hurricane 2 DTS include file dt-bindings: Document Broadcom Hurricane 2 clocks dt-bindings: Add documentation for Broadcom Hurricane 2 SoCs ARM: dts: BCM53573: Add DT for Luxul XAP-1440 ARM: dts: BCM53573: Add DT for Luxul XAP-810 ARM: dts: BCM5301X: Add DT for Luxul ABR-4500 ARM: dts: BCM5301X: Add DT for Luxul XBR-4500 ARM: dts: BCM5301X: Specify USB ports for USB LED of Luxul XWR-1200 ARM: dts: bcm2837-rpi-3-b: Add bcm43438 serial slave ARM: dts: bcm283x: Fix console path on RPi3 ARM: dts: cygnus: Add the PWM node ARM: dts: cygnus: Add the CLCD controller
This commit is contained in:
Arnd Bergmann
Коммит
877b203e15
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@ -0,0 +1,14 @@
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Broadcom Hurricane 2 device tree bindings
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---------------------------------------
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Broadcom Hurricane 2 family of SoCs are used for switching control. These SoCs
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are based on Broadcom's iProc SoC architecture and feature a single core Cortex
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A9 ARM CPUs, DDR2/DDR3 memory, PCIe GEN-2, USB 2.0 and USB 3.0, serial and NAND
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flash and a PCIe attached integrated switching engine.
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Boards with Hurricane SoCs shall have the following properties:
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Required root node property:
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BCM53342
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compatible = "brcm,bcm53342", "brcm,hr2";
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@ -137,6 +137,20 @@ These clock IDs are defined in:
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ch1_audio audiopll 2 BCM_CYGNUS_AUDIOPLL_CH1
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ch2_audio audiopll 3 BCM_CYGNUS_AUDIOPLL_CH2
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Hurricane 2
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------
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PLL and leaf clock compatible strings for Hurricane 2 are:
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"brcm,hr2-armpll"
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The following table defines the set of PLL/clock for Hurricane 2:
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Clock Source Index ID
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--- ----- ----- ---------
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crystal N/A N/A N/A
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armpll crystal N/A N/A
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Northstar and Northstar Plus
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------
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PLL and leaf clock compatible strings for Northstar and Northstar Plus are:
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@ -354,6 +354,7 @@ truly Truly Semiconductors Limited
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tsd Theobroma Systems Design und Consulting GmbH
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tyan Tyan Computer Corporation
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ucrobotics uCRobotics
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ubnt Ubiquiti Networks
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udoo Udoo
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uniwest United Western Technologies Corp (UniWest)
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upisemi uPI Semiconductor Corp.
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@ -100,6 +100,8 @@ dtb-$(CONFIG_ARCH_BCM_5301X) += \
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bcm4709-tplink-archer-c9-v1.dtb \
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bcm47094-dlink-dir-885l.dtb \
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bcm47094-linksys-panamera.dtb \
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bcm47094-luxul-abr-4500.dtb \
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bcm47094-luxul-xbr-4500.dtb \
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bcm47094-luxul-xwr-3100.dtb \
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bcm47094-netgear-r8500.dtb \
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bcm94708.dtb \
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@ -108,6 +110,8 @@ dtb-$(CONFIG_ARCH_BCM_5301X) += \
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bcm953012hr.dtb \
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bcm953012k.dtb
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dtb-$(CONFIG_ARCH_BCM_53573) += \
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bcm47189-luxul-xap-1440.dtb \
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bcm47189-luxul-xap-810.dtb \
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bcm47189-tenda-ac9.dtb \
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bcm947189acdbmr.dtb
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dtb-$(CONFIG_ARCH_BCM_63XX) += \
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@ -117,6 +121,8 @@ dtb-$(CONFIG_ARCH_BCM_CYGNUS) += \
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bcm911360k.dtb \
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bcm958300k.dtb \
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bcm958305k.dtb
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dtb-$(CONFIG_ARCH_BCM_HR2) += \
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bcm53340-ubnt-unifi-switch8.dtb
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dtb-$(CONFIG_ARCH_BCM_MOBILE) += \
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bcm28155-ap.dtb \
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bcm21664-garnet.dtb \
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@ -473,6 +473,16 @@
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status = "disabled";
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};
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clcd: clcd@180a0000 {
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compatible = "arm,pl111", "arm,primecell";
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reg = <0x180a0000 0x1000>;
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interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "combined";
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clocks = <&axi41_clk>, <&apb_clk>;
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clock-names = "clcdclk", "apb_pclk";
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status = "disabled";
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};
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v3d: v3d@180a2000 {
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compatible = "brcm,cygnus-v3d";
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reg = <0x180a2000 0x1000>;
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@ -575,6 +585,14 @@
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status = "disabled";
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};
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pwm: pwm@180aa500 {
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compatible = "brcm,kona-pwm";
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reg = <0x180aa500 0xc4>;
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#pwm-cells = <3>;
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clocks = <&asiu_clks BCM_CYGNUS_ASIU_PWM_CLK>;
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status = "disabled";
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};
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keypad: keypad@180ac000 {
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compatible = "brcm,bcm-keypad";
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reg = <0x180ac000 0x14c>;
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@ -0,0 +1,368 @@
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/*
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* BSD LICENSE
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*
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* Copyright(c) 2017 Broadcom. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
|
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* the documentation and/or other materials provided with the
|
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* distribution.
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* * Neither the name of Broadcom Corporation nor the names of its
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||||
* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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/ {
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compatible = "brcm,hr2";
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model = "Broadcom Hurricane 2 SoC";
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interrupt-parent = <&gic>;
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#address-cells = <1>;
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#size-cells = <1>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a9";
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next-level-cache = <&L2>;
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reg = <0x0>;
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};
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};
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pmu {
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compatible = "arm,cortex-a9-pmu";
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interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-affinity = <&cpu0>;
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};
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mpcore@19000000 {
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compatible = "simple-bus";
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ranges = <0x00000000 0x19000000 0x00023000>;
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#address-cells = <1>;
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#size-cells = <1>;
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a9pll: arm_clk@0 {
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#clock-cells = <0>;
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compatible = "brcm,hr2-armpll";
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clocks = <&osc>;
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reg = <0x0 0x1000>;
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};
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timer@20200 {
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compatible = "arm,cortex-a9-global-timer";
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reg = <0x20200 0x100>;
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interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&periph_clk>;
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};
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twd-timer@20600 {
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compatible = "arm,cortex-a9-twd-timer";
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reg = <0x20600 0x20>;
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) |
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IRQ_TYPE_LEVEL_HIGH)>;
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clocks = <&periph_clk>;
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};
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twd-watchdog@20620 {
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compatible = "arm,cortex-a9-twd-wdt";
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reg = <0x20620 0x20>;
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interrupts = <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) |
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IRQ_TYPE_LEVEL_HIGH)>;
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clocks = <&periph_clk>;
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};
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gic: interrupt-controller@21000 {
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compatible = "arm,cortex-a9-gic";
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#interrupt-cells = <3>;
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#address-cells = <0>;
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interrupt-controller;
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reg = <0x21000 0x1000>,
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<0x20100 0x100>;
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};
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L2: l2-cache@22000 {
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compatible = "arm,pl310-cache";
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reg = <0x22000 0x1000>;
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cache-unified;
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cache-level = <2>;
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};
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};
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clocks {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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osc: oscillator {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <25000000>;
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};
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periph_clk: periph_clk {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&a9pll>;
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clock-div = <2>;
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clock-mult = <1>;
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};
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};
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axi@18000000 {
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compatible = "simple-bus";
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ranges = <0x00000000 0x18000000 0x0011c40c>;
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#address-cells = <1>;
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#size-cells = <1>;
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uart0: serial@300 {
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compatible = "ns16550a";
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reg = <0x0300 0x100>;
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interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&osc>;
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status = "disabled";
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};
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uart1: serial@400 {
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compatible = "ns16550a";
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reg = <0x0400 0x100>;
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interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&osc>;
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status = "disabled";
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};
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dma@20000 {
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compatible = "arm,pl330", "arm,primecell";
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reg = <0x20000 0x1000>;
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interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
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#dma-cells = <1>;
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status = "disabled";
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};
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amac0: ethernet@22000 {
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compatible = "brcm,nsp-amac";
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reg = <0x22000 0x1000>,
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<0x110000 0x1000>;
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reg-names = "amac_base", "idm_base";
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interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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nand: nand@26000 {
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compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1";
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reg = <0x26000 0x600>,
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<0x11b408 0x600>,
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<0x026f00 0x20>;
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reg-names = "nand", "iproc-idm", "iproc-ext";
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interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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brcm,nand-has-wp;
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};
|
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|
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gpiob: gpio@30000 {
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compatible = "brcm,iproc-hr2-gpio", "brcm,iproc-gpio";
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reg = <0x30000 0x50>;
|
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#gpio-cells = <2>;
|
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gpio-controller;
|
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ngpios = <4>;
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interrupt-controller;
|
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interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
|
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};
|
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|
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pwm: pwm@31000 {
|
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compatible = "brcm,iproc-pwm";
|
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reg = <0x31000 0x28>;
|
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clocks = <&osc>;
|
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#pwm-cells = <3>;
|
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status = "disabled";
|
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};
|
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|
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rng: rng@33000 {
|
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compatible = "brcm,bcm-nsp-rng";
|
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reg = <0x33000 0x14>;
|
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};
|
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|
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qspi: qspi@27200 {
|
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compatible = "brcm,spi-bcm-qspi", "brcm,spi-nsp-qspi";
|
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reg = <0x027200 0x184>,
|
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<0x027000 0x124>,
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<0x11c408 0x004>,
|
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<0x0273a0 0x01c>;
|
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reg-names = "mspi", "bspi", "intr_regs",
|
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"intr_status_reg";
|
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interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
|
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<GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>,
|
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<GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
|
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<GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>,
|
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<GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
|
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<GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
|
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<GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
|
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interrupt-names = "spi_lr_fullness_reached",
|
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"spi_lr_session_aborted",
|
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"spi_lr_impatient",
|
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"spi_lr_session_done",
|
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"spi_lr_overhead",
|
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"mspi_done",
|
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"mspi_halted";
|
||||
num-cs = <2>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
/* partitions defined in board DTS */
|
||||
};
|
||||
|
||||
ccbtimer0: timer@34000 {
|
||||
compatible = "arm,sp804";
|
||||
reg = <0x34000 0x1000>;
|
||||
interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
ccbtimer1: timer@35000 {
|
||||
compatible = "arm,sp804";
|
||||
reg = <0x35000 0x1000>;
|
||||
interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
|
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<GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
i2c0: i2c@38000 {
|
||||
compatible = "brcm,iproc-i2c";
|
||||
reg = <0x38000 0x50>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <GIC_SPI 95 IRQ_TYPE_NONE>;
|
||||
clock-frequency = <100000>;
|
||||
};
|
||||
|
||||
watchdog@39000 {
|
||||
compatible = "arm,sp805", "arm,primecell";
|
||||
reg = <0x39000 0x1000>;
|
||||
interrupts = <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
i2c1: i2c@3b000 {
|
||||
compatible = "brcm,iproc-i2c";
|
||||
reg = <0x3b000 0x50>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <GIC_SPI 96 IRQ_TYPE_NONE>;
|
||||
clock-frequency = <100000>;
|
||||
};
|
||||
};
|
||||
|
||||
pflash: nor@20000000 {
|
||||
compatible = "cfi-flash", "jedec-flash";
|
||||
reg = <0x20000000 0x04000000>;
|
||||
status = "disabled";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
/* partitions defined in board DTS */
|
||||
};
|
||||
|
||||
pcie0: pcie@18012000 {
|
||||
compatible = "brcm,iproc-pcie";
|
||||
reg = <0x18012000 0x1000>;
|
||||
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &gic GIC_SPI 186 IRQ_TYPE_NONE>;
|
||||
|
||||
linux,pci-domain = <0>;
|
||||
|
||||
bus-range = <0x00 0xff>;
|
||||
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
device_type = "pci";
|
||||
|
||||
/* Note: The HW does not support I/O resources. So,
|
||||
* only the memory resource range is being specified.
|
||||
*/
|
||||
ranges = <0x82000000 0 0x08000000 0x08000000 0 0x8000000>;
|
||||
|
||||
status = "disabled";
|
||||
|
||||
msi-parent = <&msi0>;
|
||||
msi0: msi-controller {
|
||||
compatible = "brcm,iproc-msi";
|
||||
msi-controller;
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <GIC_SPI 182 IRQ_TYPE_NONE>,
|
||||
<GIC_SPI 183 IRQ_TYPE_NONE>,
|
||||
<GIC_SPI 184 IRQ_TYPE_NONE>,
|
||||
<GIC_SPI 185 IRQ_TYPE_NONE>;
|
||||
brcm,pcie-msi-inten;
|
||||
};
|
||||
};
|
||||
|
||||
pcie1: pcie@18013000 {
|
||||
compatible = "brcm,iproc-pcie";
|
||||
reg = <0x18013000 0x1000>;
|
||||
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &gic GIC_SPI 192 IRQ_TYPE_NONE>;
|
||||
|
||||
linux,pci-domain = <1>;
|
||||
|
||||
bus-range = <0x00 0xff>;
|
||||
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
device_type = "pci";
|
||||
|
||||
/* Note: The HW does not support I/O resources. So,
|
||||
* only the memory resource range is being specified.
|
||||
*/
|
||||
ranges = <0x82000000 0 0x40000000 0x40000000 0 0x8000000>;
|
||||
|
||||
status = "disabled";
|
||||
|
||||
msi-parent = <&msi1>;
|
||||
msi1: msi-controller {
|
||||
compatible = "brcm,iproc-msi";
|
||||
msi-controller;
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <GIC_SPI 188 IRQ_TYPE_NONE>,
|
||||
<GIC_SPI 189 IRQ_TYPE_NONE>,
|
||||
<GIC_SPI 190 IRQ_TYPE_NONE>,
|
||||
<GIC_SPI 191 IRQ_TYPE_NONE>;
|
||||
brcm,pcie-msi-inten;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -18,12 +18,9 @@
|
|||
compatible = "raspberrypi,model-zero-w", "brcm,bcm2835";
|
||||
model = "Raspberry Pi Zero W";
|
||||
|
||||
/* Needed by firmware to properly init UARTs */
|
||||
aliases {
|
||||
uart0 = "/soc/serial@7e201000";
|
||||
uart1 = "/soc/serial@7e215040";
|
||||
serial0 = "/soc/serial@7e201000";
|
||||
serial1 = "/soc/serial@7e215040";
|
||||
chosen {
|
||||
/* 8250 auxiliary UART instead of pl011 */
|
||||
stdout-path = "serial1:115200n8";
|
||||
};
|
||||
|
||||
leds {
|
||||
|
|
|
|||
|
|
@ -8,6 +8,11 @@
|
|||
compatible = "raspberrypi,3-model-b", "brcm,bcm2837";
|
||||
model = "Raspberry Pi 3 Model B";
|
||||
|
||||
chosen {
|
||||
/* 8250 auxiliary UART instead of pl011 */
|
||||
stdout-path = "serial1:115200n8";
|
||||
};
|
||||
|
||||
memory {
|
||||
reg = <0 0x40000000>;
|
||||
};
|
||||
|
|
@ -24,6 +29,11 @@
|
|||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart0_gpio32 &gpclk2_gpio43>;
|
||||
status = "okay";
|
||||
|
||||
bluetooth {
|
||||
compatible = "brcm,bcm43438-bt";
|
||||
max-speed = <2000000>;
|
||||
};
|
||||
};
|
||||
|
||||
/* uart1 is mapped to the pin header */
|
||||
|
|
|
|||
|
|
@ -20,8 +20,13 @@
|
|||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
aliases {
|
||||
serial0 = &uart0;
|
||||
serial1 = &uart1;
|
||||
};
|
||||
|
||||
chosen {
|
||||
bootargs = "earlyprintk console=ttyAMA0";
|
||||
stdout-path = "serial0:115200n8";
|
||||
};
|
||||
|
||||
thermal-zones {
|
||||
|
|
|
|||
|
|
@ -57,7 +57,8 @@
|
|||
usb {
|
||||
label = "bcm53xx:green:usb";
|
||||
gpios = <&chipcommon 8 GPIO_ACTIVE_LOW>;
|
||||
linux,default-trigger = "none";
|
||||
trigger-sources = <&ohci_port2>, <&ehci_port2>;
|
||||
linux,default-trigger = "usbport";
|
||||
};
|
||||
|
||||
status {
|
||||
|
|
|
|||
|
|
@ -0,0 +1,63 @@
|
|||
/*
|
||||
* Copyright (C) 2017 Luxul Inc.
|
||||
*
|
||||
* Licensed under the ISC license.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "bcm4708.dtsi"
|
||||
#include "bcm5301x-nand-cs0-bch8.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "luxul,abr-4500-v1", "brcm,bcm47094", "brcm,bcm4708";
|
||||
model = "Luxul ABR-4500 V1";
|
||||
|
||||
chosen {
|
||||
bootargs = "earlycon";
|
||||
};
|
||||
|
||||
memory {
|
||||
reg = <0x00000000 0x08000000
|
||||
0x88000000 0x18000000>;
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
status {
|
||||
label = "bcm53xx:green:status";
|
||||
gpios = <&chipcommon 20 GPIO_ACTIVE_LOW>;
|
||||
linux,default-trigger = "timer";
|
||||
};
|
||||
|
||||
usb3 {
|
||||
label = "bcm53xx:green:usb3";
|
||||
gpios = <&chipcommon 19 GPIO_ACTIVE_LOW>;
|
||||
trigger-sources = <&ohci_port1>, <&ehci_port1>,
|
||||
<&xhci_port1>;
|
||||
linux,default-trigger = "usbport";
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
gpio-keys {
|
||||
compatible = "gpio-keys";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
restart {
|
||||
label = "Reset";
|
||||
linux,code = <KEY_RESTART>;
|
||||
gpios = <&chipcommon 17 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&usb3 {
|
||||
vcc-gpio = <&chipcommon 18 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
&spi_nor {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -0,0 +1,63 @@
|
|||
/*
|
||||
* Copyright (C) 2017 Luxul Inc.
|
||||
*
|
||||
* Licensed under the ISC license.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "bcm4708.dtsi"
|
||||
#include "bcm5301x-nand-cs0-bch8.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "luxul,xbr-4500-v1", "brcm,bcm47094", "brcm,bcm4708";
|
||||
model = "Luxul XBR-4500 V1";
|
||||
|
||||
chosen {
|
||||
bootargs = "earlycon";
|
||||
};
|
||||
|
||||
memory {
|
||||
reg = <0x00000000 0x08000000
|
||||
0x88000000 0x18000000>;
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
status {
|
||||
label = "bcm53xx:green:status";
|
||||
gpios = <&chipcommon 20 GPIO_ACTIVE_HIGH>;
|
||||
linux,default-trigger = "timer";
|
||||
};
|
||||
|
||||
usb3 {
|
||||
label = "bcm53xx:green:usb3";
|
||||
gpios = <&chipcommon 19 GPIO_ACTIVE_HIGH>;
|
||||
trigger-sources = <&ohci_port1>, <&ehci_port1>,
|
||||
<&xhci_port1>;
|
||||
linux,default-trigger = "usbport";
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
gpio-keys {
|
||||
compatible = "gpio-keys";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
restart {
|
||||
label = "Reset";
|
||||
linux,code = <KEY_RESTART>;
|
||||
gpios = <&chipcommon 17 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&usb3 {
|
||||
vcc-gpio = <&chipcommon 18 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
&spi_nor {
|
||||
status = "okay";
|
||||
};
|
||||
|
|
@ -0,0 +1,50 @@
|
|||
/*
|
||||
* Copyright 2017 Luxul Inc.
|
||||
*
|
||||
* Licensed under the ISC license.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "bcm53573.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "luxul,xap-1440-v1", "brcm,bcm47189", "brcm,bcm53573";
|
||||
model = "Luxul XAP-1440 V1";
|
||||
|
||||
chosen {
|
||||
bootargs = "earlycon";
|
||||
};
|
||||
|
||||
memory {
|
||||
reg = <0x00000000 0x08000000>;
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
wlan {
|
||||
label = "bcm53xx:blue:wlan";
|
||||
gpios = <&chipcommon 10 GPIO_ACTIVE_LOW>;
|
||||
linux,default-trigger = "default-off";
|
||||
};
|
||||
|
||||
system {
|
||||
label = "bcm53xx:green:system";
|
||||
gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>;
|
||||
linux,default-trigger = "timer";
|
||||
};
|
||||
};
|
||||
|
||||
gpio-keys {
|
||||
compatible = "gpio-keys";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
restart {
|
||||
label = "Reset";
|
||||
linux,code = <KEY_RESTART>;
|
||||
gpios = <&chipcommon 7 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,87 @@
|
|||
/*
|
||||
* Copyright 2017 Luxul Inc.
|
||||
*
|
||||
* Licensed under the ISC license.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "bcm53573.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "luxul,xap-810-v1", "brcm,bcm47189", "brcm,bcm53573";
|
||||
model = "Luxul XAP-810 V1";
|
||||
|
||||
chosen {
|
||||
bootargs = "earlycon";
|
||||
};
|
||||
|
||||
memory {
|
||||
reg = <0x00000000 0x08000000>;
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
5ghz {
|
||||
label = "bcm53xx:blue:5ghz";
|
||||
gpios = <&chipcommon 11 GPIO_ACTIVE_HIGH>;
|
||||
linux,default-trigger = "default-off";
|
||||
};
|
||||
|
||||
system {
|
||||
label = "bcm53xx:green:system";
|
||||
gpios = <&chipcommon 15 GPIO_ACTIVE_HIGH>;
|
||||
linux,default-trigger = "timer";
|
||||
};
|
||||
};
|
||||
|
||||
pcie0_leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
2ghz {
|
||||
label = "bcm53xx:blue:2ghz";
|
||||
gpios = <&pcie0_chipcommon 3 GPIO_ACTIVE_HIGH>;
|
||||
linux,default-trigger = "default-off";
|
||||
};
|
||||
};
|
||||
|
||||
gpio-keys {
|
||||
compatible = "gpio-keys";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
restart {
|
||||
label = "Reset";
|
||||
linux,code = <KEY_RESTART>;
|
||||
gpios = <&chipcommon 7 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pcie0 {
|
||||
ranges = <0x00000000 0 0 0 0 0x00100000>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
|
||||
bridge@0,0,0 {
|
||||
reg = <0x0000 0 0 0 0>;
|
||||
ranges = <0x00000000 0 0 0 0 0 0 0x00100000>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
|
||||
wifi@0,1,0 {
|
||||
reg = <0x0000 0 0 0 0>;
|
||||
ranges = <0x00000000 0 0 0 0x00100000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
pcie0_chipcommon: chipcommon@0 {
|
||||
reg = <0 0x1000>;
|
||||
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,85 @@
|
|||
/*
|
||||
* DTS for Unifi Switch 8 port
|
||||
*
|
||||
* Copyright (C) 2017 Florian Fainelli <f.fainelli@gmail.com>
|
||||
*
|
||||
* Licensed under the GNU/GPL. See COPYING for details.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "bcm-hr2.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "ubnt,unifi-switch8", "brcm,bcm53342", "brcm,hr2";
|
||||
model = "Ubiquiti UniFi Switch 8 (BCM53342)";
|
||||
|
||||
/* Hurricane 2 designs use the second UART */
|
||||
chosen {
|
||||
bootargs = "console=ttyS1,115200 earlyprintk";
|
||||
};
|
||||
|
||||
memory@0 {
|
||||
reg = <0x00000000 0x08000000>,
|
||||
<0x68000000 0x08000000>;
|
||||
};
|
||||
};
|
||||
|
||||
&uart1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&qspi {
|
||||
status = "okay";
|
||||
bspi-sel = <0>;
|
||||
|
||||
flash: m25p80@0 {
|
||||
compatible = "m25p80";
|
||||
reg = <0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
spi-max-frequency = <12500000>;
|
||||
spi-cpol;
|
||||
spi-cpha;
|
||||
|
||||
partition@0 {
|
||||
label = "u-boot";
|
||||
reg = <0x0 0xc0000>;
|
||||
};
|
||||
|
||||
partition@c0000 {
|
||||
label = "u-boot-env";
|
||||
reg = <0xc0000 0x10000>;
|
||||
};
|
||||
|
||||
partition@d0000 {
|
||||
label = "shmoo";
|
||||
reg = <0xd0000 0x10000>;
|
||||
};
|
||||
|
||||
partition@e0000 {
|
||||
label = "kernel0";
|
||||
reg = <0xe0000 0xf00000>;
|
||||
};
|
||||
|
||||
partition@fe0000 {
|
||||
label = "kernel1";
|
||||
reg = <0xfe0000 0xf10000>;
|
||||
};
|
||||
|
||||
partition@1ef0000 {
|
||||
label = "cfg";
|
||||
reg = <0x1ef0000 0x100000>;
|
||||
};
|
||||
|
||||
partition@1ff0000 {
|
||||
label = "EEPROM";
|
||||
reg = <0x1ff0000 0x10000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pcie0 {
|
||||
/* Attaches to the internal switch */
|
||||
status = "okay";
|
||||
};
|
||||
Загрузка…
Ссылка в новой задаче