Merge branch 'x86-mrst-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip
* 'x86-mrst-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip: x86: sfi: Make local functions static x86, earlyprintk: Add hsu early console for Intel Medfield platform x86, earlyprintk: Add earlyprintk for Intel Moorestown platform x86: Add two helper macros for fixed address mapping x86, mrst: A function in a header file needs to be marked "inline"
This commit is contained in:
Linus Torvalds
Коммит
87affd0b94
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@ -43,6 +43,10 @@ config EARLY_PRINTK
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with klogd/syslogd or the X server. You should normally N here,
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unless you want to debug such a crash.
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config EARLY_PRINTK_MRST
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bool "Early printk for MRST platform support"
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depends on EARLY_PRINTK && X86_MRST
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config EARLY_PRINTK_DBGP
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bool "Early printk via EHCI debug port"
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depends on EARLY_PRINTK && PCI
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@ -214,5 +214,20 @@ static inline unsigned long virt_to_fix(const unsigned long vaddr)
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BUG_ON(vaddr >= FIXADDR_TOP || vaddr < FIXADDR_START);
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return __virt_to_fix(vaddr);
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}
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/* Return an pointer with offset calculated */
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static inline unsigned long __set_fixmap_offset(enum fixed_addresses idx,
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phys_addr_t phys, pgprot_t flags)
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{
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__set_fixmap(idx, phys, flags);
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return fix_to_virt(idx) + (phys & (PAGE_SIZE - 1));
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}
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#define set_fixmap_offset(idx, phys) \
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__set_fixmap_offset(idx, phys, PAGE_KERNEL)
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#define set_fixmap_offset_nocache(idx, phys) \
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__set_fixmap_offset(idx, phys, PAGE_KERNEL_NOCACHE)
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#endif /* !__ASSEMBLY__ */
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#endif /* _ASM_X86_FIXMAP_H */
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@ -10,6 +10,9 @@
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*/
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#ifndef _ASM_X86_MRST_H
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#define _ASM_X86_MRST_H
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#include <linux/sfi.h>
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extern int pci_mrst_init(void);
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int __init sfi_parse_mrtc(struct sfi_table_header *table);
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@ -26,7 +29,7 @@ enum mrst_cpu_type {
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};
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extern enum mrst_cpu_type __mrst_cpu_chip;
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static enum mrst_cpu_type mrst_identify_cpu(void)
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static inline enum mrst_cpu_type mrst_identify_cpu(void)
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{
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return __mrst_cpu_chip;
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}
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@ -42,4 +45,9 @@ extern enum mrst_timer_options mrst_timer_options;
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#define SFI_MTMR_MAX_NUM 8
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#define SFI_MRTC_MAX 8
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extern struct console early_mrst_console;
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extern void mrst_early_console_init(void);
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extern struct console early_hsu_console;
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extern void hsu_early_console_init(void);
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#endif /* _ASM_X86_MRST_H */
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@ -86,6 +86,7 @@ obj-$(CONFIG_DOUBLEFAULT) += doublefault_32.o
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obj-$(CONFIG_KGDB) += kgdb.o
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obj-$(CONFIG_VM86) += vm86_32.o
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obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
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obj-$(CONFIG_EARLY_PRINTK_MRST) += early_printk_mrst.o
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obj-$(CONFIG_HPET_TIMER) += hpet.o
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obj-$(CONFIG_APB_TIMER) += apb_timer.o
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@ -14,6 +14,7 @@
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#include <xen/hvc-console.h>
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#include <asm/pci-direct.h>
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#include <asm/fixmap.h>
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#include <asm/mrst.h>
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#include <asm/pgtable.h>
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#include <linux/usb/ehci_def.h>
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@ -238,6 +239,18 @@ static int __init setup_early_printk(char *buf)
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#ifdef CONFIG_HVC_XEN
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if (!strncmp(buf, "xen", 3))
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early_console_register(&xenboot_console, keep);
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#endif
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#ifdef CONFIG_X86_MRST_EARLY_PRINTK
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if (!strncmp(buf, "mrst", 4)) {
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mrst_early_console_init();
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early_console_register(&early_mrst_console, keep);
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}
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if (!strncmp(buf, "hsu", 3)) {
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hsu_early_console_init();
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early_console_register(&early_hsu_console, keep);
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}
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#endif
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buf++;
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}
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@ -0,0 +1,319 @@
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/*
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* early_printk_mrst.c - early consoles for Intel MID platforms
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*
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* Copyright (c) 2008-2010, Intel Corporation
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; version 2
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* of the License.
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*/
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/*
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* This file implements two early consoles named mrst and hsu.
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* mrst is based on Maxim3110 spi-uart device, it exists in both
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* Moorestown and Medfield platforms, while hsu is based on a High
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* Speed UART device which only exists in the Medfield platform
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*/
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#include <linux/serial_reg.h>
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#include <linux/serial_mfd.h>
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#include <linux/kmsg_dump.h>
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#include <linux/console.h>
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#include <linux/kernel.h>
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#include <linux/delay.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <asm/fixmap.h>
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#include <asm/pgtable.h>
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#include <asm/mrst.h>
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#define MRST_SPI_TIMEOUT 0x200000
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#define MRST_REGBASE_SPI0 0xff128000
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#define MRST_REGBASE_SPI1 0xff128400
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#define MRST_CLK_SPI0_REG 0xff11d86c
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/* Bit fields in CTRLR0 */
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#define SPI_DFS_OFFSET 0
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#define SPI_FRF_OFFSET 4
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#define SPI_FRF_SPI 0x0
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#define SPI_FRF_SSP 0x1
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#define SPI_FRF_MICROWIRE 0x2
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#define SPI_FRF_RESV 0x3
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#define SPI_MODE_OFFSET 6
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#define SPI_SCPH_OFFSET 6
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#define SPI_SCOL_OFFSET 7
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#define SPI_TMOD_OFFSET 8
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#define SPI_TMOD_TR 0x0 /* xmit & recv */
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#define SPI_TMOD_TO 0x1 /* xmit only */
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#define SPI_TMOD_RO 0x2 /* recv only */
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#define SPI_TMOD_EPROMREAD 0x3 /* eeprom read mode */
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#define SPI_SLVOE_OFFSET 10
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#define SPI_SRL_OFFSET 11
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#define SPI_CFS_OFFSET 12
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/* Bit fields in SR, 7 bits */
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#define SR_MASK 0x7f /* cover 7 bits */
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#define SR_BUSY (1 << 0)
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#define SR_TF_NOT_FULL (1 << 1)
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#define SR_TF_EMPT (1 << 2)
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#define SR_RF_NOT_EMPT (1 << 3)
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#define SR_RF_FULL (1 << 4)
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#define SR_TX_ERR (1 << 5)
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#define SR_DCOL (1 << 6)
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struct dw_spi_reg {
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u32 ctrl0;
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u32 ctrl1;
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u32 ssienr;
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u32 mwcr;
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u32 ser;
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u32 baudr;
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u32 txfltr;
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u32 rxfltr;
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u32 txflr;
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u32 rxflr;
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u32 sr;
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u32 imr;
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u32 isr;
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u32 risr;
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u32 txoicr;
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u32 rxoicr;
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u32 rxuicr;
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u32 msticr;
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u32 icr;
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u32 dmacr;
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u32 dmatdlr;
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u32 dmardlr;
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u32 idr;
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u32 version;
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/* Currently operates as 32 bits, though only the low 16 bits matter */
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u32 dr;
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} __packed;
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#define dw_readl(dw, name) __raw_readl(&(dw)->name)
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#define dw_writel(dw, name, val) __raw_writel((val), &(dw)->name)
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/* Default use SPI0 register for mrst, we will detect Penwell and use SPI1 */
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static unsigned long mrst_spi_paddr = MRST_REGBASE_SPI0;
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static u32 *pclk_spi0;
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/* Always contains an accessable address, start with 0 */
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static struct dw_spi_reg *pspi;
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static struct kmsg_dumper dw_dumper;
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static int dumper_registered;
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static void dw_kmsg_dump(struct kmsg_dumper *dumper,
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enum kmsg_dump_reason reason,
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const char *s1, unsigned long l1,
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const char *s2, unsigned long l2)
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{
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int i;
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/* When run to this, we'd better re-init the HW */
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mrst_early_console_init();
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for (i = 0; i < l1; i++)
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early_mrst_console.write(&early_mrst_console, s1 + i, 1);
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for (i = 0; i < l2; i++)
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early_mrst_console.write(&early_mrst_console, s2 + i, 1);
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}
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/* Set the ratio rate to 115200, 8n1, IRQ disabled */
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static void max3110_write_config(void)
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{
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u16 config;
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config = 0xc001;
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dw_writel(pspi, dr, config);
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}
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/* Translate char to a eligible word and send to max3110 */
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static void max3110_write_data(char c)
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{
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u16 data;
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data = 0x8000 | c;
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dw_writel(pspi, dr, data);
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}
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void mrst_early_console_init(void)
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{
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u32 ctrlr0 = 0;
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u32 spi0_cdiv;
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u32 freq; /* Freqency info only need be searched once */
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/* Base clk is 100 MHz, the actual clk = 100M / (clk_divider + 1) */
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pclk_spi0 = (void *)set_fixmap_offset_nocache(FIX_EARLYCON_MEM_BASE,
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MRST_CLK_SPI0_REG);
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spi0_cdiv = ((*pclk_spi0) & 0xe00) >> 9;
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freq = 100000000 / (spi0_cdiv + 1);
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if (mrst_identify_cpu() == MRST_CPU_CHIP_PENWELL)
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mrst_spi_paddr = MRST_REGBASE_SPI1;
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pspi = (void *)set_fixmap_offset_nocache(FIX_EARLYCON_MEM_BASE,
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mrst_spi_paddr);
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/* Disable SPI controller */
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dw_writel(pspi, ssienr, 0);
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/* Set control param, 8 bits, transmit only mode */
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ctrlr0 = dw_readl(pspi, ctrl0);
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ctrlr0 &= 0xfcc0;
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ctrlr0 |= 0xf | (SPI_FRF_SPI << SPI_FRF_OFFSET)
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| (SPI_TMOD_TO << SPI_TMOD_OFFSET);
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dw_writel(pspi, ctrl0, ctrlr0);
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/*
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* Change the spi0 clk to comply with 115200 bps, use 100000 to
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* calculate the clk dividor to make the clock a little slower
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* than real baud rate.
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*/
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dw_writel(pspi, baudr, freq/100000);
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/* Disable all INT for early phase */
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dw_writel(pspi, imr, 0x0);
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/* Set the cs to spi-uart */
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dw_writel(pspi, ser, 0x2);
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/* Enable the HW, the last step for HW init */
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dw_writel(pspi, ssienr, 0x1);
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/* Set the default configuration */
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max3110_write_config();
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/* Register the kmsg dumper */
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if (!dumper_registered) {
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dw_dumper.dump = dw_kmsg_dump;
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kmsg_dump_register(&dw_dumper);
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dumper_registered = 1;
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}
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}
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/* Slave select should be called in the read/write function */
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static void early_mrst_spi_putc(char c)
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{
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unsigned int timeout;
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u32 sr;
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timeout = MRST_SPI_TIMEOUT;
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/* Early putc needs to make sure the TX FIFO is not full */
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while (--timeout) {
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sr = dw_readl(pspi, sr);
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if (!(sr & SR_TF_NOT_FULL))
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cpu_relax();
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else
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break;
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}
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if (!timeout)
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pr_warning("MRST earlycon: timed out\n");
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else
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max3110_write_data(c);
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}
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/* Early SPI only uses polling mode */
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static void early_mrst_spi_write(struct console *con, const char *str, unsigned n)
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{
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int i;
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for (i = 0; i < n && *str; i++) {
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if (*str == '\n')
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early_mrst_spi_putc('\r');
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early_mrst_spi_putc(*str);
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str++;
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}
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}
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struct console early_mrst_console = {
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.name = "earlymrst",
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.write = early_mrst_spi_write,
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.flags = CON_PRINTBUFFER,
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.index = -1,
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};
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/*
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* Following is the early console based on Medfield HSU (High
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* Speed UART) device.
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*/
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#define HSU_PORT2_PADDR 0xffa28180
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static void __iomem *phsu;
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void hsu_early_console_init(void)
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{
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u8 lcr;
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phsu = (void *)set_fixmap_offset_nocache(FIX_EARLYCON_MEM_BASE,
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HSU_PORT2_PADDR);
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/* Disable FIFO */
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writeb(0x0, phsu + UART_FCR);
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/* Set to default 115200 bps, 8n1 */
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lcr = readb(phsu + UART_LCR);
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writeb((0x80 | lcr), phsu + UART_LCR);
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writeb(0x18, phsu + UART_DLL);
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writeb(lcr, phsu + UART_LCR);
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writel(0x3600, phsu + UART_MUL*4);
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writeb(0x8, phsu + UART_MCR);
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writeb(0x7, phsu + UART_FCR);
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writeb(0x3, phsu + UART_LCR);
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/* Clear IRQ status */
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readb(phsu + UART_LSR);
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readb(phsu + UART_RX);
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readb(phsu + UART_IIR);
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readb(phsu + UART_MSR);
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/* Enable FIFO */
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writeb(0x7, phsu + UART_FCR);
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}
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#define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
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static void early_hsu_putc(char ch)
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{
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unsigned int timeout = 10000; /* 10ms */
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u8 status;
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while (--timeout) {
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status = readb(phsu + UART_LSR);
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if (status & BOTH_EMPTY)
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break;
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udelay(1);
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}
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/* Only write the char when there was no timeout */
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if (timeout)
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writeb(ch, phsu + UART_TX);
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}
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static void early_hsu_write(struct console *con, const char *str, unsigned n)
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{
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int i;
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for (i = 0; i < n && *str; i++) {
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if (*str == '\n')
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early_hsu_putc('\r');
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early_hsu_putc(*str);
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str++;
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}
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}
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struct console early_hsu_console = {
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.name = "earlyhsu",
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.write = early_hsu_write,
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.flags = CON_PRINTBUFFER,
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.index = -1,
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};
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|
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@ -34,7 +34,7 @@
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#ifdef CONFIG_X86_LOCAL_APIC
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static unsigned long sfi_lapic_addr __initdata = APIC_DEFAULT_PHYS_BASE;
|
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void __init mp_sfi_register_lapic_address(unsigned long address)
|
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static void __init mp_sfi_register_lapic_address(unsigned long address)
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{
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mp_lapic_addr = address;
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|
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@ -46,7 +46,7 @@ void __init mp_sfi_register_lapic_address(unsigned long address)
|
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}
|
||||
|
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/* All CPUs enumerated by SFI must be present and enabled */
|
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void __cpuinit mp_sfi_register_lapic(u8 id)
|
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static void __cpuinit mp_sfi_register_lapic(u8 id)
|
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{
|
||||
if (MAX_APICS - id <= 0) {
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pr_warning("Processor #%d invalid (max %d)\n",
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||||
|
|
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|||
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