ARM: dts: sun8i-a83t: Add thermal trip points/cooling maps
This enables passive cooling by down-regulating CPU voltage and frequency. For the trip points, I used values from the BSP code directly. The critical trip point value is 30°C above the maximum recommended ambient temperature (70°C) for the SoC from the datasheet, so there's some headroom even at such a high ambient temperature. Signed-off-by: Ondrej Jirman <megous@megous.com> Signed-off-by: Maxime Ripard <maxime@cerno.tech>
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@ -72,7 +72,7 @@
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#cooling-cells = <2>;
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#cooling-cells = <2>;
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};
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};
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cpu@1 {
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cpu1: cpu@1 {
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compatible = "arm,cortex-a7";
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compatible = "arm,cortex-a7";
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device_type = "cpu";
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device_type = "cpu";
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clocks = <&ccu CLK_C0CPUX>;
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clocks = <&ccu CLK_C0CPUX>;
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@ -83,7 +83,7 @@
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#cooling-cells = <2>;
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#cooling-cells = <2>;
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};
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};
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cpu@2 {
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cpu2: cpu@2 {
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compatible = "arm,cortex-a7";
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compatible = "arm,cortex-a7";
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device_type = "cpu";
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device_type = "cpu";
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clocks = <&ccu CLK_C0CPUX>;
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clocks = <&ccu CLK_C0CPUX>;
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@ -94,7 +94,7 @@
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#cooling-cells = <2>;
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#cooling-cells = <2>;
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};
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};
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cpu@3 {
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cpu3: cpu@3 {
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compatible = "arm,cortex-a7";
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compatible = "arm,cortex-a7";
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device_type = "cpu";
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device_type = "cpu";
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clocks = <&ccu CLK_C0CPUX>;
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clocks = <&ccu CLK_C0CPUX>;
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@ -116,7 +116,7 @@
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#cooling-cells = <2>;
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#cooling-cells = <2>;
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};
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};
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cpu@101 {
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cpu101: cpu@101 {
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compatible = "arm,cortex-a7";
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compatible = "arm,cortex-a7";
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device_type = "cpu";
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device_type = "cpu";
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clocks = <&ccu CLK_C1CPUX>;
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clocks = <&ccu CLK_C1CPUX>;
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@ -127,7 +127,7 @@
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#cooling-cells = <2>;
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#cooling-cells = <2>;
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};
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};
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cpu@102 {
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cpu102: cpu@102 {
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compatible = "arm,cortex-a7";
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compatible = "arm,cortex-a7";
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device_type = "cpu";
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device_type = "cpu";
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clocks = <&ccu CLK_C1CPUX>;
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clocks = <&ccu CLK_C1CPUX>;
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@ -138,7 +138,7 @@
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#cooling-cells = <2>;
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#cooling-cells = <2>;
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};
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};
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cpu@103 {
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cpu103: cpu@103 {
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compatible = "arm,cortex-a7";
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compatible = "arm,cortex-a7";
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device_type = "cpu";
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device_type = "cpu";
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clocks = <&ccu CLK_C1CPUX>;
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clocks = <&ccu CLK_C1CPUX>;
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@ -1188,12 +1188,60 @@
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polling-delay-passive = <0>;
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polling-delay-passive = <0>;
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polling-delay = <0>;
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polling-delay = <0>;
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thermal-sensors = <&ths 0>;
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thermal-sensors = <&ths 0>;
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trips {
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cpu0_hot: cpu-hot {
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temperature = <80000>;
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hysteresis = <2000>;
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type = "passive";
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};
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cpu0_very_hot: cpu-very-hot {
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temperature = <100000>;
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hysteresis = <0>;
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type = "critical";
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};
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};
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cooling-maps {
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cpu-hot-limit {
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trip = <&cpu0_hot>;
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cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
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<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
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<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
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<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
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};
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};
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};
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};
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cpu1_thermal: cpu1-thermal {
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cpu1_thermal: cpu1-thermal {
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polling-delay-passive = <0>;
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polling-delay-passive = <0>;
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polling-delay = <0>;
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polling-delay = <0>;
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thermal-sensors = <&ths 1>;
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thermal-sensors = <&ths 1>;
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trips {
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cpu1_hot: cpu-hot {
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temperature = <80000>;
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hysteresis = <2000>;
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type = "passive";
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};
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cpu1_very_hot: cpu-very-hot {
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temperature = <100000>;
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hysteresis = <0>;
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type = "critical";
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};
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};
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cooling-maps {
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cpu-hot-limit {
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trip = <&cpu1_hot>;
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cooling-device = <&cpu100 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
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<&cpu101 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
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<&cpu102 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
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<&cpu103 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
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};
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};
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};
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};
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gpu_thermal: gpu-thermal {
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gpu_thermal: gpu-thermal {
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