iwlwifi: pcie: configure more RFH settings
Fine tune RFH registers further: * Set default queue explicitly * Set RFH to drop frames exceeding RB size * Set the maximum rx transfer size to DRAM to 128 instead of 64 Signed-off-by: Sara Sharon <sara.sharon@intel.com> Signed-off-by: Emmanuel Grumbach <emmanuel.grumbach@intel.com>
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88076015f8
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@ -6,7 +6,7 @@
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* GPL LICENSE SUMMARY
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*
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* Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved.
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* Copyright(c) 2015 Intel Deutschland GmbH
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* Copyright(c) 2015 - 2016 Intel Deutschland GmbH
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of version 2 of the GNU General Public License as
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@ -32,7 +32,7 @@
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* BSD LICENSE
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*
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* Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved.
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* Copyright(c) 2015 Intel Deutschland GmbH
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* Copyright(c) 2015 - 2016 Intel Deutschland GmbH
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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@ -368,20 +368,24 @@ static inline unsigned int FH_MEM_CBBC_QUEUE(unsigned int chnl)
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#define RFH_RXF_DMA_RBDCB_SIZE_512 (0x9 << RFH_RXF_DMA_RBDCB_SIZE_POS)
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#define RFH_RXF_DMA_RBDCB_SIZE_1024 (0xA << RFH_RXF_DMA_RBDCB_SIZE_POS)
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#define RFH_RXF_DMA_RBDCB_SIZE_2048 (0xB << RFH_RXF_DMA_RBDCB_SIZE_POS)
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#define RFH_RXF_DMA_MIN_RB_SIZE_MASK (0x03000000) /* bit 24-25 */
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#define RFH_RXF_DMA_MIN_RB_SIZE_MASK (0x03000000) /* bit 24-25 */
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#define RFH_RXF_DMA_MIN_RB_SIZE_POS 24
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#define RFH_RXF_DMA_MIN_RB_4_8 (3 << RFH_RXF_DMA_MIN_RB_SIZE_POS)
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#define RFH_RXF_DMA_SINGLE_FRAME_MASK (0x20000000) /* bit 29 */
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#define RFH_DMA_EN_MASK (0xC0000000) /* bits 30-31*/
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#define RFH_DMA_EN_ENABLE_VAL BIT(31)
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#define RFH_RXF_DMA_MIN_RB_4_8 (3 << RFH_RXF_DMA_MIN_RB_SIZE_POS)
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#define RFH_RXF_DMA_DROP_TOO_LARGE_MASK (0x04000000) /* bit 26 */
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#define RFH_RXF_DMA_SINGLE_FRAME_MASK (0x20000000) /* bit 29 */
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#define RFH_DMA_EN_MASK (0xC0000000) /* bits 30-31*/
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#define RFH_DMA_EN_ENABLE_VAL BIT(31)
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#define RFH_RXF_RXQ_ACTIVE 0xA0980C
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#define RFH_GEN_CFG 0xA09800
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#define RFH_GEN_CFG_SERVICE_DMA_SNOOP BIT(0)
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#define RFH_GEN_CFG_RFH_DMA_SNOOP BIT(1)
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#define RFH_GEN_CFG_RB_CHUNK_SIZE BIT(4) /* 0 - 64B, 1- 128B */
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#define RFH_GEN_CFG_DEFAULT_RXQ_NUM_MASK 0xF00
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#define RFH_GEN_CFG_SERVICE_DMA_SNOOP BIT(0)
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#define RFH_GEN_CFG_RFH_DMA_SNOOP BIT(1)
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#define DEFAULT_RXQ_NUM 8
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#define RFH_GEN_CFG_DEFAULT_RXQ_NUM_POS 8
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#define DEFAULT_RXQ_NUM 0
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/* end of 9000 rx series registers */
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@ -783,16 +783,26 @@ static void iwl_pcie_rx_mq_hw_init(struct iwl_trans *trans)
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* Single frame mode
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* Rx buffer size 4 or 8k or 12k
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* Min RB size 4 or 8
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* Drop frames that exceed RB size
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* 512 RBDs
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*/
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iwl_write_prph(trans, RFH_RXF_DMA_CFG,
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RFH_DMA_EN_ENABLE_VAL |
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rb_size | RFH_RXF_DMA_SINGLE_FRAME_MASK |
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RFH_RXF_DMA_MIN_RB_4_8 |
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RFH_RXF_DMA_DROP_TOO_LARGE_MASK |
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RFH_RXF_DMA_RBDCB_SIZE_512);
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/*
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* Activate DMA snooping.
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* Set RX DMA chunk size to 128 bit
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* Default queue is 0
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*/
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iwl_write_prph(trans, RFH_GEN_CFG, RFH_GEN_CFG_RFH_DMA_SNOOP |
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RFH_GEN_CFG_SERVICE_DMA_SNOOP);
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RFH_GEN_CFG_RB_CHUNK_SIZE |
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(DEFAULT_RXQ_NUM << RFH_GEN_CFG_DEFAULT_RXQ_NUM_POS) |
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RFH_GEN_CFG_SERVICE_DMA_SNOOP);
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/* Enable the relevant rx queues */
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iwl_write_prph(trans, RFH_RXF_RXQ_ACTIVE, enabled);
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/* Set interrupt coalescing timer to default (2048 usecs) */
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