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arm64: dts: exynos: TM2 - add support for GScaler devices 

This patch adds device nodes for GScaler devices to Exynos5433 SoC dtsi
and proper initial clock configuration to TM2 dts.

Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
This commit is contained in:
Marek Szyprowski 2016-11-18 13:23:11 +01:00 коммит произвёл Krzysztof Kozlowski
Родитель 4eb74a7c24
Коммит 88b9ca09c5
2 изменённых файлов: 79 добавлений и 0 удалений
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10
arch/arm64/boot/dts/exynos/exynos5433-tm2.dts
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@ -23,6 +23,9 @@
compatible = "samsung,tm2", "samsung,exynos5433";
aliases {
gsc0 = &gsc_0;
gsc1 = &gsc_1;
gsc2 = &gsc_2;
pinctrl0 = &pinctrl_alive;
pinctrl1 = &pinctrl_aud;
pinctrl2 = &pinctrl_cpif;
@ -186,6 +189,13 @@
<66700000>, <66700000>;
};
&cmu_gscl {
assigned-clocks = <&cmu_gscl CLK_MOUT_ACLK_GSCL_111_USER>,
<&cmu_gscl CLK_MOUT_ACLK_GSCL_333_USER>;
assigned-clock-parents = <&cmu_top CLK_ACLK_GSCL_111>,
<&cmu_top CLK_ACLK_GSCL_333>;
};
&cpu0 {
cpu-supply = <&buck3_reg>;
};

69
arch/arm64/boot/dts/exynos/exynos5433.dtsi
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@ -805,6 +805,45 @@
reg = <0x145f0000 0x1038>;
};
gsc_0: video-scaler@13C00000 {
compatible = "samsung,exynos5433-gsc";
reg = <0x13c00000 0x1000>;
interrupts = <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "pclk", "aclk", "aclk_xiu",
"aclk_gsclbend";
clocks = <&cmu_gscl CLK_PCLK_GSCL0>,
<&cmu_gscl CLK_ACLK_GSCL0>,
<&cmu_gscl CLK_ACLK_XIU_GSCLX>,
<&cmu_gscl CLK_ACLK_GSCLBEND_333>;
iommus = <&sysmmu_gscl0>;
};
gsc_1: video-scaler@13C10000 {
compatible = "samsung,exynos5433-gsc";
reg = <0x13c10000 0x1000>;
interrupts = <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "pclk", "aclk", "aclk_xiu",
"aclk_gsclbend";
clocks = <&cmu_gscl CLK_PCLK_GSCL1>,
<&cmu_gscl CLK_ACLK_GSCL1>,
<&cmu_gscl CLK_ACLK_XIU_GSCLX>,
<&cmu_gscl CLK_ACLK_GSCLBEND_333>;
iommus = <&sysmmu_gscl1>;
};
gsc_2: video-scaler@13C20000 {
compatible = "samsung,exynos5433-gsc";
reg = <0x13c20000 0x1000>;
interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "pclk", "aclk", "aclk_xiu",
"aclk_gsclbend";
clocks = <&cmu_gscl CLK_PCLK_GSCL2>,
<&cmu_gscl CLK_ACLK_GSCL2>,
<&cmu_gscl CLK_ACLK_XIU_GSCLX>,
<&cmu_gscl CLK_ACLK_GSCLBEND_333>;
iommus = <&sysmmu_gscl2>;
};
sysmmu_decon0x: sysmmu@0x13a00000 {
compatible = "samsung,exynos-sysmmu";
reg = <0x13a00000 0x1000>;
@ -825,6 +864,36 @@
#iommu-cells = <0>;
};
sysmmu_gscl0: sysmmu@0x13C80000 {
compatible = "samsung,exynos-sysmmu";
reg = <0x13C80000 0x1000>;
interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "aclk", "pclk";
clocks = <&cmu_gscl CLK_ACLK_SMMU_GSCL0>,
<&cmu_gscl CLK_PCLK_SMMU_GSCL0>;
#iommu-cells = <0>;
};
sysmmu_gscl1: sysmmu@0x13C90000 {
compatible = "samsung,exynos-sysmmu";
reg = <0x13C90000 0x1000>;
interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "aclk", "pclk";
clocks = <&cmu_gscl CLK_ACLK_SMMU_GSCL1>,
<&cmu_gscl CLK_PCLK_SMMU_GSCL1>;
#iommu-cells = <0>;
};
sysmmu_gscl2: sysmmu@0x13CA0000 {
compatible = "samsung,exynos-sysmmu";
reg = <0x13CA0000 0x1000>;
interrupts = <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "aclk", "pclk";
clocks = <&cmu_gscl CLK_ACLK_SMMU_GSCL2>,
<&cmu_gscl CLK_PCLK_SMMU_GSCL2>;
#iommu-cells = <0>;
};
serial_0: serial@14c10000 {
compatible = "samsung,exynos5433-uart";
reg = <0x14c10000 0x100>;