arm64: dts: freescale: Add support for phyBOARD-Pollux-i.MX8MP
Add initial support for phyBOARD-Pollux-i.MX8MP. Supported basic features: * eMMC * i2c EEPROM * i2c RTC * i2c LED * PMIC * debug UART * SD card * 1Gbit Ethernet (fec) * watchdog Signed-off-by: Teresa Remmet <t.remmet@phytec.de> Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
This commit is contained in:
Teresa Remmet
Shawn Guo
Родитель
6f30b27c5e
Коммит
88f7f6bcca
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@ -42,6 +42,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mn-evk.dtb
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dtb-$(CONFIG_ARCH_MXC) += imx8mn-ddr4-evk.dtb
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dtb-$(CONFIG_ARCH_MXC) += imx8mn-var-som-symphony.dtb
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dtb-$(CONFIG_ARCH_MXC) += imx8mp-evk.dtb
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dtb-$(CONFIG_ARCH_MXC) += imx8mp-phyboard-pollux-rdk.dtb
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dtb-$(CONFIG_ARCH_MXC) += imx8mq-evk.dtb
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dtb-$(CONFIG_ARCH_MXC) += imx8mq-hummingboard-pulse.dtb
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dtb-$(CONFIG_ARCH_MXC) += imx8mq-librem5-devkit.dtb
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@ -0,0 +1,161 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2020 PHYTEC Messtechnik GmbH
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* Author: Teresa Remmet <t.remmet@phytec.de>
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*/
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/dts-v1/;
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#include <dt-bindings/leds/leds-pca9532.h>
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#include <dt-bindings/pwm/pwm.h>
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#include "imx8mp-phycore-som.dtsi"
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/ {
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model = "PHYTEC phyBOARD-Pollux i.MX8MP";
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compatible = "phytec,imx8mp-phyboard-pollux-rdk",
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"phytec,imx8mp-phycore-som", "fsl,imx8mp";
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chosen {
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stdout-path = &uart2;
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};
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reg_usdhc2_vmmc: regulator-usdhc2 {
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compatible = "regulator-fixed";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
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regulator-name = "VSD_3V3";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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startup-delay-us = <100>;
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off-on-delay-us = <12000>;
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};
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};
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&i2c2 {
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clock-frequency = <400000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c2>;
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pinctrl-1 = <&pinctrl_i2c2_gpio>;
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sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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status = "okay";
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eeprom@51 {
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compatible = "atmel,24c02";
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reg = <0x51>;
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pagesize = <16>;
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};
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leds@62 {
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compatible = "nxp,pca9533";
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reg = <0x62>;
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led1 {
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type = <PCA9532_TYPE_LED>;
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};
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led2 {
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type = <PCA9532_TYPE_LED>;
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};
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led3 {
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type = <PCA9532_TYPE_LED>;
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};
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};
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};
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&snvs_pwrkey {
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status = "okay";
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};
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/* debug console */
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&uart2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart2>;
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status = "okay";
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};
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/* SD-Card */
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&usdhc2 {
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pinctrl-names = "default", "state_100mhz", "state_200mhz";
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pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_pins>;
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pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_pins>;
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pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_pins>;
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cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
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vmmc-supply = <®_usdhc2_vmmc>;
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bus-width = <4>;
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status = "okay";
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};
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&iomuxc {
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pinctrl_i2c2: i2c2grp {
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fsl,pins = <
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MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c3
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MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c3
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>;
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};
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pinctrl_i2c2_gpio: i2c2gpiogrp {
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fsl,pins = <
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MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16 0x1e3
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MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0x1e3
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>;
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};
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pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
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fsl,pins = <
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MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x41
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>;
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};
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pinctrl_uart2: uart2grp {
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fsl,pins = <
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MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x49
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MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x49
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>;
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};
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pinctrl_usdhc2_pins: usdhc2-gpiogrp {
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fsl,pins = <
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MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4
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>;
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};
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pinctrl_usdhc2: usdhc2grp {
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fsl,pins = <
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MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190
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MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0
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MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0
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MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0
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MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0
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MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0
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MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
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>;
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};
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pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
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fsl,pins = <
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MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194
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MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4
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MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4
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MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4
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MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4
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MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4
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MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
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>;
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};
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pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
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fsl,pins = <
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MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196
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MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6
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MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6
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MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6
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MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6
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MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6
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MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
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>;
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};
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};
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@ -0,0 +1,293 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2020 PHYTEC Messtechnik GmbH
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* Author: Teresa Remmet <t.remmet@phytec.de>
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*/
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#include <dt-bindings/net/ti-dp83867.h>
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#include "imx8mp.dtsi"
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/ {
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model = "PHYTEC phyCORE-i.MX8MP";
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compatible = "phytec,imx8mp-phycore-som", "fsl,imx8mp";
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aliases {
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rtc0 = &rv3028;
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rtc1 = &snvs_rtc;
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};
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memory@40000000 {
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device_type = "memory";
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reg = <0x0 0x40000000 0 0x80000000>;
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};
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};
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&A53_0 {
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cpu-supply = <&buck2>;
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};
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&A53_1 {
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cpu-supply = <&buck2>;
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};
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&A53_2 {
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cpu-supply = <&buck2>;
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};
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&A53_3 {
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cpu-supply = <&buck2>;
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};
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/* ethernet 1 */
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&fec {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_fec>;
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phy-mode = "rgmii-id";
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phy-handle = <ðphy1>;
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fsl,magic-packet;
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status = "okay";
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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ethphy1: ethernet-phy@0 {
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <0>;
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interrupt-parent = <&gpio1>;
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interrupts = <15 IRQ_TYPE_EDGE_FALLING>;
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ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
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ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
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ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
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ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
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enet-phy-lane-no-swap;
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};
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};
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};
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&i2c1 {
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clock-frequency = <400000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c1>;
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pinctrl-1 = <&pinctrl_i2c1_gpio>;
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sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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status = "okay";
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pmic: pmic@25 {
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reg = <0x25>;
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compatible = "nxp,pca9450c";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_pmic>;
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interrupt-parent = <&gpio4>;
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interrupts = <18 IRQ_TYPE_LEVEL_LOW>;
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regulators {
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buck1: BUCK1 {
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regulator-compatible = "BUCK1";
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regulator-min-microvolt = <600000>;
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regulator-max-microvolt = <2187500>;
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regulator-boot-on;
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regulator-always-on;
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regulator-ramp-delay = <3125>;
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};
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buck2: BUCK2 {
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regulator-compatible = "BUCK2";
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regulator-min-microvolt = <600000>;
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regulator-max-microvolt = <2187500>;
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regulator-boot-on;
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regulator-always-on;
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regulator-ramp-delay = <3125>;
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};
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buck4: BUCK4 {
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regulator-compatible = "BUCK4";
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regulator-min-microvolt = <600000>;
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regulator-max-microvolt = <3400000>;
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regulator-boot-on;
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regulator-always-on;
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};
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buck5: BUCK5 {
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regulator-compatible = "BUCK5";
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regulator-min-microvolt = <600000>;
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regulator-max-microvolt = <3400000>;
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regulator-boot-on;
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regulator-always-on;
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};
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buck6: BUCK6 {
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regulator-compatible = "BUCK6";
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regulator-min-microvolt = <600000>;
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regulator-max-microvolt = <3400000>;
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regulator-boot-on;
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regulator-always-on;
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};
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ldo1: LDO1 {
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regulator-compatible = "LDO1";
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regulator-min-microvolt = <1600000>;
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regulator-max-microvolt = <3300000>;
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regulator-boot-on;
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regulator-always-on;
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};
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ldo2: LDO2 {
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regulator-compatible = "LDO2";
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regulator-min-microvolt = <800000>;
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regulator-max-microvolt = <1150000>;
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regulator-boot-on;
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regulator-always-on;
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};
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ldo3: LDO3 {
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regulator-compatible = "LDO3";
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regulator-min-microvolt = <800000>;
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regulator-max-microvolt = <3300000>;
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regulator-boot-on;
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regulator-always-on;
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};
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ldo4: LDO4 {
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regulator-compatible = "LDO4";
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regulator-min-microvolt = <800000>;
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regulator-max-microvolt = <3300000>;
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regulator-boot-on;
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regulator-always-on;
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};
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ldo5: LDO5 {
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regulator-compatible = "LDO5";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <3300000>;
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};
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};
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};
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eeprom@51 {
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compatible = "atmel,24c32";
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reg = <0x51>;
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pagesize = <32>;
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};
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rv3028: rtc@52 {
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compatible = "microcrystal,rv3028";
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reg = <0x52>;
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trickle-resistor-ohms = <3000>;
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};
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};
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/* eMMC */
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&usdhc3 {
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pinctrl-names = "default", "state_100mhz", "state_200mhz";
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pinctrl-0 = <&pinctrl_usdhc3>;
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pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
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pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
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bus-width = <8>;
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non-removable;
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status = "okay";
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};
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&wdog1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_wdog>;
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fsl,ext-reset-output;
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status = "okay";
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};
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&iomuxc {
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pinctrl_fec: fecgrp {
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fsl,pins = <
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MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x3
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MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x3
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MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x91
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MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x91
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MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x91
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MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x91
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MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x91
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MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x91
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MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x1f
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MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x1f
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MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x1f
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MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x1f
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MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x1f
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MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x1f
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MX8MP_IOMUXC_GPIO1_IO15__GPIO1_IO15 0x11
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>;
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};
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pinctrl_i2c1: i2c1grp {
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fsl,pins = <
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MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c3
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MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c3
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>;
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};
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pinctrl_i2c1_gpio: i2c1gpiogrp {
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fsl,pins = <
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MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14 0x1e3
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MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15 0x1e3
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>;
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};
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pinctrl_pmic: pmicirqgrp {
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fsl,pins = <
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MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0x141
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>;
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};
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pinctrl_usdhc3: usdhc3grp {
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fsl,pins = <
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MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190
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MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0
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MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0
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MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0
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MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0
|
||||
MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0
|
||||
MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0
|
||||
MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0
|
||||
MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0
|
||||
MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0
|
||||
MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
|
||||
fsl,pins = <
|
||||
MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194
|
||||
MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4
|
||||
MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4
|
||||
MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4
|
||||
MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4
|
||||
MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4
|
||||
MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4
|
||||
MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4
|
||||
MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4
|
||||
MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4
|
||||
MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
|
||||
fsl,pins = <
|
||||
MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196
|
||||
MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6
|
||||
MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6
|
||||
MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6
|
||||
MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6
|
||||
MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6
|
||||
MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6
|
||||
MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6
|
||||
MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6
|
||||
MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6
|
||||
MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_wdog: wdoggrp {
|
||||
fsl,pins = <
|
||||
MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0xc6
|
||||
>;
|
||||
};
|
||||
};
|
||||
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