Documentation/i2c: Checkpatch cleanup
Remove all trailing whitespace in Documentation/i2c. Signed-off-by: Andrea Gelmini <andrea.gelmini@gelma.net> Signed-off-by: Jean Delvare <khali@linux-fr.org>
This commit is contained in:
Andrea Gelmini
Jean Delvare
Родитель
aef4b9aaae
Коммит
89140f4157
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@ -6,12 +6,12 @@ Supported adapters:
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http://www.ali.com.tw/eng/support/datasheet_request.php
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Authors:
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Frodo Looijaard <frodol@dds.nl>,
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Frodo Looijaard <frodol@dds.nl>,
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Philip Edelbrock <phil@netroedge.com>,
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Mark D. Studebaker <mdsxyz123@yahoo.com>,
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Dan Eaton <dan.eaton@rocketlogix.com>,
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Stephen Rousset<stephen.rousset@rocketlogix.com>
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Description
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-----------
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@ -18,7 +18,7 @@ For an overview of these chips see http://www.acerlabs.com
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The M1563 southbridge is deceptively similar to the M1533, with a few
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notable exceptions. One of those happens to be the fact they upgraded the
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i2c core to be SMBus 2.0 compliant, and happens to be almost identical to
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the i2c controller found in the Intel 801 south bridges.
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the i2c controller found in the Intel 801 south bridges.
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Features
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--------
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@ -6,8 +6,8 @@ Supported adapters:
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http://www.ali.com.tw/eng/support/datasheet_request.php
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Authors:
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Frodo Looijaard <frodol@dds.nl>,
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Philip Edelbrock <phil@netroedge.com>,
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Frodo Looijaard <frodol@dds.nl>,
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Philip Edelbrock <phil@netroedge.com>,
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Mark D. Studebaker <mdsxyz123@yahoo.com>
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Module Parameters
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@ -40,10 +40,10 @@ M1541 and M1543C South Bridges.
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The M1543C is a South bridge for desktop systems.
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The M1541 is a South bridge for portable systems.
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They are part of the following ALI chipsets:
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* "Aladdin Pro 2" includes the M1621 Slot 1 North bridge with AGP and
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* "Aladdin Pro 2" includes the M1621 Slot 1 North bridge with AGP and
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100MHz CPU Front Side bus
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* "Aladdin V" includes the M1541 Socket 7 North bridge with AGP and 100MHz
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* "Aladdin V" includes the M1541 Socket 7 North bridge with AGP and 100MHz
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CPU Front Side bus
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Some Aladdin V motherboards:
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Asus P5A
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@ -77,7 +77,7 @@ output of lspci will show something similar to the following:
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** then run lspci.
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** If you see the 1533 and 5229 devices but NOT the 7101 device,
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** then you must enable ACPI, the PMU, SMB, or something similar
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** in the BIOS.
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** in the BIOS.
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** The driver won't work if it can't find the M7101 device.
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The SMB controller is part of the M7101 device, which is an ACPI-compliant
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@ -87,8 +87,8 @@ The whole M7101 device has to be enabled for the SMB to work. You can't
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just enable the SMB alone. The SMB and the ACPI have separate I/O spaces.
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We make sure that the SMB is enabled. We leave the ACPI alone.
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Features
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--------
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Features
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--------
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This driver controls the SMB Host only. The SMB Slave
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controller on the M15X3 is not enabled. This driver does not use
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@ -1,10 +1,10 @@
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Kernel driver i2c-pca-isa
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Supported adapters:
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This driver supports ISA boards using the Philips PCA 9564
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Parallel bus to I2C bus controller
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This driver supports ISA boards using the Philips PCA 9564
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Parallel bus to I2C bus controller
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Author: Ian Campbell <icampbell@arcom.com>, Arcom Control Systems
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Author: Ian Campbell <icampbell@arcom.com>, Arcom Control Systems
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Module Parameters
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-----------------
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@ -12,12 +12,12 @@ Module Parameters
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* base int
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I/O base address
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* irq int
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IRQ interrupt
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* clock int
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IRQ interrupt
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* clock int
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Clock rate as described in table 1 of PCA9564 datasheet
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Description
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-----------
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This driver supports ISA boards using the Philips PCA 9564
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Parallel bus to I2C bus controller
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This driver supports ISA boards using the Philips PCA 9564
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Parallel bus to I2C bus controller
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@ -1,41 +1,41 @@
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Kernel driver i2c-sis5595
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Authors:
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Authors:
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Frodo Looijaard <frodol@dds.nl>,
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Mark D. Studebaker <mdsxyz123@yahoo.com>,
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Philip Edelbrock <phil@netroedge.com>
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Philip Edelbrock <phil@netroedge.com>
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Supported adapters:
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* Silicon Integrated Systems Corp. SiS5595 Southbridge
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Datasheet: Publicly available at the Silicon Integrated Systems Corp. site.
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Note: all have mfr. ID 0x1039.
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Note: all have mfr. ID 0x1039.
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SUPPORTED PCI ID
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5595 0008
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Note: these chips contain a 0008 device which is incompatible with the
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5595. We recognize these by the presence of the listed
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"blacklist" PCI ID and refuse to load.
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NOT SUPPORTED PCI ID BLACKLIST PCI ID
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540 0008 0540
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550 0008 0550
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5513 0008 5511
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5581 0008 5597
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5582 0008 5597
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5597 0008 5597
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5598 0008 5597/5598
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630 0008 0630
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645 0008 0645
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646 0008 0646
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648 0008 0648
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650 0008 0650
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651 0008 0651
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730 0008 0730
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735 0008 0735
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745 0008 0745
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746 0008 0746
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SUPPORTED PCI ID
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5595 0008
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Note: these chips contain a 0008 device which is incompatible with the
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5595. We recognize these by the presence of the listed
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"blacklist" PCI ID and refuse to load.
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NOT SUPPORTED PCI ID BLACKLIST PCI ID
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540 0008 0540
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550 0008 0550
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5513 0008 5511
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5581 0008 5597
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5582 0008 5597
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5597 0008 5597
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5598 0008 5597/5598
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630 0008 0630
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645 0008 0645
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646 0008 0646
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648 0008 0648
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650 0008 0650
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651 0008 0651
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730 0008 0730
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735 0008 0735
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745 0008 0745
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746 0008 0746
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Module Parameters
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-----------------
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@ -14,9 +14,9 @@ Module Parameters
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* force = [1|0] Forcibly enable the SIS630. DANGEROUS!
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This can be interesting for chipsets not named
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above to check if it works for you chipset, but DANGEROUS!
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* high_clock = [1|0] Forcibly set Host Master Clock to 56KHz (default,
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what your BIOS use). DANGEROUS! This should be a bit
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* high_clock = [1|0] Forcibly set Host Master Clock to 56KHz (default,
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what your BIOS use). DANGEROUS! This should be a bit
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faster, but freeze some systems (i.e. my Laptop).
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@ -44,6 +44,6 @@ Philip Edelbrock <phil@netroedge.com>
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- testing SiS730 support
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Mark M. Hoffman <mhoffman@lightlink.com>
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- bug fixes
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To anyone else which I forgot here ;), thanks!
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@ -1,17 +1,17 @@
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The I2C protocol knows about two kinds of device addresses: normal 7 bit
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The I2C protocol knows about two kinds of device addresses: normal 7 bit
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addresses, and an extended set of 10 bit addresses. The sets of addresses
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do not intersect: the 7 bit address 0x10 is not the same as the 10 bit
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address 0x10 (though a single device could respond to both of them). You
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select a 10 bit address by adding an extra byte after the address
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byte:
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S Addr7 Rd/Wr ....
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S Addr7 Rd/Wr ....
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becomes
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S 11110 Addr10 Rd/Wr
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S is the start bit, Rd/Wr the read/write bit, and if you count the number
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of bits, you will see the there are 8 after the S bit for 7 bit addresses,
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and 16 after the S bit for 10 bit addresses.
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WARNING! The current 10 bit address support is EXPERIMENTAL. There are
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WARNING! The current 10 bit address support is EXPERIMENTAL. There are
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several places in the code that will cause SEVERE PROBLEMS with 10 bit
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addresses, even though there is some basic handling and hooks. Also,
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almost no supported adapter handles the 10 bit addresses correctly.
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