iwlwifi: yoyo: support for new DBGI_SRAM region

new region handling is added  for dump collection.

Signed-off-by: Mukesh Sisodiya <mukesh.sisodiya@intel.com>
Signed-off-by: Luca Coelho <luciano.coelho@intel.com>
Link: https://lore.kernel.org/r/iwlwifi.20210819183728.af9a24b82396.I53c5f82bd2d0f56fd699e3841c922082d99f1c90@changeid
Signed-off-by: Luca Coelho <luciano.coelho@intel.com>
This commit is contained in:
Mukesh Sisodiya 2021-08-19 18:40:33 +03:00 коммит произвёл Luca Coelho
Родитель 4e110e799c
Коммит 89639e06d0
3 изменённых файлов: 47 добавлений и 0 удалений

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@ -129,6 +129,7 @@ struct iwl_fw_ini_region_internal_buffer {
* &IWL_FW_INI_REGION_PERIPHERY_PHY, &IWL_FW_INI_REGION_PERIPHERY_AUX, * &IWL_FW_INI_REGION_PERIPHERY_PHY, &IWL_FW_INI_REGION_PERIPHERY_AUX,
* &IWL_FW_INI_REGION_PAGING, &IWL_FW_INI_REGION_CSR, * &IWL_FW_INI_REGION_PAGING, &IWL_FW_INI_REGION_CSR,
* &IWL_FW_INI_REGION_DRAM_IMR and &IWL_FW_INI_REGION_PCI_IOSF_CONFIG * &IWL_FW_INI_REGION_DRAM_IMR and &IWL_FW_INI_REGION_PCI_IOSF_CONFIG
* &IWL_FW_INI_REGION_DBGI_SRAM, &FW_TLV_DEBUG_REGION_TYPE_DBGI_SRAM,
* @fifos: fifos configuration. Used by &IWL_FW_INI_REGION_TXF and * @fifos: fifos configuration. Used by &IWL_FW_INI_REGION_TXF and
* &IWL_FW_INI_REGION_RXF * &IWL_FW_INI_REGION_RXF
* @err_table: error table configuration. Used by * @err_table: error table configuration. Used by
@ -295,6 +296,7 @@ enum iwl_fw_ini_buffer_location {
* @IWL_FW_INI_REGION_DRAM_IMR: IMR memory * @IWL_FW_INI_REGION_DRAM_IMR: IMR memory
* @IWL_FW_INI_REGION_PCI_IOSF_CONFIG: PCI/IOSF config * @IWL_FW_INI_REGION_PCI_IOSF_CONFIG: PCI/IOSF config
* @IWL_FW_INI_REGION_SPECIAL_DEVICE_MEMORY: special device memory * @IWL_FW_INI_REGION_SPECIAL_DEVICE_MEMORY: special device memory
* @IWL_FW_INI_REGION_DBGI_SRAM: periphery registers of DBGI SRAM
* @IWL_FW_INI_REGION_NUM: number of region types * @IWL_FW_INI_REGION_NUM: number of region types
*/ */
enum iwl_fw_ini_region_type { enum iwl_fw_ini_region_type {
@ -316,6 +318,7 @@ enum iwl_fw_ini_region_type {
IWL_FW_INI_REGION_DRAM_IMR, IWL_FW_INI_REGION_DRAM_IMR,
IWL_FW_INI_REGION_PCI_IOSF_CONFIG, IWL_FW_INI_REGION_PCI_IOSF_CONFIG,
IWL_FW_INI_REGION_SPECIAL_DEVICE_MEMORY, IWL_FW_INI_REGION_SPECIAL_DEVICE_MEMORY,
IWL_FW_INI_REGION_DBGI_SRAM,
IWL_FW_INI_REGION_NUM IWL_FW_INI_REGION_NUM
}; /* FW_TLV_DEBUG_REGION_TYPE_API_E */ }; /* FW_TLV_DEBUG_REGION_TYPE_API_E */

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@ -1517,6 +1517,37 @@ iwl_dump_ini_special_mem_iter(struct iwl_fw_runtime *fwrt,
return sizeof(*range) + le32_to_cpu(range->range_data_size); return sizeof(*range) + le32_to_cpu(range->range_data_size);
} }
static int
iwl_dump_ini_dbgi_sram_iter(struct iwl_fw_runtime *fwrt,
struct iwl_dump_ini_region_data *reg_data,
void *range_ptr, int idx)
{
struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data;
struct iwl_fw_ini_error_dump_range *range = range_ptr;
__le32 *val = range->data;
u32 prph_data;
int i;
if (!iwl_trans_grab_nic_access(fwrt->trans))
return -EBUSY;
range->range_data_size = reg->dev_addr.size;
iwl_write_prph_no_grab(fwrt->trans, DBGI_SRAM_TARGET_ACCESS_CFG,
DBGI_SRAM_TARGET_ACCESS_CFG_RESET_ADDRESS_MSK);
for (i = 0; i < (le32_to_cpu(reg->dev_addr.size) / 4); i++) {
prph_data = iwl_read_prph(fwrt->trans, (i % 2) ?
DBGI_SRAM_TARGET_ACCESS_RDATA_MSB :
DBGI_SRAM_TARGET_ACCESS_RDATA_LSB);
if (prph_data == 0x5a5a5a5a) {
iwl_trans_release_nic_access(fwrt->trans);
return -EBUSY;
}
*val++ = cpu_to_le32(prph_data);
}
iwl_trans_release_nic_access(fwrt->trans);
return sizeof(*range) + le32_to_cpu(range->range_data_size);
}
static int iwl_dump_ini_fw_pkt_iter(struct iwl_fw_runtime *fwrt, static int iwl_dump_ini_fw_pkt_iter(struct iwl_fw_runtime *fwrt,
struct iwl_dump_ini_region_data *reg_data, struct iwl_dump_ini_region_data *reg_data,
void *range_ptr, int idx) void *range_ptr, int idx)
@ -2189,6 +2220,12 @@ static const struct iwl_dump_ini_mem_ops iwl_dump_ini_region_ops[] = {
.fill_mem_hdr = iwl_dump_ini_special_mem_fill_header, .fill_mem_hdr = iwl_dump_ini_special_mem_fill_header,
.fill_range = iwl_dump_ini_special_mem_iter, .fill_range = iwl_dump_ini_special_mem_iter,
}, },
[IWL_FW_INI_REGION_DBGI_SRAM] = {
.get_num_of_ranges = iwl_dump_ini_mem_ranges,
.get_size = iwl_dump_ini_mem_get_size,
.fill_mem_hdr = iwl_dump_ini_mem_fill_header,
.fill_range = iwl_dump_ini_dbgi_sram_iter,
},
}; };
static u32 iwl_dump_ini_trigger(struct iwl_fw_runtime *fwrt, static u32 iwl_dump_ini_trigger(struct iwl_fw_runtime *fwrt,

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@ -348,6 +348,13 @@
#define RFIC_REG_RD 0xAD0470 #define RFIC_REG_RD 0xAD0470
#define WFPM_CTRL_REG 0xA03030 #define WFPM_CTRL_REG 0xA03030
#define WFPM_GP2 0xA030B4 #define WFPM_GP2 0xA030B4
/* DBGI SRAM Register details */
#define DBGI_SRAM_TARGET_ACCESS_CFG 0x00A2E14C
#define DBGI_SRAM_TARGET_ACCESS_CFG_RESET_ADDRESS_MSK 0x10000
#define DBGI_SRAM_TARGET_ACCESS_RDATA_LSB 0x00A2E154
#define DBGI_SRAM_TARGET_ACCESS_RDATA_MSB 0x00A2E158
enum { enum {
ENABLE_WFPM = BIT(31), ENABLE_WFPM = BIT(31),
WFPM_AUX_CTL_AUX_IF_MAC_OWNER_MSK = 0x80000000, WFPM_AUX_CTL_AUX_IF_MAC_OWNER_MSK = 0x80000000,