Merge branch 'topic/xilinx' into for-linus
This commit is contained in:
Vinod Koul
Коммит
896e041e8e
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@ -28,6 +28,7 @@
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/iopoll.h>
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#include <linux/module.h>
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#include <linux/of_address.h>
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#include <linux/of_dma.h>
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@ -190,8 +191,7 @@ struct xilinx_vdma_tx_descriptor {
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* @desc_offset: TX descriptor registers offset
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* @lock: Descriptor operation lock
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* @pending_list: Descriptors waiting
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* @active_desc: Active descriptor
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* @allocated_desc: Allocated descriptor
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* @active_list: Descriptors ready to submit
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* @done_list: Complete descriptors
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* @common: DMA common channel
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* @desc_pool: Descriptors pool
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@ -206,6 +206,7 @@ struct xilinx_vdma_tx_descriptor {
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* @tasklet: Cleanup work after irq
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* @config: Device configuration info
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* @flush_on_fsync: Flush on Frame sync
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* @desc_pendingcount: Descriptor pending count
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*/
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struct xilinx_vdma_chan {
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struct xilinx_vdma_device *xdev;
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@ -213,8 +214,7 @@ struct xilinx_vdma_chan {
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u32 desc_offset;
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spinlock_t lock;
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struct list_head pending_list;
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struct xilinx_vdma_tx_descriptor *active_desc;
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struct xilinx_vdma_tx_descriptor *allocated_desc;
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struct list_head active_list;
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struct list_head done_list;
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struct dma_chan common;
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struct dma_pool *desc_pool;
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@ -229,6 +229,7 @@ struct xilinx_vdma_chan {
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struct tasklet_struct tasklet;
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struct xilinx_vdma_config config;
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bool flush_on_fsync;
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u32 desc_pendingcount;
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};
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/**
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@ -254,6 +255,9 @@ struct xilinx_vdma_device {
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container_of(chan, struct xilinx_vdma_chan, common)
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#define to_vdma_tx_descriptor(tx) \
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container_of(tx, struct xilinx_vdma_tx_descriptor, async_tx)
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#define xilinx_vdma_poll_timeout(chan, reg, val, cond, delay_us, timeout_us) \
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readl_poll_timeout(chan->xdev->regs + chan->ctrl_offset + reg, val, \
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cond, delay_us, timeout_us)
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/* IO accessors */
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static inline u32 vdma_read(struct xilinx_vdma_chan *chan, u32 reg)
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@ -342,19 +346,11 @@ static struct xilinx_vdma_tx_descriptor *
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xilinx_vdma_alloc_tx_descriptor(struct xilinx_vdma_chan *chan)
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{
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struct xilinx_vdma_tx_descriptor *desc;
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unsigned long flags;
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if (chan->allocated_desc)
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return chan->allocated_desc;
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desc = kzalloc(sizeof(*desc), GFP_KERNEL);
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if (!desc)
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return NULL;
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spin_lock_irqsave(&chan->lock, flags);
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chan->allocated_desc = desc;
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spin_unlock_irqrestore(&chan->lock, flags);
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INIT_LIST_HEAD(&desc->segments);
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return desc;
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@ -412,9 +408,7 @@ static void xilinx_vdma_free_descriptors(struct xilinx_vdma_chan *chan)
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xilinx_vdma_free_desc_list(chan, &chan->pending_list);
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xilinx_vdma_free_desc_list(chan, &chan->done_list);
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xilinx_vdma_free_tx_descriptor(chan, chan->active_desc);
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chan->active_desc = NULL;
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xilinx_vdma_free_desc_list(chan, &chan->active_list);
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spin_unlock_irqrestore(&chan->lock, flags);
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}
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@ -560,18 +554,17 @@ static bool xilinx_vdma_is_idle(struct xilinx_vdma_chan *chan)
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*/
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static void xilinx_vdma_halt(struct xilinx_vdma_chan *chan)
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{
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int loop = XILINX_VDMA_LOOP_COUNT;
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int err;
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u32 val;
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vdma_ctrl_clr(chan, XILINX_VDMA_REG_DMACR, XILINX_VDMA_DMACR_RUNSTOP);
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||||
/* Wait for the hardware to halt */
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||||
do {
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||||
if (vdma_ctrl_read(chan, XILINX_VDMA_REG_DMASR) &
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||||
XILINX_VDMA_DMASR_HALTED)
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break;
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} while (loop--);
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err = xilinx_vdma_poll_timeout(chan, XILINX_VDMA_REG_DMASR, val,
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(val & XILINX_VDMA_DMASR_HALTED), 0,
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XILINX_VDMA_LOOP_COUNT);
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if (!loop) {
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if (err) {
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dev_err(chan->dev, "Cannot stop channel %p: %x\n",
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chan, vdma_ctrl_read(chan, XILINX_VDMA_REG_DMASR));
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chan->err = true;
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@ -586,18 +579,17 @@ static void xilinx_vdma_halt(struct xilinx_vdma_chan *chan)
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*/
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static void xilinx_vdma_start(struct xilinx_vdma_chan *chan)
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{
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int loop = XILINX_VDMA_LOOP_COUNT;
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int err;
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u32 val;
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vdma_ctrl_set(chan, XILINX_VDMA_REG_DMACR, XILINX_VDMA_DMACR_RUNSTOP);
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/* Wait for the hardware to start */
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do {
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if (!(vdma_ctrl_read(chan, XILINX_VDMA_REG_DMASR) &
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||||
XILINX_VDMA_DMASR_HALTED))
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break;
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} while (loop--);
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err = xilinx_vdma_poll_timeout(chan, XILINX_VDMA_REG_DMASR, val,
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!(val & XILINX_VDMA_DMASR_HALTED), 0,
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XILINX_VDMA_LOOP_COUNT);
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if (!loop) {
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if (err) {
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dev_err(chan->dev, "Cannot start channel %p: %x\n",
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chan, vdma_ctrl_read(chan, XILINX_VDMA_REG_DMASR));
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@ -614,45 +606,39 @@ static void xilinx_vdma_start(struct xilinx_vdma_chan *chan)
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static void xilinx_vdma_start_transfer(struct xilinx_vdma_chan *chan)
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{
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struct xilinx_vdma_config *config = &chan->config;
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struct xilinx_vdma_tx_descriptor *desc;
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unsigned long flags;
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struct xilinx_vdma_tx_descriptor *desc, *tail_desc;
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u32 reg;
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struct xilinx_vdma_tx_segment *head, *tail = NULL;
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struct xilinx_vdma_tx_segment *tail_segment;
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||||
/* This function was invoked with lock held */
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if (chan->err)
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return;
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spin_lock_irqsave(&chan->lock, flags);
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/* There's already an active descriptor, bail out. */
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if (chan->active_desc)
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goto out_unlock;
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if (list_empty(&chan->pending_list))
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goto out_unlock;
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return;
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desc = list_first_entry(&chan->pending_list,
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struct xilinx_vdma_tx_descriptor, node);
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tail_desc = list_last_entry(&chan->pending_list,
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struct xilinx_vdma_tx_descriptor, node);
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tail_segment = list_last_entry(&tail_desc->segments,
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struct xilinx_vdma_tx_segment, node);
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/* If it is SG mode and hardware is busy, cannot submit */
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if (chan->has_sg && xilinx_vdma_is_running(chan) &&
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!xilinx_vdma_is_idle(chan)) {
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dev_dbg(chan->dev, "DMA controller still busy\n");
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goto out_unlock;
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return;
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}
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/*
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||||
* If hardware is idle, then all descriptors on the running lists are
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||||
* done, start new transfers
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||||
*/
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if (chan->has_sg) {
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head = list_first_entry(&desc->segments,
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struct xilinx_vdma_tx_segment, node);
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tail = list_entry(desc->segments.prev,
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struct xilinx_vdma_tx_segment, node);
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vdma_ctrl_write(chan, XILINX_VDMA_REG_CURDESC, head->phys);
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}
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if (chan->has_sg)
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vdma_ctrl_write(chan, XILINX_VDMA_REG_CURDESC,
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desc->async_tx.phys);
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/* Configure the hardware using info in the config structure */
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reg = vdma_ctrl_read(chan, XILINX_VDMA_REG_DMACR);
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@ -662,6 +648,10 @@ static void xilinx_vdma_start_transfer(struct xilinx_vdma_chan *chan)
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else
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reg &= ~XILINX_VDMA_DMACR_FRAMECNT_EN;
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/* Configure channel to allow number frame buffers */
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vdma_ctrl_write(chan, XILINX_VDMA_REG_FRMSTORE,
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chan->desc_pendingcount);
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/*
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* With SG, start with circular mode, so that BDs can be fetched.
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* In direct register mode, if not parking, enable circular mode
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@ -690,16 +680,19 @@ static void xilinx_vdma_start_transfer(struct xilinx_vdma_chan *chan)
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xilinx_vdma_start(chan);
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if (chan->err)
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goto out_unlock;
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return;
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/* Start the transfer */
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if (chan->has_sg) {
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vdma_ctrl_write(chan, XILINX_VDMA_REG_TAILDESC, tail->phys);
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vdma_ctrl_write(chan, XILINX_VDMA_REG_TAILDESC,
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tail_segment->phys);
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} else {
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struct xilinx_vdma_tx_segment *segment, *last = NULL;
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int i = 0;
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list_for_each_entry(segment, &desc->segments, node) {
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list_for_each_entry(desc, &chan->pending_list, node) {
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segment = list_first_entry(&desc->segments,
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||||
struct xilinx_vdma_tx_segment, node);
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vdma_desc_write(chan,
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XILINX_VDMA_REG_START_ADDRESS(i++),
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segment->hw.buf_addr);
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||||
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|
@ -707,7 +700,7 @@ static void xilinx_vdma_start_transfer(struct xilinx_vdma_chan *chan)
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|||
}
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||||
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||||
if (!last)
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goto out_unlock;
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||||
return;
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||||
/* HW expects these parameters to be same for one transaction */
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vdma_desc_write(chan, XILINX_VDMA_REG_HSIZE, last->hw.hsize);
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|
@ -716,11 +709,8 @@ static void xilinx_vdma_start_transfer(struct xilinx_vdma_chan *chan)
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|||
vdma_desc_write(chan, XILINX_VDMA_REG_VSIZE, last->hw.vsize);
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||||
}
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||||
|
||||
list_del(&desc->node);
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||||
chan->active_desc = desc;
|
||||
|
||||
out_unlock:
|
||||
spin_unlock_irqrestore(&chan->lock, flags);
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||||
list_splice_tail_init(&chan->pending_list, &chan->active_list);
|
||||
chan->desc_pendingcount = 0;
|
||||
}
|
||||
|
||||
/**
|
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|
|
@ -730,8 +720,11 @@ out_unlock:
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|||
static void xilinx_vdma_issue_pending(struct dma_chan *dchan)
|
||||
{
|
||||
struct xilinx_vdma_chan *chan = to_xilinx_chan(dchan);
|
||||
unsigned long flags;
|
||||
|
||||
spin_lock_irqsave(&chan->lock, flags);
|
||||
xilinx_vdma_start_transfer(chan);
|
||||
spin_unlock_irqrestore(&chan->lock, flags);
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
@ -742,24 +735,17 @@ static void xilinx_vdma_issue_pending(struct dma_chan *dchan)
|
|||
*/
|
||||
static void xilinx_vdma_complete_descriptor(struct xilinx_vdma_chan *chan)
|
||||
{
|
||||
struct xilinx_vdma_tx_descriptor *desc;
|
||||
unsigned long flags;
|
||||
struct xilinx_vdma_tx_descriptor *desc, *next;
|
||||
|
||||
spin_lock_irqsave(&chan->lock, flags);
|
||||
/* This function was invoked with lock held */
|
||||
if (list_empty(&chan->active_list))
|
||||
return;
|
||||
|
||||
desc = chan->active_desc;
|
||||
if (!desc) {
|
||||
dev_dbg(chan->dev, "no running descriptors\n");
|
||||
goto out_unlock;
|
||||
list_for_each_entry_safe(desc, next, &chan->active_list, node) {
|
||||
list_del(&desc->node);
|
||||
dma_cookie_complete(&desc->async_tx);
|
||||
list_add_tail(&desc->node, &chan->done_list);
|
||||
}
|
||||
|
||||
dma_cookie_complete(&desc->async_tx);
|
||||
list_add_tail(&desc->node, &chan->done_list);
|
||||
|
||||
chan->active_desc = NULL;
|
||||
|
||||
out_unlock:
|
||||
spin_unlock_irqrestore(&chan->lock, flags);
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
@ -770,21 +756,17 @@ out_unlock:
|
|||
*/
|
||||
static int xilinx_vdma_reset(struct xilinx_vdma_chan *chan)
|
||||
{
|
||||
int loop = XILINX_VDMA_LOOP_COUNT;
|
||||
int err;
|
||||
u32 tmp;
|
||||
|
||||
vdma_ctrl_set(chan, XILINX_VDMA_REG_DMACR, XILINX_VDMA_DMACR_RESET);
|
||||
|
||||
tmp = vdma_ctrl_read(chan, XILINX_VDMA_REG_DMACR) &
|
||||
XILINX_VDMA_DMACR_RESET;
|
||||
|
||||
/* Wait for the hardware to finish reset */
|
||||
do {
|
||||
tmp = vdma_ctrl_read(chan, XILINX_VDMA_REG_DMACR) &
|
||||
XILINX_VDMA_DMACR_RESET;
|
||||
} while (loop-- && tmp);
|
||||
err = xilinx_vdma_poll_timeout(chan, XILINX_VDMA_REG_DMACR, tmp,
|
||||
!(tmp & XILINX_VDMA_DMACR_RESET), 0,
|
||||
XILINX_VDMA_LOOP_COUNT);
|
||||
|
||||
if (!loop) {
|
||||
if (err) {
|
||||
dev_err(chan->dev, "reset timeout, cr %x, sr %x\n",
|
||||
vdma_ctrl_read(chan, XILINX_VDMA_REG_DMACR),
|
||||
vdma_ctrl_read(chan, XILINX_VDMA_REG_DMASR));
|
||||
|
|
@ -793,7 +775,7 @@ static int xilinx_vdma_reset(struct xilinx_vdma_chan *chan)
|
|||
|
||||
chan->err = false;
|
||||
|
||||
return 0;
|
||||
return err;
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
@ -870,14 +852,54 @@ static irqreturn_t xilinx_vdma_irq_handler(int irq, void *data)
|
|||
}
|
||||
|
||||
if (status & XILINX_VDMA_DMASR_FRM_CNT_IRQ) {
|
||||
spin_lock(&chan->lock);
|
||||
xilinx_vdma_complete_descriptor(chan);
|
||||
xilinx_vdma_start_transfer(chan);
|
||||
spin_unlock(&chan->lock);
|
||||
}
|
||||
|
||||
tasklet_schedule(&chan->tasklet);
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
/**
|
||||
* append_desc_queue - Queuing descriptor
|
||||
* @chan: Driver specific dma channel
|
||||
* @desc: dma transaction descriptor
|
||||
*/
|
||||
static void append_desc_queue(struct xilinx_vdma_chan *chan,
|
||||
struct xilinx_vdma_tx_descriptor *desc)
|
||||
{
|
||||
struct xilinx_vdma_tx_segment *tail_segment;
|
||||
struct xilinx_vdma_tx_descriptor *tail_desc;
|
||||
|
||||
if (list_empty(&chan->pending_list))
|
||||
goto append;
|
||||
|
||||
/*
|
||||
* Add the hardware descriptor to the chain of hardware descriptors
|
||||
* that already exists in memory.
|
||||
*/
|
||||
tail_desc = list_last_entry(&chan->pending_list,
|
||||
struct xilinx_vdma_tx_descriptor, node);
|
||||
tail_segment = list_last_entry(&tail_desc->segments,
|
||||
struct xilinx_vdma_tx_segment, node);
|
||||
tail_segment->hw.next_desc = (u32)desc->async_tx.phys;
|
||||
|
||||
/*
|
||||
* Add the software descriptor and all children to the list
|
||||
* of pending transactions
|
||||
*/
|
||||
append:
|
||||
list_add_tail(&desc->node, &chan->pending_list);
|
||||
chan->desc_pendingcount++;
|
||||
|
||||
if (unlikely(chan->desc_pendingcount > chan->num_frms)) {
|
||||
dev_dbg(chan->dev, "desc pendingcount is too high\n");
|
||||
chan->desc_pendingcount = chan->num_frms;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* xilinx_vdma_tx_submit - Submit DMA transaction
|
||||
* @tx: Async transaction descriptor
|
||||
|
|
@ -906,11 +928,8 @@ static dma_cookie_t xilinx_vdma_tx_submit(struct dma_async_tx_descriptor *tx)
|
|||
|
||||
cookie = dma_cookie_assign(tx);
|
||||
|
||||
/* Append the transaction to the pending transactions queue. */
|
||||
list_add_tail(&desc->node, &chan->pending_list);
|
||||
|
||||
/* Free the allocated desc */
|
||||
chan->allocated_desc = NULL;
|
||||
/* Put this transaction onto the tail of the pending queue */
|
||||
append_desc_queue(chan, desc);
|
||||
|
||||
spin_unlock_irqrestore(&chan->lock, flags);
|
||||
|
||||
|
|
@ -973,13 +992,6 @@ xilinx_vdma_dma_prep_interleaved(struct dma_chan *dchan,
|
|||
else
|
||||
hw->buf_addr = xt->src_start;
|
||||
|
||||
/* Link the previous next descriptor to current */
|
||||
if (!list_empty(&desc->segments)) {
|
||||
prev = list_last_entry(&desc->segments,
|
||||
struct xilinx_vdma_tx_segment, node);
|
||||
prev->hw.next_desc = segment->phys;
|
||||
}
|
||||
|
||||
/* Insert the segment into the descriptor segments list. */
|
||||
list_add_tail(&segment->node, &desc->segments);
|
||||
|
||||
|
|
@ -988,7 +1000,7 @@ xilinx_vdma_dma_prep_interleaved(struct dma_chan *dchan,
|
|||
/* Link the last hardware descriptor with the first. */
|
||||
segment = list_first_entry(&desc->segments,
|
||||
struct xilinx_vdma_tx_segment, node);
|
||||
prev->hw.next_desc = segment->phys;
|
||||
desc->async_tx.phys = segment->phys;
|
||||
|
||||
return &desc->async_tx;
|
||||
|
||||
|
|
@ -1127,10 +1139,12 @@ static int xilinx_vdma_chan_probe(struct xilinx_vdma_device *xdev,
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chan->dev = xdev->dev;
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chan->xdev = xdev;
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chan->has_sg = xdev->has_sg;
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chan->desc_pendingcount = 0x0;
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spin_lock_init(&chan->lock);
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INIT_LIST_HEAD(&chan->pending_list);
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INIT_LIST_HEAD(&chan->done_list);
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INIT_LIST_HEAD(&chan->active_list);
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/* Retrieve the channel properties from the device tree */
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has_dre = of_property_read_bool(node, "xlnx,include-dre");
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