[PATCH] arm26: fixup asm statement in kernel/fiq.c
Signed-off-by: Alexey Dobriyan <adobriyan@gmail.com> Acked-by: Ian Molton <spyro@f2s.com> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
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a16ef86c87
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896f361bd2
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@ -104,14 +104,14 @@ void set_fiq_regs(struct pt_regs *regs)
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{
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register unsigned long tmp, tmp2;
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__asm__ volatile (
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"mov %0, pc
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bic %1, %0, #0x3
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orr %1, %1, %3
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teqp %1, #0 @ select FIQ mode
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mov r0, r0
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ldmia %2, {r8 - r14}
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teqp %0, #0 @ return to SVC mode
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mov r0, r0"
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"mov %0, pc \n"
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"bic %1, %0, #0x3 \n"
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"orr %1, %1, %3 \n"
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"teqp %1, #0 @ select FIQ mode \n"
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"mov r0, r0 \n"
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"ldmia %2, {r8 - r14} \n"
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"teqp %0, #0 @ return to SVC mode \n"
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"mov r0, r0 "
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: "=&r" (tmp), "=&r" (tmp2)
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: "r" (®s->ARM_r8), "I" (PSR_I_BIT | PSR_F_BIT | MODE_FIQ26)
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/* These registers aren't modified by the above code in a way
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@ -125,14 +125,14 @@ void get_fiq_regs(struct pt_regs *regs)
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{
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register unsigned long tmp, tmp2;
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__asm__ volatile (
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"mov %0, pc
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bic %1, %0, #0x3
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orr %1, %1, %3
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teqp %1, #0 @ select FIQ mode
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mov r0, r0
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stmia %2, {r8 - r14}
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teqp %0, #0 @ return to SVC mode
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mov r0, r0"
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"mov %0, pc \n"
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"bic %1, %0, #0x3 \n"
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"orr %1, %1, %3 \n"
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"teqp %1, #0 @ select FIQ mode \n"
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"mov r0, r0 \n"
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"stmia %2, {r8 - r14} \n"
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"teqp %0, #0 @ return to SVC mode \n"
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"mov r0, r0 "
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: "=&r" (tmp), "=&r" (tmp2)
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: "r" (®s->ARM_r8), "I" (PSR_I_BIT | PSR_F_BIT | MODE_FIQ26)
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/* These registers aren't modified by the above code in a way
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