powerpc/pci: Pull ppc32 PCI features into common
Some of the PCI features we have in ppc32 we will need on ppc64 platforms in the future. These include support for: * ppc_md.pci_exclude_device * indirect config cycles * early config cycles We also simplified the logic in fake_pci_bus() to assume it will always get a valid pci_controller. Since all current callers seem to pass it one. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Grant Likely <grant.likely@secretlab.ca> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
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@ -209,14 +209,14 @@ struct machdep_calls {
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/*
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* optional PCI "hooks"
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*/
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/* Called in indirect_* to avoid touching devices */
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int (*pci_exclude_device)(struct pci_controller *, unsigned char, unsigned char);
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/* Called at then very end of pcibios_init() */
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void (*pcibios_after_init)(void);
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#endif /* CONFIG_PPC32 */
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/* Called in indirect_* to avoid touching devices */
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int (*pci_exclude_device)(struct pci_controller *, unsigned char, unsigned char);
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/* Called after PPC generic resource fixup to perform
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machine specific fixups */
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void (*pcibios_fixup_resources)(struct pci_dev *);
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@ -77,9 +77,7 @@ struct pci_controller {
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int first_busno;
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int last_busno;
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#ifndef CONFIG_PPC64
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int self_busno;
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#endif
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void __iomem *io_base_virt;
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#ifdef CONFIG_PPC64
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@ -104,7 +102,6 @@ struct pci_controller {
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unsigned int __iomem *cfg_addr;
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void __iomem *cfg_data;
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#ifndef CONFIG_PPC64
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/*
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* Used for variants of PCI indirect handling and possible quirks:
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* SET_CFG_TYPE - used on 4xx or any PHB that does explicit type0/1
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@ -128,7 +125,6 @@ struct pci_controller {
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#define PPC_INDIRECT_TYPE_BIG_ENDIAN 0x00000010
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#define PPC_INDIRECT_TYPE_BROKEN_MRM 0x00000020
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u32 indirect_type;
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#endif /* !CONFIG_PPC64 */
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/* Currently, we limit ourselves to 1 IO range and 3 mem
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* ranges since the common pci_bus structure can't handle more
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*/
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@ -146,21 +142,6 @@ struct pci_controller {
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#endif /* CONFIG_PPC64 */
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};
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#ifndef CONFIG_PPC64
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static inline struct pci_controller *pci_bus_to_host(const struct pci_bus *bus)
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{
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return bus->sysdata;
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}
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static inline int isa_vaddr_is_ioport(void __iomem *address)
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{
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/* No specific ISA handling on ppc32 at this stage, it
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* all goes through PCI
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*/
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return 0;
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}
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/* These are used for config access before all the PCI probing
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has been done. */
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extern int early_read_config_byte(struct pci_controller *hose, int bus,
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@ -182,6 +163,22 @@ extern int early_find_capability(struct pci_controller *hose, int bus,
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extern void setup_indirect_pci(struct pci_controller* hose,
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resource_size_t cfg_addr,
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resource_size_t cfg_data, u32 flags);
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#ifndef CONFIG_PPC64
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static inline struct pci_controller *pci_bus_to_host(const struct pci_bus *bus)
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{
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return bus->sysdata;
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}
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static inline int isa_vaddr_is_ioport(void __iomem *address)
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{
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/* No specific ISA handling on ppc32 at this stage, it
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* all goes through PCI
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*/
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return 0;
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}
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#else /* CONFIG_PPC64 */
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/*
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@ -1617,3 +1617,74 @@ void __devinit pcibios_setup_phb_resources(struct pci_controller *hose)
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(unsigned long)hose->io_base_virt - _IO_BASE);
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}
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/*
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* Null PCI config access functions, for the case when we can't
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* find a hose.
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*/
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#define NULL_PCI_OP(rw, size, type) \
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static int \
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null_##rw##_config_##size(struct pci_dev *dev, int offset, type val) \
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{ \
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return PCIBIOS_DEVICE_NOT_FOUND; \
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}
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static int
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null_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
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int len, u32 *val)
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{
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return PCIBIOS_DEVICE_NOT_FOUND;
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}
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static int
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null_write_config(struct pci_bus *bus, unsigned int devfn, int offset,
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int len, u32 val)
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{
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return PCIBIOS_DEVICE_NOT_FOUND;
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}
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static struct pci_ops null_pci_ops =
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{
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.read = null_read_config,
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.write = null_write_config,
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};
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/*
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* These functions are used early on before PCI scanning is done
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* and all of the pci_dev and pci_bus structures have been created.
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*/
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static struct pci_bus *
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fake_pci_bus(struct pci_controller *hose, int busnr)
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{
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static struct pci_bus bus;
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if (hose == 0) {
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printk(KERN_ERR "Can't find hose for PCI bus %d!\n", busnr);
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}
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bus.number = busnr;
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bus.sysdata = hose;
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bus.ops = hose? hose->ops: &null_pci_ops;
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return &bus;
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}
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#define EARLY_PCI_OP(rw, size, type) \
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int early_##rw##_config_##size(struct pci_controller *hose, int bus, \
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int devfn, int offset, type value) \
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{ \
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return pci_bus_##rw##_config_##size(fake_pci_bus(hose, bus), \
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devfn, offset, value); \
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}
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EARLY_PCI_OP(read, byte, u8 *)
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EARLY_PCI_OP(read, word, u16 *)
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EARLY_PCI_OP(read, dword, u32 *)
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EARLY_PCI_OP(write, byte, u8)
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EARLY_PCI_OP(write, word, u16)
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EARLY_PCI_OP(write, dword, u32)
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extern int pci_bus_find_capability (struct pci_bus *bus, unsigned int devfn, int cap);
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int early_find_capability(struct pci_controller *hose, int bus, int devfn,
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int cap)
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{
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return pci_bus_find_capability(fake_pci_bus(hose, bus), devfn, cap);
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}
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@ -469,75 +469,4 @@ long sys_pciconfig_iobase(long which, unsigned long bus, unsigned long devfn)
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return result;
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}
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/*
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* Null PCI config access functions, for the case when we can't
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* find a hose.
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*/
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#define NULL_PCI_OP(rw, size, type) \
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static int \
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null_##rw##_config_##size(struct pci_dev *dev, int offset, type val) \
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{ \
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return PCIBIOS_DEVICE_NOT_FOUND; \
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}
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static int
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null_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
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int len, u32 *val)
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{
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return PCIBIOS_DEVICE_NOT_FOUND;
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}
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static int
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null_write_config(struct pci_bus *bus, unsigned int devfn, int offset,
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int len, u32 val)
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{
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return PCIBIOS_DEVICE_NOT_FOUND;
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}
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static struct pci_ops null_pci_ops =
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{
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.read = null_read_config,
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.write = null_write_config,
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};
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/*
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* These functions are used early on before PCI scanning is done
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* and all of the pci_dev and pci_bus structures have been created.
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*/
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static struct pci_bus *
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fake_pci_bus(struct pci_controller *hose, int busnr)
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{
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static struct pci_bus bus;
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if (hose == 0) {
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hose = pci_bus_to_hose(busnr);
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if (hose == 0)
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printk(KERN_ERR "Can't find hose for PCI bus %d!\n", busnr);
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}
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bus.number = busnr;
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bus.sysdata = hose;
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bus.ops = hose? hose->ops: &null_pci_ops;
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return &bus;
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}
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#define EARLY_PCI_OP(rw, size, type) \
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int early_##rw##_config_##size(struct pci_controller *hose, int bus, \
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int devfn, int offset, type value) \
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{ \
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return pci_bus_##rw##_config_##size(fake_pci_bus(hose, bus), \
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devfn, offset, value); \
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}
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EARLY_PCI_OP(read, byte, u8 *)
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EARLY_PCI_OP(read, word, u16 *)
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EARLY_PCI_OP(read, dword, u32 *)
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EARLY_PCI_OP(write, byte, u8)
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EARLY_PCI_OP(write, word, u16)
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EARLY_PCI_OP(write, dword, u32)
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extern int pci_bus_find_capability (struct pci_bus *bus, unsigned int devfn, int cap);
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int early_find_capability(struct pci_controller *hose, int bus, int devfn,
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int cap)
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{
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return pci_bus_find_capability(fake_pci_bus(hose, bus), devfn, cap);
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}
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