staging: comedi: hwrdv_apci1500: absorb private header
The header file hwdrv_apci1500.h is only included by the source file hwrdv_apci1500.c. Absorb the header into the source and delete the header. Signed-off-by: H Hartley Sweeten <hsweeten@visionengravers.com> Cc: Ian Abbott <abbotti@mev.co.uk> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
H Hartley Sweeten
Greg Kroah-Hartman
Родитель
618a97e8a2
Коммит
89c6d64020
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@ -45,7 +45,105 @@ You should also find the complete GPL in the COPYING file accompanying this sour
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+----------+-----------+------------------------------------------------+
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*/
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#include "hwdrv_apci1500.h"
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/********* Definitions for APCI-1500 card *****/
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/* Card Specific information */
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#define APCI1500_ADDRESS_RANGE 4
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/* DIGITAL INPUT-OUTPUT DEFINE */
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#define APCI1500_DIGITAL_OP 2
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#define APCI1500_DIGITAL_IP 0
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#define APCI1500_AND 2
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#define APCI1500_OR 4
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#define APCI1500_OR_PRIORITY 6
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#define APCI1500_CLK_SELECT 0
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#define COUNTER1 0
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#define COUNTER2 1
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#define COUNTER3 2
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#define APCI1500_COUNTER 0x20
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#define APCI1500_TIMER 0
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#define APCI1500_WATCHDOG 0
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#define APCI1500_SINGLE 0
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#define APCI1500_CONTINUOUS 0x80
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#define APCI1500_DISABLE 0
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#define APCI1500_ENABLE 1
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#define APCI1500_SOFTWARE_TRIGGER 0x4
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#define APCI1500_HARDWARE_TRIGGER 0x10
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#define APCI1500_SOFTWARE_GATE 0
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#define APCI1500_HARDWARE_GATE 0x8
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#define START 0
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#define STOP 1
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#define TRIGGER 2
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/*
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* Zillog I/O enumeration
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*/
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enum {
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APCI1500_Z8536_PORT_C,
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APCI1500_Z8536_PORT_B,
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APCI1500_Z8536_PORT_A,
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APCI1500_Z8536_CONTROL_REGISTER
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};
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/*
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* Z8536 CIO Internal Address
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*/
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enum {
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APCI1500_RW_MASTER_INTERRUPT_CONTROL,
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APCI1500_RW_MASTER_CONFIGURATION_CONTROL,
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APCI1500_RW_PORT_A_INTERRUPT_CONTROL,
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APCI1500_RW_PORT_B_INTERRUPT_CONTROL,
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APCI1500_RW_TIMER_COUNTER_INTERRUPT_VECTOR,
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APCI1500_RW_PORT_C_DATA_PCITCH_POLARITY,
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APCI1500_RW_PORT_C_DATA_DIRECTION,
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APCI1500_RW_PORT_C_SPECIAL_IO_CONTROL,
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APCI1500_RW_PORT_A_COMMAND_AND_STATUS,
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APCI1500_RW_PORT_B_COMMAND_AND_STATUS,
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APCI1500_RW_CPT_TMR1_CMD_STATUS,
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APCI1500_RW_CPT_TMR2_CMD_STATUS,
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APCI1500_RW_CPT_TMR3_CMD_STATUS,
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APCI1500_RW_PORT_A_DATA,
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APCI1500_RW_PORT_B_DATA,
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APCI1500_RW_PORT_C_DATA,
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APCI1500_R_CPT_TMR1_VALUE_HIGH,
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APCI1500_R_CPT_TMR1_VALUE_LOW,
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APCI1500_R_CPT_TMR2_VALUE_HIGH,
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APCI1500_R_CPT_TMR2_VALUE_LOW,
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APCI1500_R_CPT_TMR3_VALUE_HIGH,
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APCI1500_R_CPT_TMR3_VALUE_LOW,
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APCI1500_RW_CPT_TMR1_TIME_CST_HIGH,
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APCI1500_RW_CPT_TMR1_TIME_CST_LOW,
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APCI1500_RW_CPT_TMR2_TIME_CST_HIGH,
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APCI1500_RW_CPT_TMR2_TIME_CST_LOW,
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APCI1500_RW_CPT_TMR3_TIME_CST_HIGH,
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APCI1500_RW_CPT_TMR3_TIME_CST_LOW,
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APCI1500_RW_CPT_TMR1_MODE_SPECIFICATION,
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APCI1500_RW_CPT_TMR2_MODE_SPECIFICATION,
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APCI1500_RW_CPT_TMR3_MODE_SPECIFICATION,
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APCI1500_R_CURRENT_VECTOR,
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APCI1500_RW_PORT_A_SPECIFICATION,
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APCI1500_RW_PORT_A_HANDSHAKE_SPECIFICATION,
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APCI1500_RW_PORT_A_DATA_PCITCH_POLARITY,
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APCI1500_RW_PORT_A_DATA_DIRECTION,
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APCI1500_RW_PORT_A_SPECIAL_IO_CONTROL,
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APCI1500_RW_PORT_A_PATTERN_POLARITY,
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APCI1500_RW_PORT_A_PATTERN_TRANSITION,
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APCI1500_RW_PORT_A_PATTERN_MASK,
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APCI1500_RW_PORT_B_SPECIFICATION,
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APCI1500_RW_PORT_B_HANDSHAKE_SPECIFICATION,
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APCI1500_RW_PORT_B_DATA_PCITCH_POLARITY,
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APCI1500_RW_PORT_B_DATA_DIRECTION,
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APCI1500_RW_PORT_B_SPECIAL_IO_CONTROL,
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APCI1500_RW_PORT_B_PATTERN_POLARITY,
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APCI1500_RW_PORT_B_PATTERN_TRANSITION,
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APCI1500_RW_PORT_B_PATTERN_MASK
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};
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static int i_TimerCounter1Init = 0;
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static int i_TimerCounter2Init = 0;
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@ -1,115 +0,0 @@
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/*
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* Copyright (C) 2004,2005 ADDI-DATA GmbH for the source code of this module.
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*
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* ADDI-DATA GmbH
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* Dieselstrasse 3
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* D-77833 Ottersweier
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* Tel: +19(0)7223/9493-0
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* Fax: +49(0)7223/9493-92
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* http://www.addi-data.com
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* info@addi-data.com
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the Free
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* Software Foundation; either version 2 of the License, or (at your option)
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* any later version.
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*/
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/********* Definitions for APCI-1500 card *****/
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/* Card Specific information */
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#define APCI1500_ADDRESS_RANGE 4
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/* DIGITAL INPUT-OUTPUT DEFINE */
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#define APCI1500_DIGITAL_OP 2
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#define APCI1500_DIGITAL_IP 0
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#define APCI1500_AND 2
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#define APCI1500_OR 4
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#define APCI1500_OR_PRIORITY 6
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#define APCI1500_CLK_SELECT 0
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#define COUNTER1 0
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#define COUNTER2 1
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#define COUNTER3 2
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#define APCI1500_COUNTER 0x20
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#define APCI1500_TIMER 0
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#define APCI1500_WATCHDOG 0
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#define APCI1500_SINGLE 0
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#define APCI1500_CONTINUOUS 0x80
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#define APCI1500_DISABLE 0
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#define APCI1500_ENABLE 1
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#define APCI1500_SOFTWARE_TRIGGER 0x4
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#define APCI1500_HARDWARE_TRIGGER 0x10
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#define APCI1500_SOFTWARE_GATE 0
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#define APCI1500_HARDWARE_GATE 0x8
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#define START 0
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#define STOP 1
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#define TRIGGER 2
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/*
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* Zillog I/O enumeration
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*/
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enum {
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APCI1500_Z8536_PORT_C,
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APCI1500_Z8536_PORT_B,
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APCI1500_Z8536_PORT_A,
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APCI1500_Z8536_CONTROL_REGISTER
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};
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/*
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* Z8536 CIO Internal Address
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*/
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enum {
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APCI1500_RW_MASTER_INTERRUPT_CONTROL,
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APCI1500_RW_MASTER_CONFIGURATION_CONTROL,
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APCI1500_RW_PORT_A_INTERRUPT_CONTROL,
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APCI1500_RW_PORT_B_INTERRUPT_CONTROL,
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APCI1500_RW_TIMER_COUNTER_INTERRUPT_VECTOR,
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APCI1500_RW_PORT_C_DATA_PCITCH_POLARITY,
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APCI1500_RW_PORT_C_DATA_DIRECTION,
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APCI1500_RW_PORT_C_SPECIAL_IO_CONTROL,
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APCI1500_RW_PORT_A_COMMAND_AND_STATUS,
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APCI1500_RW_PORT_B_COMMAND_AND_STATUS,
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APCI1500_RW_CPT_TMR1_CMD_STATUS,
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APCI1500_RW_CPT_TMR2_CMD_STATUS,
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APCI1500_RW_CPT_TMR3_CMD_STATUS,
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APCI1500_RW_PORT_A_DATA,
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APCI1500_RW_PORT_B_DATA,
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APCI1500_RW_PORT_C_DATA,
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APCI1500_R_CPT_TMR1_VALUE_HIGH,
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APCI1500_R_CPT_TMR1_VALUE_LOW,
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APCI1500_R_CPT_TMR2_VALUE_HIGH,
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APCI1500_R_CPT_TMR2_VALUE_LOW,
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APCI1500_R_CPT_TMR3_VALUE_HIGH,
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APCI1500_R_CPT_TMR3_VALUE_LOW,
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APCI1500_RW_CPT_TMR1_TIME_CST_HIGH,
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APCI1500_RW_CPT_TMR1_TIME_CST_LOW,
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APCI1500_RW_CPT_TMR2_TIME_CST_HIGH,
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APCI1500_RW_CPT_TMR2_TIME_CST_LOW,
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APCI1500_RW_CPT_TMR3_TIME_CST_HIGH,
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APCI1500_RW_CPT_TMR3_TIME_CST_LOW,
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APCI1500_RW_CPT_TMR1_MODE_SPECIFICATION,
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APCI1500_RW_CPT_TMR2_MODE_SPECIFICATION,
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APCI1500_RW_CPT_TMR3_MODE_SPECIFICATION,
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APCI1500_R_CURRENT_VECTOR,
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APCI1500_RW_PORT_A_SPECIFICATION,
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APCI1500_RW_PORT_A_HANDSHAKE_SPECIFICATION,
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APCI1500_RW_PORT_A_DATA_PCITCH_POLARITY,
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APCI1500_RW_PORT_A_DATA_DIRECTION,
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APCI1500_RW_PORT_A_SPECIAL_IO_CONTROL,
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APCI1500_RW_PORT_A_PATTERN_POLARITY,
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APCI1500_RW_PORT_A_PATTERN_TRANSITION,
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APCI1500_RW_PORT_A_PATTERN_MASK,
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APCI1500_RW_PORT_B_SPECIFICATION,
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APCI1500_RW_PORT_B_HANDSHAKE_SPECIFICATION,
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APCI1500_RW_PORT_B_DATA_PCITCH_POLARITY,
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APCI1500_RW_PORT_B_DATA_DIRECTION,
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APCI1500_RW_PORT_B_SPECIAL_IO_CONTROL,
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APCI1500_RW_PORT_B_PATTERN_POLARITY,
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APCI1500_RW_PORT_B_PATTERN_TRANSITION,
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APCI1500_RW_PORT_B_PATTERN_MASK
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};
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