* An EDAC driver for Cavium ThunderX RAS IP (Sergey Temerkhanov)
* Removal of DRAM error reporting through PCI SERR NMI (Borislav Petkov) * Misc small fixes (Jan Glauber, Thor Thayer) -----BEGIN PGP SIGNATURE----- iQIzBAABCAAdFiEEzv7L6UO9uDPlPSfHEsHwGGHeVUoFAlkGtO0ACgkQEsHwGGHe VUoXfA/+JLgcHpI04KcvJtTMpNWE3p04xLdzw7hvgvWPLg+JDHF1jXxA4HRy7usI BAsEZIcpyk/9tzYjKm4zc/8nhlrjx/ic9cU+hZa8zCy/47uArX9HlrsxAUpgVxcx YmWzZ2gyo9Jsi/44wZwnp4dNWibvyG5ECrgis7AFOihT1qyi74YajNfqJWWUbG/H W3DkCVs2JVzelue3rI9J8f9MSZk5sL3C9vfFWxk6ifiqr+rlUphoSNFdF+mRnBdr dvk555G4Xmmz97ZiBAOM12M1trn+4lCkyfuQuMw0cZYt7F/nS7ZdLqAKK8H1KIoE mGl29p85svZRhIM25Cd759LSharAetqpNyxicjAwONwLcKiXVf2UuR5NohVj3y1f Dbrh4zRx0OVJctaAKzLEHhW3Re/VA6lU8JUuvjBytKV5fr64jBpqSXFDL8J4y7p2 RJnKNbPkoXB75LukNqxDgpL+YEnJjzlslqxLqgPVgHFtrsUjpNHAJ9rKDeJQoW3b wC2wVBZmwx+4ShyHjJePJC7C6a/gDktbDos2/XW11DHa4w8ZbZ2Q4ep9oYegBKcd szliytm0LWlUTUDVNoc9DW/ka0NAh43kjvCqcmUcfC+4lhMO28eajvj35PP7fcic hmCAQnJz6M8t1VgxO7xvWi4jAwhvbzXM5IV1O3tIDMYHJQhrLBw= =vGf1 -----END PGP SIGNATURE----- Merge tag 'edac_for_4.12' of git://git.kernel.org/pub/scm/linux/kernel/git/bp/bp Pull EDAC updates from Borislav Petkov: - an EDAC driver for Cavium ThunderX RAS IP (Sergey Temerkhanov) - removal of DRAM error reporting through PCI SERR NMI (Borislav Petkov) - misc small fixes (Jan Glauber, Thor Thayer) * tag 'edac_for_4.12' of git://git.kernel.org/pub/scm/linux/kernel/git/bp/bp: EDAC, ghes: Do not enable it by default EDAC: Rename report status accessors EDAC: Delete edac_stub.c EDAC: Update Kconfig help text EDAC: Remove EDAC_MM_EDAC EDAC: Issue tracepoint only when it is defined ACPI/extlog: Add EDAC dependency EDAC: Move edac_op_state to edac_mc.c EDAC: Remove edac_err_assert EDAC: Get rid of edac_handlers x86/nmi, EDAC: Get rid of DRAM error reporting thru PCI SERR NMI EDAC, highbank: Align Makefile directives EDAC, thunderx: Remove unused code EDAC, thunderx: Change LMC index calculation EDAC, altera: Fix peripheral warnings for Cyclone5 EDAC, thunderx: Fix L2C MCI interrupt disable EDAC, thunderx: Add Cavium ThunderX EDAC driver
This commit is contained in:
Linus Torvalds
Коммит
89d1cf89c8
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@ -4715,6 +4715,7 @@ L: linux-edac@vger.kernel.org
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L: linux-mips@linux-mips.org
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S: Supported
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F: drivers/edac/octeon_edac*
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F: drivers/edac/thunderx_edac*
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EDAC-E752X
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M: Mark Gross <mark.gross@intel.com>
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@ -748,7 +748,6 @@ CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
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CONFIG_LEDS_TRIGGER_TRANSIENT=y
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CONFIG_LEDS_TRIGGER_CAMERA=y
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CONFIG_EDAC=y
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CONFIG_EDAC_MM_EDAC=y
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CONFIG_EDAC_HIGHBANK_MC=y
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CONFIG_EDAC_HIGHBANK_L2=y
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CONFIG_RTC_CLASS=y
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@ -635,8 +635,7 @@ CONFIG_LEDS_TRIGGER_GPIO=m
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CONFIG_LEDS_TRIGGER_DEFAULT_ON=m
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CONFIG_LEDS_TRIGGER_TRANSIENT=m
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CONFIG_LEDS_TRIGGER_CAMERA=m
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CONFIG_EDAC=y
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CONFIG_EDAC_MM_EDAC=m
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CONFIG_EDAC=m
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CONFIG_RTC_CLASS=y
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CONFIG_RTC_DEBUG=y
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CONFIG_RTC_DRV_DS1307=m
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@ -16,9 +16,8 @@ CONFIG_DAVICOM_PHY=y
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CONFIG_DMADEVICES=y
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CONFIG_E1000E=y
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CONFIG_E1000=y
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CONFIG_EDAC_MM_EDAC=y
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CONFIG_EDAC_MPC85XX=y
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CONFIG_EDAC=y
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CONFIG_EDAC_MPC85XX=y
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CONFIG_EEPROM_AT24=y
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CONFIG_EEPROM_LEGACY=y
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CONFIG_FB_FSL_DIU=y
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@ -155,7 +155,6 @@ CONFIG_USB_OHCI_HCD_PPC_OF_BE=y
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CONFIG_USB_OHCI_HCD_PPC_OF_LE=y
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CONFIG_USB_STORAGE=y
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CONFIG_EDAC=y
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CONFIG_EDAC_MM_EDAC=y
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CONFIG_EDAC_MPC85XX=y
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CONFIG_RTC_CLASS=y
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# CONFIG_RTC_INTF_PROC is not set
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@ -116,7 +116,6 @@ CONFIG_LEDS_TRIGGERS=y
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CONFIG_LEDS_TRIGGER_TIMER=y
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CONFIG_LEDS_TRIGGER_HEARTBEAT=y
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CONFIG_EDAC=y
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CONFIG_EDAC_MM_EDAC=y
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CONFIG_RTC_CLASS=y
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CONFIG_RTC_DRV_DS1307=y
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CONFIG_RTC_DRV_CMOS=y
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@ -179,7 +179,6 @@ CONFIG_INFINIBAND_MTHCA=m
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CONFIG_INFINIBAND_IPOIB=m
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CONFIG_INFINIBAND_IPOIB_DEBUG_DATA=y
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CONFIG_EDAC=y
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CONFIG_EDAC_MM_EDAC=y
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CONFIG_EDAC_CELL=y
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CONFIG_UIO=m
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CONFIG_EXT2_FS=y
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@ -142,7 +142,6 @@ CONFIG_USB_UHCI_HCD=y
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CONFIG_USB_SL811_HCD=y
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CONFIG_USB_STORAGE=y
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CONFIG_EDAC=y
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CONFIG_EDAC_MM_EDAC=y
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CONFIG_EDAC_PASEMI=y
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CONFIG_RTC_CLASS=y
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CONFIG_RTC_DRV_DS1307=y
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@ -262,7 +262,6 @@ CONFIG_INFINIBAND_IPOIB_CM=y
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CONFIG_INFINIBAND_SRP=m
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CONFIG_INFINIBAND_ISER=m
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CONFIG_EDAC=y
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CONFIG_EDAC_MM_EDAC=y
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CONFIG_EDAC_PASEMI=y
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CONFIG_RTC_CLASS=y
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CONFIG_RTC_DRV_DS1307=y
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@ -173,7 +173,6 @@ CONFIG_INFINIBAND_MTHCA=m
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CONFIG_INFINIBAND_IPOIB=m
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CONFIG_INFINIBAND_ISER=m
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CONFIG_EDAC=y
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CONFIG_EDAC_MM_EDAC=y
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CONFIG_RTC_CLASS=y
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CONFIG_RTC_DRV_DS1307=y
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CONFIG_FS_DAX=y
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@ -988,8 +988,7 @@ CONFIG_LEDS_TRIGGER_BACKLIGHT=m
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CONFIG_LEDS_TRIGGER_DEFAULT_ON=m
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CONFIG_ACCESSIBILITY=y
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CONFIG_A11Y_BRAILLE_CONSOLE=y
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CONFIG_EDAC=y
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CONFIG_EDAC_MM_EDAC=m
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CONFIG_EDAC=m
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CONFIG_RTC_CLASS=y
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# CONFIG_RTC_HCTOSYS is not set
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CONFIG_RTC_DRV_DS1307=m
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@ -249,7 +249,6 @@ CONFIG_USB_EHCI_HCD=y
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CONFIG_USB_OHCI_HCD=y
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CONFIG_USB_STORAGE=y
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CONFIG_EDAC=y
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CONFIG_EDAC_MM_EDAC=y
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CONFIG_RTC_CLASS=y
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CONFIG_RTC_DRV_TILE=y
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CONFIG_EXT2_FS=y
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@ -358,7 +358,6 @@ CONFIG_WATCHDOG_NOWAYOUT=y
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# CONFIG_VGA_ARB is not set
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# CONFIG_USB_SUPPORT is not set
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CONFIG_EDAC=y
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CONFIG_EDAC_MM_EDAC=y
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CONFIG_RTC_CLASS=y
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CONFIG_RTC_DRV_TILE=y
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CONFIG_EXT2_FS=y
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@ -222,17 +222,6 @@ pci_serr_error(unsigned char reason, struct pt_regs *regs)
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pr_emerg("NMI: PCI system error (SERR) for reason %02x on CPU %d.\n",
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reason, smp_processor_id());
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/*
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* On some machines, PCI SERR line is used to report memory
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* errors. EDAC makes use of it.
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*/
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#if defined(CONFIG_EDAC)
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if (edac_handler_set()) {
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edac_atomic_assert_error();
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return;
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}
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#endif
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if (panic_on_unrecovered_nmi)
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nmi_panic(regs, "NMI: Not continuing");
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@ -469,9 +469,8 @@ config ACPI_WATCHDOG
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config ACPI_EXTLOG
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tristate "Extended Error Log support"
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depends on X86_MCE && X86_LOCAL_APIC
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depends on X86_MCE && X86_LOCAL_APIC && EDAC
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select UEFI_CPER
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select RAS
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default n
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help
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Certain usages such as Predictive Failure Analysis (PFA) require
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@ -229,7 +229,7 @@ static int __init extlog_init(void)
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if (!(cap & MCG_ELOG_P) || !extlog_get_l1addr())
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return -ENODEV;
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if (get_edac_report_status() == EDAC_REPORTING_FORCE) {
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if (edac_get_report_status() == EDAC_REPORTING_FORCE) {
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pr_warn("Not loading eMCA, error reporting force-enabled through EDAC.\n");
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return -EPERM;
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}
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@ -285,8 +285,8 @@ static int __init extlog_init(void)
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* eMCA event report method has higher priority than EDAC method,
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* unless EDAC event report method is mandatory.
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*/
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old_edac_report_status = get_edac_report_status();
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set_edac_report_status(EDAC_REPORTING_DISABLED);
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old_edac_report_status = edac_get_report_status();
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edac_set_report_status(EDAC_REPORTING_DISABLED);
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mce_register_decode_chain(&extlog_mce_dec);
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/* enable OS to be involved to take over management from BIOS */
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((struct extlog_l1_head *)extlog_l1_addr)->flags |= FLAG_OS_OPTIN;
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@ -308,7 +308,7 @@ err:
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static void __exit extlog_exit(void)
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{
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set_edac_report_status(old_edac_report_status);
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edac_set_report_status(old_edac_report_status);
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mce_unregister_decode_chain(&extlog_mce_dec);
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((struct extlog_l1_head *)extlog_l1_addr)->flags &= ~FLAG_OS_OPTIN;
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if (extlog_l1_addr)
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@ -10,26 +10,16 @@ config EDAC_SUPPORT
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bool
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menuconfig EDAC
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bool "EDAC (Error Detection And Correction) reporting"
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depends on HAS_IOMEM && EDAC_SUPPORT
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tristate "EDAC (Error Detection And Correction) reporting"
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depends on HAS_IOMEM && EDAC_SUPPORT && RAS
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help
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EDAC is designed to report errors in the core system.
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These are low-level errors that are reported in the CPU or
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supporting chipset or other subsystems:
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EDAC is a subsystem along with hardware-specific drivers designed to
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report hardware errors. These are low-level errors that are reported
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in the CPU or supporting chipset or other subsystems:
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memory errors, cache errors, PCI errors, thermal throttling, etc..
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If unsure, select 'Y'.
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If this code is reporting problems on your system, please
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see the EDAC project web pages for more information at:
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<http://bluesmoke.sourceforge.net/>
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and:
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<http://buttersideup.com/edacwiki>
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There is also a mailing list for the EDAC project, which can
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be found via the sourceforge page.
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The mailing list for the EDAC project is linux-edac@vger.kernel.org.
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if EDAC
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@ -62,21 +52,9 @@ config EDAC_DECODE_MCE
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which occur really early upon boot, before the module infrastructure
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has been initialized.
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config EDAC_MM_EDAC
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tristate "Main Memory EDAC (Error Detection And Correction) reporting"
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select RAS
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help
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Some systems are able to detect and correct errors in main
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memory. EDAC can report statistics on memory error
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detection and correction (EDAC - or commonly referred to ECC
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errors). EDAC will also try to decode where these errors
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occurred so that a particular failing memory module can be
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replaced. If unsure, select 'Y'.
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config EDAC_GHES
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bool "Output ACPI APEI/GHES BIOS detected errors via EDAC"
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depends on ACPI_APEI_GHES && (EDAC_MM_EDAC=y)
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default y
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depends on ACPI_APEI_GHES && (EDAC=y)
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help
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Not all machines support hardware-driven error report. Some of those
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provide a BIOS-driven error report mechanism via ACPI, using the
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@ -98,7 +76,7 @@ config EDAC_GHES
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config EDAC_AMD64
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tristate "AMD64 (Opteron, Athlon64)"
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depends on EDAC_MM_EDAC && AMD_NB && EDAC_DECODE_MCE
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depends on AMD_NB && EDAC_DECODE_MCE
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help
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Support for error detection and correction of DRAM ECC errors on
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the AMD64 families (>= K8) of memory controllers.
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@ -124,28 +102,28 @@ config EDAC_AMD64_ERROR_INJECTION
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config EDAC_AMD76X
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tristate "AMD 76x (760, 762, 768)"
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depends on EDAC_MM_EDAC && PCI && X86_32
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depends on PCI && X86_32
|
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help
|
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Support for error detection and correction on the AMD 76x
|
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series of chipsets used with the Athlon processor.
|
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|
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config EDAC_E7XXX
|
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tristate "Intel e7xxx (e7205, e7500, e7501, e7505)"
|
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depends on EDAC_MM_EDAC && PCI && X86_32
|
||||
depends on PCI && X86_32
|
||||
help
|
||||
Support for error detection and correction on the Intel
|
||||
E7205, E7500, E7501 and E7505 server chipsets.
|
||||
|
||||
config EDAC_E752X
|
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tristate "Intel e752x (e7520, e7525, e7320) and 3100"
|
||||
depends on EDAC_MM_EDAC && PCI && X86
|
||||
depends on PCI && X86
|
||||
help
|
||||
Support for error detection and correction on the Intel
|
||||
E7520, E7525, E7320 server chipsets.
|
||||
|
||||
config EDAC_I82443BXGX
|
||||
tristate "Intel 82443BX/GX (440BX/GX)"
|
||||
depends on EDAC_MM_EDAC && PCI && X86_32
|
||||
depends on PCI && X86_32
|
||||
depends on BROKEN
|
||||
help
|
||||
Support for error detection and correction on the Intel
|
||||
|
|
@ -153,56 +131,56 @@ config EDAC_I82443BXGX
|
|||
|
||||
config EDAC_I82875P
|
||||
tristate "Intel 82875p (D82875P, E7210)"
|
||||
depends on EDAC_MM_EDAC && PCI && X86_32
|
||||
depends on PCI && X86_32
|
||||
help
|
||||
Support for error detection and correction on the Intel
|
||||
DP82785P and E7210 server chipsets.
|
||||
|
||||
config EDAC_I82975X
|
||||
tristate "Intel 82975x (D82975x)"
|
||||
depends on EDAC_MM_EDAC && PCI && X86
|
||||
depends on PCI && X86
|
||||
help
|
||||
Support for error detection and correction on the Intel
|
||||
DP82975x server chipsets.
|
||||
|
||||
config EDAC_I3000
|
||||
tristate "Intel 3000/3010"
|
||||
depends on EDAC_MM_EDAC && PCI && X86
|
||||
depends on PCI && X86
|
||||
help
|
||||
Support for error detection and correction on the Intel
|
||||
3000 and 3010 server chipsets.
|
||||
|
||||
config EDAC_I3200
|
||||
tristate "Intel 3200"
|
||||
depends on EDAC_MM_EDAC && PCI && X86
|
||||
depends on PCI && X86
|
||||
help
|
||||
Support for error detection and correction on the Intel
|
||||
3200 and 3210 server chipsets.
|
||||
|
||||
config EDAC_IE31200
|
||||
tristate "Intel e312xx"
|
||||
depends on EDAC_MM_EDAC && PCI && X86
|
||||
depends on PCI && X86
|
||||
help
|
||||
Support for error detection and correction on the Intel
|
||||
E3-1200 based DRAM controllers.
|
||||
|
||||
config EDAC_X38
|
||||
tristate "Intel X38"
|
||||
depends on EDAC_MM_EDAC && PCI && X86
|
||||
depends on PCI && X86
|
||||
help
|
||||
Support for error detection and correction on the Intel
|
||||
X38 server chipsets.
|
||||
|
||||
config EDAC_I5400
|
||||
tristate "Intel 5400 (Seaburg) chipsets"
|
||||
depends on EDAC_MM_EDAC && PCI && X86
|
||||
depends on PCI && X86
|
||||
help
|
||||
Support for error detection and correction the Intel
|
||||
i5400 MCH chipset (Seaburg).
|
||||
|
||||
config EDAC_I7CORE
|
||||
tristate "Intel i7 Core (Nehalem) processors"
|
||||
depends on EDAC_MM_EDAC && PCI && X86 && X86_MCE_INTEL
|
||||
depends on PCI && X86 && X86_MCE_INTEL
|
||||
help
|
||||
Support for error detection and correction the Intel
|
||||
i7 Core (Nehalem) Integrated Memory Controller that exists on
|
||||
|
|
@ -211,58 +189,56 @@ config EDAC_I7CORE
|
|||
|
||||
config EDAC_I82860
|
||||
tristate "Intel 82860"
|
||||
depends on EDAC_MM_EDAC && PCI && X86_32
|
||||
depends on PCI && X86_32
|
||||
help
|
||||
Support for error detection and correction on the Intel
|
||||
82860 chipset.
|
||||
|
||||
config EDAC_R82600
|
||||
tristate "Radisys 82600 embedded chipset"
|
||||
depends on EDAC_MM_EDAC && PCI && X86_32
|
||||
depends on PCI && X86_32
|
||||
help
|
||||
Support for error detection and correction on the Radisys
|
||||
82600 embedded chipset.
|
||||
|
||||
config EDAC_I5000
|
||||
tristate "Intel Greencreek/Blackford chipset"
|
||||
depends on EDAC_MM_EDAC && X86 && PCI
|
||||
depends on X86 && PCI
|
||||
help
|
||||
Support for error detection and correction the Intel
|
||||
Greekcreek/Blackford chipsets.
|
||||
|
||||
config EDAC_I5100
|
||||
tristate "Intel San Clemente MCH"
|
||||
depends on EDAC_MM_EDAC && X86 && PCI
|
||||
depends on X86 && PCI
|
||||
help
|
||||
Support for error detection and correction the Intel
|
||||
San Clemente MCH.
|
||||
|
||||
config EDAC_I7300
|
||||
tristate "Intel Clarksboro MCH"
|
||||
depends on EDAC_MM_EDAC && X86 && PCI
|
||||
depends on X86 && PCI
|
||||
help
|
||||
Support for error detection and correction the Intel
|
||||
Clarksboro MCH (Intel 7300 chipset).
|
||||
|
||||
config EDAC_SBRIDGE
|
||||
tristate "Intel Sandy-Bridge/Ivy-Bridge/Haswell Integrated MC"
|
||||
depends on EDAC_MM_EDAC && PCI && X86_64 && X86_MCE_INTEL
|
||||
depends on PCI_MMCONFIG
|
||||
depends on PCI && X86_64 && X86_MCE_INTEL && PCI_MMCONFIG
|
||||
help
|
||||
Support for error detection and correction the Intel
|
||||
Sandy Bridge, Ivy Bridge and Haswell Integrated Memory Controllers.
|
||||
|
||||
config EDAC_SKX
|
||||
tristate "Intel Skylake server Integrated MC"
|
||||
depends on EDAC_MM_EDAC && PCI && X86_64 && X86_MCE_INTEL
|
||||
depends on PCI_MMCONFIG
|
||||
depends on PCI && X86_64 && X86_MCE_INTEL && PCI_MMCONFIG
|
||||
help
|
||||
Support for error detection and correction the Intel
|
||||
Skylake server Integrated Memory Controllers.
|
||||
|
||||
config EDAC_PND2
|
||||
tristate "Intel Pondicherry2"
|
||||
depends on EDAC_MM_EDAC && PCI && X86_64 && X86_MCE_INTEL
|
||||
depends on PCI && X86_64 && X86_MCE_INTEL
|
||||
help
|
||||
Support for error detection and correction on the Intel
|
||||
Pondicherry2 Integrated Memory Controller. This SoC IP is
|
||||
|
|
@ -271,36 +247,35 @@ config EDAC_PND2
|
|||
|
||||
config EDAC_MPC85XX
|
||||
tristate "Freescale MPC83xx / MPC85xx"
|
||||
depends on EDAC_MM_EDAC && FSL_SOC
|
||||
depends on FSL_SOC
|
||||
help
|
||||
Support for error detection and correction on the Freescale
|
||||
MPC8349, MPC8560, MPC8540, MPC8548, T4240
|
||||
|
||||
config EDAC_LAYERSCAPE
|
||||
tristate "Freescale Layerscape DDR"
|
||||
depends on EDAC_MM_EDAC && ARCH_LAYERSCAPE
|
||||
depends on ARCH_LAYERSCAPE
|
||||
help
|
||||
Support for error detection and correction on Freescale memory
|
||||
controllers on Layerscape SoCs.
|
||||
|
||||
config EDAC_MV64X60
|
||||
tristate "Marvell MV64x60"
|
||||
depends on EDAC_MM_EDAC && MV64X60
|
||||
depends on MV64X60
|
||||
help
|
||||
Support for error detection and correction on the Marvell
|
||||
MV64360 and MV64460 chipsets.
|
||||
|
||||
config EDAC_PASEMI
|
||||
tristate "PA Semi PWRficient"
|
||||
depends on EDAC_MM_EDAC && PCI
|
||||
depends on PPC_PASEMI
|
||||
depends on PPC_PASEMI && PCI
|
||||
help
|
||||
Support for error detection and correction on PA Semi
|
||||
PWRficient.
|
||||
|
||||
config EDAC_CELL
|
||||
tristate "Cell Broadband Engine memory controller"
|
||||
depends on EDAC_MM_EDAC && PPC_CELL_COMMON
|
||||
depends on PPC_CELL_COMMON
|
||||
help
|
||||
Support for error detection and correction on the
|
||||
Cell Broadband Engine internal memory controller
|
||||
|
|
@ -308,7 +283,7 @@ config EDAC_CELL
|
|||
|
||||
config EDAC_PPC4XX
|
||||
tristate "PPC4xx IBM DDR2 Memory Controller"
|
||||
depends on EDAC_MM_EDAC && 4xx
|
||||
depends on 4xx
|
||||
help
|
||||
This enables support for EDAC on the ECC memory used
|
||||
with the IBM DDR2 memory controller found in various
|
||||
|
|
@ -317,7 +292,7 @@ config EDAC_PPC4XX
|
|||
|
||||
config EDAC_AMD8131
|
||||
tristate "AMD8131 HyperTransport PCI-X Tunnel"
|
||||
depends on EDAC_MM_EDAC && PCI && PPC_MAPLE
|
||||
depends on PCI && PPC_MAPLE
|
||||
help
|
||||
Support for error detection and correction on the
|
||||
AMD8131 HyperTransport PCI-X Tunnel chip.
|
||||
|
|
@ -326,7 +301,7 @@ config EDAC_AMD8131
|
|||
|
||||
config EDAC_AMD8111
|
||||
tristate "AMD8111 HyperTransport I/O Hub"
|
||||
depends on EDAC_MM_EDAC && PCI && PPC_MAPLE
|
||||
depends on PCI && PPC_MAPLE
|
||||
help
|
||||
Support for error detection and correction on the
|
||||
AMD8111 HyperTransport I/O Hub chip.
|
||||
|
|
@ -335,7 +310,7 @@ config EDAC_AMD8111
|
|||
|
||||
config EDAC_CPC925
|
||||
tristate "IBM CPC925 Memory Controller (PPC970FX)"
|
||||
depends on EDAC_MM_EDAC && PPC64
|
||||
depends on PPC64
|
||||
help
|
||||
Support for error detection and correction on the
|
||||
IBM CPC925 Bridge and Memory Controller, which is
|
||||
|
|
@ -344,7 +319,7 @@ config EDAC_CPC925
|
|||
|
||||
config EDAC_TILE
|
||||
tristate "Tilera Memory Controller"
|
||||
depends on EDAC_MM_EDAC && TILE
|
||||
depends on TILE
|
||||
default y
|
||||
help
|
||||
Support for error detection and correction on the
|
||||
|
|
@ -352,49 +327,59 @@ config EDAC_TILE
|
|||
|
||||
config EDAC_HIGHBANK_MC
|
||||
tristate "Highbank Memory Controller"
|
||||
depends on EDAC_MM_EDAC && ARCH_HIGHBANK
|
||||
depends on ARCH_HIGHBANK
|
||||
help
|
||||
Support for error detection and correction on the
|
||||
Calxeda Highbank memory controller.
|
||||
|
||||
config EDAC_HIGHBANK_L2
|
||||
tristate "Highbank L2 Cache"
|
||||
depends on EDAC_MM_EDAC && ARCH_HIGHBANK
|
||||
depends on ARCH_HIGHBANK
|
||||
help
|
||||
Support for error detection and correction on the
|
||||
Calxeda Highbank memory controller.
|
||||
|
||||
config EDAC_OCTEON_PC
|
||||
tristate "Cavium Octeon Primary Caches"
|
||||
depends on EDAC_MM_EDAC && CPU_CAVIUM_OCTEON
|
||||
depends on CPU_CAVIUM_OCTEON
|
||||
help
|
||||
Support for error detection and correction on the primary caches of
|
||||
the cnMIPS cores of Cavium Octeon family SOCs.
|
||||
|
||||
config EDAC_OCTEON_L2C
|
||||
tristate "Cavium Octeon Secondary Caches (L2C)"
|
||||
depends on EDAC_MM_EDAC && CAVIUM_OCTEON_SOC
|
||||
depends on CAVIUM_OCTEON_SOC
|
||||
help
|
||||
Support for error detection and correction on the
|
||||
Cavium Octeon family of SOCs.
|
||||
|
||||
config EDAC_OCTEON_LMC
|
||||
tristate "Cavium Octeon DRAM Memory Controller (LMC)"
|
||||
depends on EDAC_MM_EDAC && CAVIUM_OCTEON_SOC
|
||||
depends on CAVIUM_OCTEON_SOC
|
||||
help
|
||||
Support for error detection and correction on the
|
||||
Cavium Octeon family of SOCs.
|
||||
|
||||
config EDAC_OCTEON_PCI
|
||||
tristate "Cavium Octeon PCI Controller"
|
||||
depends on EDAC_MM_EDAC && PCI && CAVIUM_OCTEON_SOC
|
||||
depends on PCI && CAVIUM_OCTEON_SOC
|
||||
help
|
||||
Support for error detection and correction on the
|
||||
Cavium Octeon family of SOCs.
|
||||
|
||||
config EDAC_THUNDERX
|
||||
tristate "Cavium ThunderX EDAC"
|
||||
depends on ARM64
|
||||
depends on PCI
|
||||
help
|
||||
Support for error detection and correction on the
|
||||
Cavium ThunderX memory controllers (LMC), Cache
|
||||
Coherent Processor Interconnect (CCPI) and L2 cache
|
||||
blocks (TAD, CBC, MCI).
|
||||
|
||||
config EDAC_ALTERA
|
||||
bool "Altera SOCFPGA ECC"
|
||||
depends on EDAC_MM_EDAC=y && ARCH_SOCFPGA
|
||||
depends on EDAC=y && ARCH_SOCFPGA
|
||||
help
|
||||
Support for error detection and correction on the
|
||||
Altera SOCs. This must be selected for SDRAM ECC.
|
||||
|
|
@ -460,14 +445,14 @@ config EDAC_ALTERA_SDMMC
|
|||
|
||||
config EDAC_SYNOPSYS
|
||||
tristate "Synopsys DDR Memory Controller"
|
||||
depends on EDAC_MM_EDAC && ARCH_ZYNQ
|
||||
depends on ARCH_ZYNQ
|
||||
help
|
||||
Support for error detection and correction on the Synopsys DDR
|
||||
memory controller.
|
||||
|
||||
config EDAC_XGENE
|
||||
tristate "APM X-Gene SoC"
|
||||
depends on EDAC_MM_EDAC && (ARM64 || COMPILE_TEST)
|
||||
depends on (ARM64 || COMPILE_TEST)
|
||||
help
|
||||
Support for error detection and correction on the
|
||||
APM X-Gene family of SOCs.
|
||||
|
|
|
|||
|
|
@ -6,8 +6,7 @@
|
|||
# GNU General Public License.
|
||||
#
|
||||
|
||||
obj-$(CONFIG_EDAC) := edac_stub.o
|
||||
obj-$(CONFIG_EDAC_MM_EDAC) += edac_core.o
|
||||
obj-$(CONFIG_EDAC) := edac_core.o
|
||||
|
||||
edac_core-y := edac_mc.o edac_device.o edac_mc_sysfs.o
|
||||
edac_core-y += edac_module.o edac_device_sysfs.o wq.o
|
||||
|
|
@ -67,13 +66,14 @@ obj-$(CONFIG_EDAC_AMD8131) += amd8131_edac.o
|
|||
|
||||
obj-$(CONFIG_EDAC_TILE) += tile_edac.o
|
||||
|
||||
obj-$(CONFIG_EDAC_HIGHBANK_MC) += highbank_mc_edac.o
|
||||
obj-$(CONFIG_EDAC_HIGHBANK_L2) += highbank_l2_edac.o
|
||||
obj-$(CONFIG_EDAC_HIGHBANK_MC) += highbank_mc_edac.o
|
||||
obj-$(CONFIG_EDAC_HIGHBANK_L2) += highbank_l2_edac.o
|
||||
|
||||
obj-$(CONFIG_EDAC_OCTEON_PC) += octeon_edac-pc.o
|
||||
obj-$(CONFIG_EDAC_OCTEON_L2C) += octeon_edac-l2c.o
|
||||
obj-$(CONFIG_EDAC_OCTEON_LMC) += octeon_edac-lmc.o
|
||||
obj-$(CONFIG_EDAC_OCTEON_PCI) += octeon_edac-pci.o
|
||||
obj-$(CONFIG_EDAC_THUNDERX) += thunderx_edac.o
|
||||
|
||||
obj-$(CONFIG_EDAC_ALTERA) += altera_edac.o
|
||||
obj-$(CONFIG_EDAC_SYNOPSYS) += synopsys_edac.o
|
||||
|
|
|
|||
|
|
@ -1023,13 +1023,23 @@ out:
|
|||
return ret;
|
||||
}
|
||||
|
||||
static int socfpga_is_a10(void)
|
||||
{
|
||||
return of_machine_is_compatible("altr,socfpga-arria10");
|
||||
}
|
||||
|
||||
static int validate_parent_available(struct device_node *np);
|
||||
static const struct of_device_id altr_edac_a10_device_of_match[];
|
||||
static int __init __maybe_unused altr_init_a10_ecc_device_type(char *compat)
|
||||
{
|
||||
int irq;
|
||||
struct device_node *child, *np = of_find_compatible_node(NULL, NULL,
|
||||
"altr,socfpga-a10-ecc-manager");
|
||||
struct device_node *child, *np;
|
||||
|
||||
if (!socfpga_is_a10())
|
||||
return -ENODEV;
|
||||
|
||||
np = of_find_compatible_node(NULL, NULL,
|
||||
"altr,socfpga-a10-ecc-manager");
|
||||
if (!np) {
|
||||
edac_printk(KERN_ERR, EDAC_DEVICE, "ECC Manager not found\n");
|
||||
return -ENODEV;
|
||||
|
|
@ -1545,8 +1555,12 @@ static const struct edac_device_prv_data a10_sdmmceccb_data = {
|
|||
static int __init socfpga_init_sdmmc_ecc(void)
|
||||
{
|
||||
int rc = -ENODEV;
|
||||
struct device_node *child = of_find_compatible_node(NULL, NULL,
|
||||
"altr,socfpga-sdmmc-ecc");
|
||||
struct device_node *child;
|
||||
|
||||
if (!socfpga_is_a10())
|
||||
return -ENODEV;
|
||||
|
||||
child = of_find_compatible_node(NULL, NULL, "altr,socfpga-sdmmc-ecc");
|
||||
if (!child) {
|
||||
edac_printk(KERN_WARNING, EDAC_DEVICE, "SDMMC node not found\n");
|
||||
return -ENODEV;
|
||||
|
|
|
|||
|
|
@ -40,6 +40,11 @@
|
|||
#define edac_atomic_scrub(va, size) do { } while (0)
|
||||
#endif
|
||||
|
||||
int edac_op_state = EDAC_OPSTATE_INVAL;
|
||||
EXPORT_SYMBOL_GPL(edac_op_state);
|
||||
|
||||
static int edac_report = EDAC_REPORTING_ENABLED;
|
||||
|
||||
/* lock to memory controller's control array */
|
||||
static DEFINE_MUTEX(mem_ctls_mutex);
|
||||
static LIST_HEAD(mc_devices);
|
||||
|
|
@ -52,6 +57,65 @@ static void const *edac_mc_owner;
|
|||
|
||||
static struct bus_type mc_bus[EDAC_MAX_MCS];
|
||||
|
||||
int edac_get_report_status(void)
|
||||
{
|
||||
return edac_report;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(edac_get_report_status);
|
||||
|
||||
void edac_set_report_status(int new)
|
||||
{
|
||||
if (new == EDAC_REPORTING_ENABLED ||
|
||||
new == EDAC_REPORTING_DISABLED ||
|
||||
new == EDAC_REPORTING_FORCE)
|
||||
edac_report = new;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(edac_set_report_status);
|
||||
|
||||
static int edac_report_set(const char *str, const struct kernel_param *kp)
|
||||
{
|
||||
if (!str)
|
||||
return -EINVAL;
|
||||
|
||||
if (!strncmp(str, "on", 2))
|
||||
edac_report = EDAC_REPORTING_ENABLED;
|
||||
else if (!strncmp(str, "off", 3))
|
||||
edac_report = EDAC_REPORTING_DISABLED;
|
||||
else if (!strncmp(str, "force", 5))
|
||||
edac_report = EDAC_REPORTING_FORCE;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int edac_report_get(char *buffer, const struct kernel_param *kp)
|
||||
{
|
||||
int ret = 0;
|
||||
|
||||
switch (edac_report) {
|
||||
case EDAC_REPORTING_ENABLED:
|
||||
ret = sprintf(buffer, "on");
|
||||
break;
|
||||
case EDAC_REPORTING_DISABLED:
|
||||
ret = sprintf(buffer, "off");
|
||||
break;
|
||||
case EDAC_REPORTING_FORCE:
|
||||
ret = sprintf(buffer, "force");
|
||||
break;
|
||||
default:
|
||||
ret = -EINVAL;
|
||||
break;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static const struct kernel_param_ops edac_report_ops = {
|
||||
.set = edac_report_set,
|
||||
.get = edac_report_get,
|
||||
};
|
||||
|
||||
module_param_cb(edac_report, &edac_report_ops, &edac_report, 0644);
|
||||
|
||||
unsigned edac_dimm_info_location(struct dimm_info *dimm, char *buf,
|
||||
unsigned len)
|
||||
{
|
||||
|
|
@ -504,22 +568,6 @@ struct mem_ctl_info *find_mci_by_dev(struct device *dev)
|
|||
}
|
||||
EXPORT_SYMBOL_GPL(find_mci_by_dev);
|
||||
|
||||
/*
|
||||
* handler for EDAC to check if NMI type handler has asserted interrupt
|
||||
*/
|
||||
static int edac_mc_assert_error_check_and_clear(void)
|
||||
{
|
||||
int old_state;
|
||||
|
||||
if (edac_op_state == EDAC_OPSTATE_POLL)
|
||||
return 1;
|
||||
|
||||
old_state = edac_err_assert;
|
||||
edac_err_assert = 0;
|
||||
|
||||
return old_state;
|
||||
}
|
||||
|
||||
/*
|
||||
* edac_mc_workq_function
|
||||
* performs the operation scheduled by a workq request
|
||||
|
|
@ -536,7 +584,7 @@ static void edac_mc_workq_function(struct work_struct *work_req)
|
|||
return;
|
||||
}
|
||||
|
||||
if (edac_mc_assert_error_check_and_clear())
|
||||
if (edac_op_state == EDAC_OPSTATE_POLL)
|
||||
mci->edac_check(mci);
|
||||
|
||||
mutex_unlock(&mem_ctls_mutex);
|
||||
|
|
@ -601,7 +649,6 @@ static int add_mc_to_global_list(struct mem_ctl_info *mci)
|
|||
}
|
||||
|
||||
list_add_tail_rcu(&mci->link, insert_before);
|
||||
atomic_inc(&edac_handlers);
|
||||
return 0;
|
||||
|
||||
fail0:
|
||||
|
|
@ -619,7 +666,6 @@ fail1:
|
|||
|
||||
static int del_mc_from_global_list(struct mem_ctl_info *mci)
|
||||
{
|
||||
int handlers = atomic_dec_return(&edac_handlers);
|
||||
list_del_rcu(&mci->link);
|
||||
|
||||
/* these are for safe removal of devices from global list while
|
||||
|
|
@ -628,7 +674,7 @@ static int del_mc_from_global_list(struct mem_ctl_info *mci)
|
|||
synchronize_rcu();
|
||||
INIT_LIST_HEAD(&mci->link);
|
||||
|
||||
return handlers;
|
||||
return list_empty(&mc_devices);
|
||||
}
|
||||
|
||||
struct mem_ctl_info *edac_mc_find(int idx)
|
||||
|
|
@ -763,7 +809,7 @@ struct mem_ctl_info *edac_mc_del_mc(struct device *dev)
|
|||
/* mark MCI offline: */
|
||||
mci->op_state = OP_OFFLINE;
|
||||
|
||||
if (!del_mc_from_global_list(mci))
|
||||
if (del_mc_from_global_list(mci))
|
||||
edac_mc_owner = NULL;
|
||||
|
||||
mutex_unlock(&mem_ctls_mutex);
|
||||
|
|
@ -1195,10 +1241,13 @@ void edac_mc_handle_error(const enum hw_event_mc_err_type type,
|
|||
|
||||
/* Report the error via the trace interface */
|
||||
grain_bits = fls_long(e->grain) + 1;
|
||||
trace_mc_event(type, e->msg, e->label, e->error_count,
|
||||
mci->mc_idx, e->top_layer, e->mid_layer, e->low_layer,
|
||||
(e->page_frame_number << PAGE_SHIFT) | e->offset_in_page,
|
||||
grain_bits, e->syndrome, e->other_detail);
|
||||
|
||||
if (IS_ENABLED(CONFIG_RAS))
|
||||
trace_mc_event(type, e->msg, e->label, e->error_count,
|
||||
mci->mc_idx, e->top_layer, e->mid_layer,
|
||||
e->low_layer,
|
||||
(e->page_frame_number << PAGE_SHIFT) | e->offset_in_page,
|
||||
grain_bits, e->syndrome, e->other_detail);
|
||||
|
||||
edac_raw_mc_handle_error(type, mci, e);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,68 +0,0 @@
|
|||
/*
|
||||
* common EDAC components that must be in kernel
|
||||
*
|
||||
* Author: Dave Jiang <djiang@mvista.com>
|
||||
*
|
||||
* 2007 (c) MontaVista Software, Inc.
|
||||
* 2010 (c) Advanced Micro Devices Inc.
|
||||
* Borislav Petkov <bp@alien8.de>
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without any
|
||||
* warranty of any kind, whether express or implied.
|
||||
*
|
||||
*/
|
||||
#include <linux/module.h>
|
||||
#include <linux/edac.h>
|
||||
#include <linux/atomic.h>
|
||||
#include <linux/device.h>
|
||||
|
||||
int edac_op_state = EDAC_OPSTATE_INVAL;
|
||||
EXPORT_SYMBOL_GPL(edac_op_state);
|
||||
|
||||
atomic_t edac_handlers = ATOMIC_INIT(0);
|
||||
EXPORT_SYMBOL_GPL(edac_handlers);
|
||||
|
||||
int edac_err_assert = 0;
|
||||
EXPORT_SYMBOL_GPL(edac_err_assert);
|
||||
|
||||
int edac_report_status = EDAC_REPORTING_ENABLED;
|
||||
EXPORT_SYMBOL_GPL(edac_report_status);
|
||||
|
||||
static int __init edac_report_setup(char *str)
|
||||
{
|
||||
if (!str)
|
||||
return -EINVAL;
|
||||
|
||||
if (!strncmp(str, "on", 2))
|
||||
set_edac_report_status(EDAC_REPORTING_ENABLED);
|
||||
else if (!strncmp(str, "off", 3))
|
||||
set_edac_report_status(EDAC_REPORTING_DISABLED);
|
||||
else if (!strncmp(str, "force", 5))
|
||||
set_edac_report_status(EDAC_REPORTING_FORCE);
|
||||
|
||||
return 0;
|
||||
}
|
||||
__setup("edac_report=", edac_report_setup);
|
||||
|
||||
/*
|
||||
* called to determine if there is an EDAC driver interested in
|
||||
* knowing an event (such as NMI) occurred
|
||||
*/
|
||||
int edac_handler_set(void)
|
||||
{
|
||||
if (edac_op_state == EDAC_OPSTATE_POLL)
|
||||
return 0;
|
||||
|
||||
return atomic_read(&edac_handlers);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(edac_handler_set);
|
||||
|
||||
/*
|
||||
* handler for NMI type of interrupts to assert error
|
||||
*/
|
||||
void edac_atomic_assert_error(void)
|
||||
{
|
||||
edac_err_assert++;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(edac_atomic_assert_error);
|
||||
|
|
@ -1349,7 +1349,7 @@ static int pnd2_mce_check_error(struct notifier_block *nb, unsigned long val, vo
|
|||
struct dram_addr daddr;
|
||||
char *type;
|
||||
|
||||
if (get_edac_report_status() == EDAC_REPORTING_DISABLED)
|
||||
if (edac_get_report_status() == EDAC_REPORTING_DISABLED)
|
||||
return NOTIFY_DONE;
|
||||
|
||||
mci = pnd2_mci;
|
||||
|
|
|
|||
|
|
@ -3075,7 +3075,7 @@ static int sbridge_mce_check_error(struct notifier_block *nb, unsigned long val,
|
|||
struct sbridge_pvt *pvt;
|
||||
char *type;
|
||||
|
||||
if (get_edac_report_status() == EDAC_REPORTING_DISABLED)
|
||||
if (edac_get_report_status() == EDAC_REPORTING_DISABLED)
|
||||
return NOTIFY_DONE;
|
||||
|
||||
mci = get_mci_for_node_id(mce->socketid);
|
||||
|
|
@ -3441,7 +3441,7 @@ static int __init sbridge_init(void)
|
|||
|
||||
if (rc >= 0) {
|
||||
mce_register_decode_chain(&sbridge_mce_dec);
|
||||
if (get_edac_report_status() == EDAC_REPORTING_DISABLED)
|
||||
if (edac_get_report_status() == EDAC_REPORTING_DISABLED)
|
||||
sbridge_printk(KERN_WARNING, "Loading driver, error reporting disabled.\n");
|
||||
return 0;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -971,7 +971,7 @@ static int skx_mce_check_error(struct notifier_block *nb, unsigned long val,
|
|||
struct mem_ctl_info *mci;
|
||||
char *type;
|
||||
|
||||
if (get_edac_report_status() == EDAC_REPORTING_DISABLED)
|
||||
if (edac_get_report_status() == EDAC_REPORTING_DISABLED)
|
||||
return NOTIFY_DONE;
|
||||
|
||||
/* ignore unless this is memory related with an address */
|
||||
|
|
|
|||
Разница между файлами не показана из-за своего большого размера
Загрузить разницу
|
|
@ -28,12 +28,10 @@ struct device;
|
|||
#define EDAC_OPSTATE_INT 2
|
||||
|
||||
extern int edac_op_state;
|
||||
extern int edac_err_assert;
|
||||
extern atomic_t edac_handlers;
|
||||
|
||||
extern int edac_handler_set(void);
|
||||
extern void edac_atomic_assert_error(void);
|
||||
extern struct bus_type *edac_get_sysfs_subsys(void);
|
||||
struct bus_type *edac_get_sysfs_subsys(void);
|
||||
int edac_get_report_status(void);
|
||||
void edac_set_report_status(int new);
|
||||
|
||||
enum {
|
||||
EDAC_REPORTING_ENABLED,
|
||||
|
|
@ -41,28 +39,6 @@ enum {
|
|||
EDAC_REPORTING_FORCE
|
||||
};
|
||||
|
||||
extern int edac_report_status;
|
||||
#ifdef CONFIG_EDAC
|
||||
static inline int get_edac_report_status(void)
|
||||
{
|
||||
return edac_report_status;
|
||||
}
|
||||
|
||||
static inline void set_edac_report_status(int new)
|
||||
{
|
||||
edac_report_status = new;
|
||||
}
|
||||
#else
|
||||
static inline int get_edac_report_status(void)
|
||||
{
|
||||
return EDAC_REPORTING_DISABLED;
|
||||
}
|
||||
|
||||
static inline void set_edac_report_status(int new)
|
||||
{
|
||||
}
|
||||
#endif
|
||||
|
||||
static inline void opstate_init(void)
|
||||
{
|
||||
switch (edac_op_state) {
|
||||
|
|
|
|||
Загрузка…
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